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https://github.com/openhwgroup/cve2.git
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Cleanup unneeded signals and dead code
This commit is contained in:
Sven Stucki
parent
e305a8e648
commit
82eaaf86be
3 changed files with 45 additions and 105 deletions
113
controller.sv
113
controller.sv
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@ -64,7 +64,7 @@ module controller
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output logic mult_mac_en_o, // Use the accumulator after multiplication
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output logic regfile_we_o, // Write Enable to regfile
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output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations
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output logic regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations
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output logic regfile_alu_we_o, // Write Enable to regfile 2nd port
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@ -163,23 +163,21 @@ module controller
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logic trap_insn;
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logic deassert_we;
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logic lsu_stall;
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logic misalign_stall;
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logic instr_ack_stall;
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logic load_stall;
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logic jr_stall;
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logic trap_stall;
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logic lsu_stall;
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logic misalign_stall;
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logic instr_ack_stall;
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logic load_stall;
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logic jr_stall;
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logic trap_stall;
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`ifdef BRANCH_PREDICTION
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logic wrong_branch_taken;
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`endif
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logic rega_used;
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logic regb_used;
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logic regc_used;
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logic rega_used;
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logic regb_used;
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logic regc_used;
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logic halt_if;
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logic halt_id;
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logic illegal_insn_int;
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logic halt_if;
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logic halt_id;
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logic illegal_insn_int;
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/////////////////////////////////////////////
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// ____ _ //
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@ -189,9 +187,9 @@ module controller
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// |____/ \___|\___\___/ \__,_|\___|_| //
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// //
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/////////////////////////////////////////////
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always_comb
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begin
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// Default values
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jump_in_id = `BRANCH_NONE;
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alu_operator = `ALU_NOP;
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@ -210,7 +208,7 @@ module controller
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regfile_we = 1'b0;
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regfile_alu_we = 1'b0;
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regfile_alu_waddr_mux_sel_o = 2'b01;
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regfile_alu_waddr_mux_sel_o = 1'b1;
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prepost_useincr_o = 1'b1;
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@ -238,10 +236,6 @@ module controller
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regb_used = 1'b0;
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regc_used = 1'b0;
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`ifdef BRANCH_PREDICTION
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wrong_branch_taken_o = 1'b0;
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take_branch_o = 1'b0;
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`endif
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unique case (instr_rdata_i[6:0])
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@ -256,7 +250,6 @@ module controller
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`OPCODE_JAL: begin // Jump and Link
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if (instr_rdata_i ==? `INSTR_JAL) begin
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// Insert bubbles
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jump_in_id = `BRANCH_JAL;
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// Calculate and store PC+4
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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@ -273,7 +266,6 @@ module controller
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`OPCODE_JALR: begin // Jump and Link Register
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if (instr_rdata_i ==? `INSTR_JALR) begin
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// Insert bubbles
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jump_in_id = `BRANCH_JALR;
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// Calculate and store PC+4
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alu_op_a_mux_sel_o = `OP_A_CURRPC;
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@ -306,7 +298,7 @@ module controller
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default: begin
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illegal_insn_int = 1'b1;
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end
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endcase // case (instr_rdata_i)
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endcase
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end
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@ -321,16 +313,16 @@ module controller
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`OPCODE_STORE,
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`OPCODE_STORE_POST: begin
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data_req = 1'b1;
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data_we = 1'b1;
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rega_used = 1'b1;
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regb_used = 1'b1;
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alu_operator = `ALU_ADD;
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data_req = 1'b1;
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data_we = 1'b1;
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rega_used = 1'b1;
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regb_used = 1'b1;
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alu_operator = `ALU_ADD;
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// post-increment setup
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if (instr_rdata_i[6:0] == `OPCODE_STORE_POST) begin
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prepost_useincr_o = 1'b0;
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regfile_alu_waddr_mux_sel_o = 2'b00;
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regfile_alu_waddr_mux_sel_o = 1'b0;
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regfile_alu_we = 1'b1;
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end
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@ -359,20 +351,20 @@ module controller
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`OPCODE_LOAD,
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`OPCODE_LOAD_POST: begin
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data_req = 1'b1;
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regfile_we = 1'b1;
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rega_used = 1'b1;
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data_type_o = 2'b00;
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data_req = 1'b1;
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regfile_we = 1'b1;
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rega_used = 1'b1;
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data_type_o = 2'b00;
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// offset from immediate
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alu_operator = `ALU_ADD;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_I;
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alu_operator = `ALU_ADD;
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_I;
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// post-increment setup
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if (instr_rdata_i[6:0] == `OPCODE_LOAD_POST) begin
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prepost_useincr_o = 1'b0;
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regfile_alu_waddr_mux_sel_o = 2'b00;
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regfile_alu_waddr_mux_sel_o = 1'b0;
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regfile_alu_we = 1'b1;
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end
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@ -509,7 +501,7 @@ module controller
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regfile_alu_we = 1'b0;
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illegal_insn_int = 1'b1;
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end
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endcase // unique case (instr_rdata_i)
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endcase
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end
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/*
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@ -523,34 +515,13 @@ module controller
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regfile_alu_we = 1'b1;
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casex (instr_rdata_i[3:0])
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4'b0XXX: begin // Standard Operation
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alu_operator = {3'b000, instr_rdata_i[2:0]};
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if ((instr_rdata_i[2:0] ==? 3'b00X) || (instr_rdata_i[2:0] == 3'b010)) begin // l.add, l.addc & l.sub
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set_overflow = 1'b1;
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set_carry = 1'b1;
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end
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end
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4'b1000: begin // Shift Operation
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alu_operator = {4'b0010, instr_rdata_i[7:6]};
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end
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4'b110X: begin // l.ext{b,h,w}{s,z}
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alu_operator = {3'b010, instr_rdata_i[7:6], instr_rdata_i[0]};
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regb_used = 1'b0; // register b is not used
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end
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4'b1110: begin // l.cmov
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alu_operator = `ALU_CMOV;
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end
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4'b1111: begin // l.ff1
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alu_operator = `ALU_FF1;
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end
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default: begin
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// synopsys translate_off
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$display("%t: Illegal ALU instruction received.", $time);
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// synopsys translate_on
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regfile_alu_we = 1'b0; // disable Write Enable for illegal instruction
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illegal_insn_int = 1'b1;
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end
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endcase // casex (instr_rdata_i[3:2])
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end
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@ -598,26 +569,6 @@ module controller
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end
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endcase //~case(instr_rdata_i[3:0])
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end
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2'b11: begin // Multiplication
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if ((instr_rdata_i[3:0] == 4'b0110) || (instr_rdata_i[3:0] == 4'b1011))
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begin // Is multiplication and no division
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mult_is_running = 1'b1;
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if ((instr_rdata_i[3:0] == 4'b0110) || (instr_rdata_i[3:0] == 4'b1011)) // l.mul & l.mulu
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begin
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regfile_alu_we = 1'b1;
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regfile_alu_waddr_mux_sel_o = 2'b01;
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end
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end
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else
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begin
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// synopsys translate_off
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$display("%t: Division instruction received, this is not supported.", $time);
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// synopsys translate_on
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illegal_insn_int = 1'b1;
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end
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end
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endcase; // case (instr_rdata_i[9:8])
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end
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@ -10,7 +10,7 @@
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// Create Date: 08/08/2014 //
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// Design Name: hwloop regs //
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// Module Name: hwloop_regs.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Hardware loop registers //
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@ -23,8 +23,6 @@
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// //
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// //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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@ -55,9 +53,9 @@ module hwloop_regs
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);
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_regs_q;
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_regs_q;
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_regs_q;
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_regs_q;
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_end_regs_q;
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logic [`HWLOOP_REGS-1:0] [31:0] hwloop_counter_regs_q;
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int unsigned i;
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27
id_stage.sv
27
id_stage.sv
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@ -149,8 +149,8 @@ module id_stage
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input logic [31:0] regfile_alu_wdata_fw_i,
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_branch_o, // we are executing a branch instruction (bf, bnf)
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output logic perf_jump_o, // we are executing a jump instruction
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output logic perf_branch_o, // we are executing a branch instruction
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output logic perf_jr_stall_o, // jump-register-hazard
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output logic perf_ld_stall_o // load-use-hazard
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);
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@ -181,9 +181,6 @@ module id_stage
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logic irq_present;
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// Signals running between controller and exception controller
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logic [1:0] jump_in_ex; // registered copy of jump_in_id
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assign jump_in_ex_o = jump_in_ex;
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logic illegal_insn;
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logic illegal_c_insn;
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logic trap_insn;
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@ -192,7 +189,7 @@ module id_stage
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logic clear_isr_running;
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logic exc_pipe_flush;
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// Register file interface
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logic [4:0] regfile_addr_ra_id;
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logic [4:0] regfile_addr_rb_id;
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logic [4:0] regfile_addr_rc_id;
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@ -226,7 +223,7 @@ module id_stage
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// Register Write Control
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logic regfile_we_id;
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logic [1:0] regfile_alu_waddr_mux_sel; // TODO: FixMe -> 1bit
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logic regfile_alu_waddr_mux_sel;
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// Data Memory Control
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logic data_we_id;
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@ -302,14 +299,8 @@ module id_stage
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// Second Register Write Adress Selection
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// Used for prepost load/store and multiplier
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always_comb
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begin : alu_waddr_mux
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case (regfile_alu_waddr_mux_sel)
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default: regfile_alu_waddr_id = regfile_addr_ra_id;
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2'b00: regfile_alu_waddr_id = regfile_addr_ra_id;
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2'b01: regfile_alu_waddr_id = regfile_waddr_id;
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endcase
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end
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assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ?
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regfile_waddr_id : regfile_addr_ra_id;
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///////////////////////////////////////////////////////////////////////////////////////
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@ -682,7 +673,7 @@ module id_stage
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// Controller
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.core_busy_i ( core_busy_o ),
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.jump_in_id_i ( jump_in_id_o ),
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.jump_in_ex_i ( jump_in_ex ),
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.jump_in_ex_i ( jump_in_ex_o ),
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.stall_id_i ( stall_id_o ),
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.illegal_insn_i ( illegal_insn ),
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.trap_insn_i ( trap_insn ),
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@ -781,7 +772,7 @@ module id_stage
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hwloop_wb_mux_sel_ex_o <= 1'b0;
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hwloop_cnt_o <= 32'b0;
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jump_in_ex <= 2'b0;
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jump_in_ex_o <= 2'b0;
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end
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else if ((stall_ex_o == 1'b0) && (data_misaligned_i == 1'b1))
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@ -844,7 +835,7 @@ module id_stage
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hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel;
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hwloop_cnt_o <= hwloop_cnt;
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jump_in_ex <= jump_in_id_o;
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jump_in_ex_o <= jump_in_id_o;
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end
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end
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