The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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Daniel Mlynek 9d232d1cde Include assert macros when they are used
prim_assert.sv is a file containing assertion macros (defines).
Previously, prim_assert.sv was compiled as normal SystemVerilog file.
This made the defines available for the whole compilation unit as soon
as they were defined. Since all cores using prim_assert depended (in
fusesoc) on the lowrisc:prim:assert core, prim_assert was always
compiled first, and the defines were visible in subsequent files.

All of that is only true if all files end up in one comilation unit. The
SV standard states that what makes up a compilation unit is
tool-defined, but also states that typically, passing multiple files (or
a file list/.f file) to a single tool invocation means that all files
end up in one compilation unit; if the tool is called multiple times,
then the files end up in separate compilation units.

Edalize (the fusesoc backend) doesn't guarantee either behavior, and so
it happens that for Vivado, Verilator, Cadence and Synopsys simulators,
all files are compiled into a single compilation unit. But for Riviera,
each file is a separate compilation unit.

To avoid relying on the definition of compilation units, and to do the
generally right thing (TM), this commit changes the code to always
include the prim_assert.sv file when it is used in a source file.
Include guards are introduced in the prim_assert.sv file to avoid
defining things twice.
2020-01-28 14:46:48 +00:00
doc [rtl] Add FPGA Register File 2020-01-14 16:21:58 +01:00
dv Specify boot address in decimal 2020-01-28 14:46:48 +00:00
examples Simple System: Correctly tie-off unused signals 2020-01-28 14:46:48 +00:00
lint Include assert macros when they are used 2020-01-28 14:46:48 +00:00
rtl Include assert macros when they are used 2020-01-28 14:46:48 +00:00
shared Include assert macros when they are used 2020-01-28 14:46:48 +00:00
syn [syn] Feed ABC faster clock for better results 2020-01-23 17:41:52 +00:00
vendor Update google_riscv-dv to google/riscv-dv@a655f34 (#564) 2020-01-23 15:10:14 -08:00
.clang-format Add lowRISC standard clang-format file 2019-09-11 12:00:49 +01:00
.gitignore Update gitignore to include simple system files 2019-11-25 14:13:17 +01:00
azure-pipelines.yml [ci] Add clang-format checking to CI 2020-01-02 13:20:35 +01:00
CONTRIBUTING.md Fix vim setting suggestion 2019-06-19 14:39:41 +02:00
CREDITS.md Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
ibex_core.core [rtl] Add FPGA Register File 2020-01-14 16:21:58 +01:00
ibex_core_tracing.core [dv] Remove clock gating primitive in dv/uvm/tb 2019-11-16 00:25:32 +01:00
ibex_tracer.core [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
Makefile FPGA example: add support for the Arty A7-35 2020-01-27 20:18:17 +00:00
README.md [ci] Add clang-format checking to CI 2020-01-02 13:20:35 +01:00
src_files.yml [RTL] - Add PMP module 2019-08-29 17:43:37 +01:00

Build Status

Ibex RISC-V Core

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

The Ibex user manual can be read online at ReadTheDocs. It is also contained in the doc folder of this repository.

Contributing

We highly appreciate community contributions. To ease our work of reviewing your contributions, please:

  • Create your own branch to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the contribution guide.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.

When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style guide. All C and C++ code should be formatted with clang-format before committing. Either run clang-format -i filename.cc or git clang-format on added files.

To get started, please check out the "Good First Issue" list.

Issues and Troubleshooting

If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

Questions?

Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.

References

  1. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)