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https://github.com/openhwgroup/cve2.git
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Move compressed decoder/expander to IF stage
I.e. the decoder is now before the IF/ID pipeline It turns out there is enough timing budget to put it there and thus it simplifies timing in the ID stage
This commit is contained in:
Andreas Traber
parent
f5e1020f57
commit
b347299f31
3 changed files with 47 additions and 24 deletions
19
id_stage.sv
19
id_stage.sv
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@ -55,11 +55,12 @@ module id_stage
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output logic [31:0] jump_target_o,
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// IF and ID stage signals
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output logic compressed_instr_o,
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output logic [2:0] pc_mux_sel_o,
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output logic [1:0] exc_pc_mux_o,
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output logic force_nop_o,
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input logic illegal_c_insn_i,
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input logic [31:0] current_pc_if_i,
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input logic [31:0] current_pc_id_i,
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@ -140,6 +141,7 @@ module id_stage
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input logic [31:0] regfile_alu_wdata_fw_i,
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// Performance Counters
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output logic perf_compressed_o, // current instrution is compressed
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output logic perf_jump_o, // we are executing a jump instruction
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output logic perf_branch_o, // we are executing a branch instruction
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output logic perf_jr_stall_o, // jump-register-hazard
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@ -149,6 +151,7 @@ module id_stage
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// Compressed instruction decoding
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logic [31:0] instr;
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logic is_compressed;
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// Immediate decoding and sign extension
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logic [31:0] imm_i_type;
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@ -267,14 +270,10 @@ module id_stage
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assign pc_mux_sel_o = (exc_pc_sel == 1'b1) ? `PC_EXCEPTION : pc_mux_sel_int;
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// compressed instruction decoding
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compressed_decoder compressed_decoder_i (
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.instr_i ( instr_rdata_i ),
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.instr_o ( instr ),
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.is_compressed_o ( compressed_instr_o ),
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.illegal_instr_o ( illegal_c_insn )
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);
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assign instr = instr_rdata_i;
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assign is_compressed = (instr[1:0] != 2'b11);
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assign perf_compressed_o = is_compressed;
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// immediate extraction and sign extension
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assign imm_i_type = { {20 {instr[31]}}, instr[31:20] };
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@ -414,7 +413,7 @@ module id_stage
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`IMM_I: immediate_b = imm_i_type;
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`IMM_S: immediate_b = imm_s_type;
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`IMM_U: immediate_b = imm_u_type;
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`IMM_PCINCR: immediate_b = compressed_instr_o ? 32'h2 : 32'h4;
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`IMM_PCINCR: immediate_b = is_compressed ? 32'h2 : 32'h4;
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default: immediate_b = imm_i_type;
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endcase; // case (immediate_mux_sel)
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end
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@ -591,7 +590,7 @@ module id_stage
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.irq_present_i ( irq_present ),
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// Exception Controller Signals
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.illegal_c_insn_i ( illegal_c_insn ),
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.illegal_c_insn_i ( illegal_c_insn_i ),
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.illegal_insn_o ( illegal_insn ),
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.trap_insn_o ( trap_insn ),
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.pc_valid_i ( pc_valid ),
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29
if_stage.sv
29
if_stage.sv
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@ -55,6 +55,7 @@ module if_stage
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// Output of IF Pipeline stage
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output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding
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output logic illegal_c_insn_id_o, // compressed decoder thinks this is an invalid instruction
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output logic [31:0] current_pc_if_o,
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output logic [31:0] current_pc_id_o,
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@ -441,20 +442,40 @@ module if_stage
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offset_fsm_cs == UNALIGNED_16) || instr_req_o;
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// compressed instruction decoding, or more precisely compressed instruction
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// expander
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//
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// since it does not matter where we decompress instructions, we do it here
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// to ease timing closure
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logic [31:0] instr_decompressed;
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logic illegal_c_insn;
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compressed_decoder compressed_decoder_i
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(
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.instr_i ( instr_rdata_int ),
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.instr_o ( instr_decompressed ),
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.is_compressed_o ( ),
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.illegal_instr_o ( illegal_c_insn )
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);
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// IF-ID pipeline registers, frozen when the ID stage is stalled
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always_ff @(posedge clk, negedge rst_n)
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begin : IF_ID_PIPE_REGISTERS
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if (rst_n == 1'b0)
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begin
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instr_rdata_id_o <= '0;
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current_pc_id_o <= '0;
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instr_rdata_id_o <= '0;
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illegal_c_insn_id_o <= 1'b0;
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current_pc_id_o <= '0;
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end
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else
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begin
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if (~stall_id_i)
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begin : ENABLED_PIPE
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instr_rdata_id_o <= instr_rdata_int;
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current_pc_id_o <= current_pc_if_o;
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instr_rdata_id_o <= instr_decompressed;
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illegal_c_insn_id_o <= illegal_c_insn;
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current_pc_id_o <= current_pc_if_o;
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end
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end
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end
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@ -83,6 +83,7 @@ module riscv_core
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// IF/ID signals
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logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage
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logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
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logic [31:0] current_pc_if; // Current Program counter
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logic [31:0] current_pc_id; // Current Program counter
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logic force_nop_id;
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@ -90,7 +91,7 @@ module riscv_core
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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// ID performance counter signals
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logic compressed_instr;
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logic perf_compressed;
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logic is_decoding;
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@ -240,9 +241,10 @@ module riscv_core
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.instr_rdata_i ( instr_rdata_i ),
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// outputs to ID stage
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.instr_rdata_id_o ( instr_rdata_id ), // Output of IF Pipeline stage
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.current_pc_if_o ( current_pc_if ), // current pc
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.current_pc_id_o ( current_pc_id ), // current pc
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.instr_rdata_id_o ( instr_rdata_id ), // Output of IF Pipeline stage
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.illegal_c_insn_id_o ( illegal_c_insn_id ),
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.current_pc_if_o ( current_pc_if ), // current pc in IF stage
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.current_pc_id_o ( current_pc_id ), // current pc in ID stage
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// Forwrding ports - control signals
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.force_nop_i ( force_nop_id ), // select incoming instr or NOP
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@ -308,11 +310,11 @@ module riscv_core
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.force_nop_o ( force_nop_id ),
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.illegal_c_insn_i ( illegal_c_insn_id ),
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.current_pc_if_i ( current_pc_if ),
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.current_pc_id_i ( current_pc_id ),
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.compressed_instr_o ( compressed_instr ),
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// STALLS
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.stall_if_o ( stall_if ),
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.stall_id_o ( stall_id ),
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@ -391,6 +393,7 @@ module riscv_core
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.regfile_we_wb_i ( regfile_we_wb ), // write enable for the register file
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.regfile_wdata_wb_i ( regfile_wdata ), // write data to commit in the register file
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.perf_compressed_o ( perf_compressed ),
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.perf_jump_o ( perf_jump ),
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.perf_branch_o ( perf_branch ),
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.perf_jr_stall_o ( perf_jr_stall ),
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@ -540,9 +543,9 @@ module riscv_core
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.epcr_o ( epcr ),
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// performance counter related signals
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.stall_id_i ( stall_id ),
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.is_compressed_i ( compressed_instr ),
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.is_decoding_i ( is_decoding ),
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.stall_id_i ( stall_id ),
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.is_compressed_i ( perf_compressed ),
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.is_decoding_i ( is_decoding ),
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.instr_fetch_i ( ~instr_ack_int ),
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@ -646,7 +649,7 @@ module riscv_core
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begin
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// get current PC and instruction
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instr = id_stage_i.instr[31:0];
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compressed = id_stage_i.compressed_instr_o;
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compressed = id_stage_i.is_compressed;
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pc = id_stage_i.current_pc_id_i;
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// get register values
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