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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
b347299f31
I.e. the decoder is now before the IF/ID pipeline It turns out there is enough timing budget to put it there and thus it simplifies timing in the ID stage |
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| include | ||
| .gitignore | ||
| alu.sv | ||
| compressed_decoder.sv | ||
| controller.sv | ||
| cs_registers.sv | ||
| debug_unit.sv | ||
| ex_stage.sv | ||
| exc_controller.sv | ||
| hwloop_controller.sv | ||
| hwloop_regs.sv | ||
| id_stage.sv | ||
| if_stage.sv | ||
| instr_core_interface.sv | ||
| load_store_unit.sv | ||
| mult.sv | ||
| register_file.sv | ||
| riscv_core.sv | ||