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Begin tapeout of littleRISCV (misaligned RV32IC)

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Markus Wegmann 2017-01-12 19:31:49 +01:00
parent 946c31ab9a
commit fdfca50e16
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THIS_CORE_IS_AUTOMATICALLY_GENERATATED!!!.txt Normal file
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This core export was automatically generated by ri5cly-manage.py
Following settings were enabled: ['JUMP_IN_ID', 'SIMPLE_ALU', 'MERGE_ID_EX', 'NO_JUMP_ADDER']