Udi Jonnalagadda
9b656a0a2c
Update google_riscv-dv to google/riscv-dv@39797b2
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 39797b2f07784e775149a4f05c90fee2427124e5
* coverage flow updates (Udi Jonnalagadda)
* Update src/riscv_debug_rom_gen.sv (Tom Roberts)
* debug_rom_gen: Fix return address issue (Tom Roberts)
* Add sfence.vma after PTE process (google/riscv-dv#731 ) (taoliug)
* generate gen_config data in tabular format (aneels3)
* Fix coverage issue for ml target (google/riscv-dv#729 ) (taoliug)
* Fix index offset constraint conflict (google/riscv-dv#728 ) (taoliug)
* Fix rcs import and create_instr function (aneels3)
* Fix setup_misa and formatting issue (aneels3)
* Fix SPIKE ISSUE google/riscv-dv#722 (aneels3)
* Fix coverage issue (aneels3)
* fix google/riscv-dv#725 (Udi Jonnalagadda)
* Fix formatting and linting issue (aneels3)
* Add function setup_misa (ShraddhaDevaiya)
* Fix gen_trap_handler_section (aneels3)
* Add constraint (ShraddhaDevaiya)
* Fixed push_gpr_to_kernel def (Saurabh Singh)
* Add ic file to the target dir (aneels3)
* Fix timeout issue (aneels3)
* add mtvec constraint (pvipsyash)
* Fix create_instr issue (aneels3)
* Add function push_gpr_to_kernel (ishitapvips)
* Fix invalid CSR test for RV64GCV target (google/riscv-dv#720 )
(taoliug)
* Fix solve...before... on non-rand variables issue (google/riscv-
dv#719) (taoliug)
* Add rv32c instructions (aneels3)
* Modify riscv_instr class fields (aneels3)
* Fix import issue (aneels3)
* Significantly improves performance of pyflow functional coverage
(through changing the way that covergroups are instantiated & data
are sampled) (Hodjat Asghari Esfeden)
* fix jumps to `test_done` and `init_[m/s/u]_mode` (google/riscv-
dv#710) (udinator)
* Fix multi-harts program generation with PMP enabled (google/riscv-
dv#716) (taoliug)
* Fix google/riscv-dv#681 (google/riscv-dv#715 ) (taoliug)
* Add initial support for rv32imc (aneels3)
* resolve conflicts (aneels3)
* add rv32imc core setting (pvipsyash)
* changes for core settings (pvipsyash)
* add riscv_compressed_instr (aneels3)
* Convert code to be PEP8 compliant (Hodjat Asghari Esfeden)
* Add riscv_data_page_gen (aneels3)
* Integrates functional coverage side of pyflow into cov.py
(google/riscv-dv#708 ) (Hodjat Asghari Esfeden)
* Workaround of the SV compilation problem caused by assigning the
const array variable with the empty concatenation. (google/riscv-
dv#704) (Dariusz Stachańczyk)
* Add rv32m and rv32c instr defines (ShraddhaDevaiya)
* Fix logging issue along with other minor fixes (Hodjat Asghari
Esfeden)
* Add push_stack and pop_stack instr. (ShraddhaDevaiya)
* Fix minor issues (aneels3)
* Add a target for RV32IMC with SV32 address translation
(google/riscv-dv#699 ) (taoliug)
* Fixes a minot import issue (Hodjat Asghari Esfeden)
* Fix LR/SC sequence issue (google/riscv-dv#698 ) (taoliug)
* fix ebreak generation bug (google/riscv-dv#689 ) (udinator)
* Update vector extension to v0.9 (google/riscv-dv#697 ) (taoliug)
* Fixes a few issues in riscv_asm_program_gen and
riscv_instr_gen_config (Hodjat Asghari Esfeden)
* fix iterate over args dict (pvipsyash)
* fix parse_args (pvipsyash)
* fix cmdline argparse for directed stream (pvipsyash)
* [pygen/riscv_instr_stream] Fix ebreak generation (Udi Jonnalagadda)
* Fix flake8 related formatting (aneels3)
* Add jal instr (aneels3)
* Fixes for same rd for main instructions (Saurabh Singh)
* Fixes to resolve label issue for directed class (Saurabh Singh)
* Add constraint on jump_start (ShraddhaDevaiya)
* Add Constraint for jump instructions. (ShraddhaDevaiya)
* fix minor issue in directed_lib (pvipsyash)
* Add riscv_jal_instr to directed_lib (pvipsyash)
* Fix forward branch label compilation error (aneels3)
Signed-off-by: Udi Jonnalagadda <udij@google.com>
2020-10-23 17:00:38 -07:00
Udi
216ba1a42d
Update google_riscv-dv to google/riscv-dv@3cf691d
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Update code from upstream repository https://github.com/google/riscv-
dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804
* remove hardcoded CSR names (Udi Jonnalagadda)
* initial custom CSR support (Udi Jonnalagadda)
* Add support for segmented load/store instructions (google/riscv-
dv#656) (taoliug)
* fix post_randomize issue (aneels3)
* add MAX_LMUL to rv32i config (google/riscv-dv#649 ) (udinator)
* Ignore log and asm file (aneels3)
* Add Command Line Support (aneels3)
* support for command-line arguments (pvipsyash)
* Reorder import statements (aneels3)
* Modified function randomize_gpr in instr_stream file
(ShraddhaDevaiya)
* Updated riscv_instr_sequence file and modified other python files to
get main block in asm file. (ShraddhaDevaiya)
* Modify get_rand_instr() (aneels3)
* added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk)
* Aldec Riviera-PRO compiler command line arguments modified.
(google/riscv-dv#638 ) (Dariusz Stachańczyk)
* allow coverage compilation to be run on LSF (google/riscv-dv#637 )
(udinator)
* Add CHIPS Alliance work group information to the README
(google/riscv-dv#633 ) (taoliug)
* Add indexed/strided vector load/store instrution stream
(google/riscv-dv#632 ) (taoliug)
* Add constraint for mtvec alignment in vectored interrupt mode
(google/riscv-dv#631 ) (taoliug)
* Add bitstring requirement to pygen/experimental README
(google/riscv-dv#630 ) (taoliug)
* Add unsupported load/store instruction filtering (google/riscv-
dv#629) (taoliug)
* Add different methods to initialize the vregs (google/riscv-dv#627 )
(Josep Sans)
* Support a vetor instruction only mode (google/riscv-dv#626 )
(taoliug)
* Add riscv_instr_stream.py file (aneels3)
* Importing PyVSC module (google/riscv-dv#625 ) (Hodjat Asghari
Esfeden)
* update pygen_src files (google/riscv-dv#612 ) (BharathNR1030)
* Fix typo (google/riscv-dv#624 ) (taoliug)
* Fix B-ext instruction generation issue (google/riscv-dv#620 )
(taoliug)
Signed-off-by: Udi <udij@google.com>
2020-07-24 00:09:07 -07:00
udinator
3d8089c235
Update google_riscv-dv to google/riscv-dv@a655f34 ( #564 )
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Update code from upstream repository https://github.com/google/riscv-
dv to revision a655f34eb5058da442b38ca010b0d008291c11b5
* Support running C test (google/riscv-dv#453 ) (Hai Hoang Dang)
* run.py: Do not compare csv file when specified -debug switch
(google/riscv-dv#451 ) (Hai Hoang Dang)
* adjust location of nested interrupt mstatus.mie enable
(google/riscv-dv#444 ) (udinator)
* Implement storing the commands that would be executed as a script
(google/riscv-dv#450 ) (Hai Hoang Dang)
* Move document from README to docs, add HTML preview for the new doc
(google/riscv-dv#448 ) (taoliug)
* Use single HTML format (google/riscv-dv#447 ) (taoliug)
* Update HTML document (google/riscv-dv#446 ) (taoliug)
* Add framework for custom extensions (google/riscv-dv#442 ) (taoliug)
Signed-off-by: Udi <udij@google.com>
2020-01-23 15:10:14 -08:00
udinator
8ce399dbe6
Update google_riscv-dv to google/riscv-dv@d23da38 ( #549 )
...
* update vendor.hjson to exclude generated pdf file
* Update google_riscv-dv to google/riscv-dv@d23da38
Update code from upstream repository https://github.com/google/riscv-
dv to revision d23da3862f95954e6374aaec787e0fb0c1878a16
* fix matched_list and directed_list size comparisons (Udi
Jonnalagadda)
* Add run_cmd_output for reporting all debug command lines
(google/riscv-dv#436 ) (Hai Hoang Dang)
* Resolve: missing pass gcc_opts from YAML for GCC compile command
(google/riscv-dv#435 ) (Hai Hoang Dang)
* Sphinx: Add generating pdf file (google/riscv-dv#431 ) (Hai Hoang
Dang)
* integrate directed asm_tests with yaml flow (Udi Jonnalagadda)
* Fix running cov without arguments (google/riscv-dv#433 ) (Hai Hoang
Dang)
* Add setup Travis CI for tracking build docs, and install
(google/riscv-dv#430 ) (Hai Hoang Dang)
* Add handling KeyboardInterrupt for run_cmd and run_parallel_cmd
(google/riscv-dv#424 ) (Hai Hoang Dang)
* Sphinx: add basic page for structure of the document (google/riscv-
dv#428) (Hai Hoang Dang)
* README.md: Update the information relating to usage (google/riscv-
dv#426) (Hai Hoang Dang)
* Add initial Sphinx docs (google/riscv-dv#427 ) (Hai Hoang Dang)
* Fix typo in the testlist (google/riscv-dv#423 ) (taoliug)
* Add try-except for handling KeyboardInterrupt (google/riscv-dv#421 )
(Hai Hoang Dang)
* Update information about instruction for running scripts
(google/riscv-dv#420 ) (Hai Hoang Dang)
* Add vector permutation, reduction, mask instructions (google/riscv-
dv#422) (taoliug)
* Python package (google/riscv-dv#419 ) (Hai Hoang Dang)
* Refactor the code for cov.py (google/riscv-dv#416 ) (Hai Hoang Dang)
* Update ovpsim config for vector extesion (google/riscv-dv#415 )
(taoliug)
* Fix coverage flow issue (google/riscv-dv#414 ) (taoliug)
* Add missing license header (google/riscv-dv#412 ) (taoliug)
* Fix typo in cov_test (google/riscv-dv#410 ) (taoliug)
* Add vector floating point instructions (google/riscv-dv#409 )
(taoliug)
* Add fixed point arithmetic vector instruction (google/riscv-dv#408 )
(taoliug)
* cov.py: Generate error when it cannot find spike_sim directory
(google/riscv-dv#407 ) (Hai Hoang Dang)
* Add vector CSR initialization routine (google/riscv-dv#405 )
(taoliug)
* Create vector extension target, add basic enums (google/riscv-
dv#404) (taoliug)
* Fix qrun sim warning (google/riscv-dv#402 ) (taoliug)
* Try fix qrun constraint solver issue (google/riscv-dv#401 ) (taoliug)
* Fix simulation warning (google/riscv-dv#400 ) (taoliug)
* run.py: Generate error for gcc compile when it cannot find assembly
files (google/riscv-dv#398 ) (Hai Hoang Dang)
* Add numeric corner case test, misc coverage fixes (google/riscv-
dv#396) (taoliug)
* Switch to new CSV format (google/riscv-dv#395 ) (taoliug)
* misc fixes for the coverage model (google/riscv-dv#394 ) (taoliug)
* Fix new CSV coverage flow issue (google/riscv-dv#392 ) (taoliug)
* Integrate new trace CSV format with coverage flow (google/riscv-
dv#390) (taoliug)
* Add experimental script for the new CSV format (google/riscv-dv#389 )
(taoliug)
* Support flexible running directed assembly tests (google/riscv-
dv#386) (Hai Hoang Dang)
* run.py: Enhance passing argument for gen function (google/riscv-
dv#382) (Hai Hoang Dang)
* Fix qrun issue, take 2 (google/riscv-dv#384 ) (taoliug)
* Attempt to fix qrun issue (google/riscv-dv#383 ) (taoliug)
* Fix (google/riscv-dv#381 ) (taoliug)
* Fix typo (google/riscv-dv#380 ) (taoliug)
* Fix qrun simulation issue (google/riscv-dv#379 ) (taoliug)
* Cleaning the output directory by default. Using exist output
directory (google/riscv-dv#377 ) (Hai Hoang Dang)
* Fix ius compilation error temporarily (google/riscv-dv#378 )
(taoliug)
* Functional coverage improvement (google/riscv-dv#376 ) (taoliug)
* Add unaligned jump instruction support (google/riscv-dv#375 )
(taoliug)
* move handcoded asm_test generation into separate output directory
(Udi Jonnalagadda)
* Ignore return code for ovpsim sim (google/riscv-dv#371 ) (taoliug)
* Fix mie compare mismatch (google/riscv-dv#370 ) (taoliug)
* Fix directory/file name for assembly test flow (google/riscv-dv#369 )
(taoliug)
* Fix error in README (google/riscv-dv#368 ) (taoliug)
* Add sample rv32imc test (google/riscv-dv#367 ) (taoliug)
* Fix typo (google/riscv-dv#366 ) (taoliug)
* Support running regression with hand-coded assembly tests
(google/riscv-dv#365 ) (taoliug)
Signed-off-by: Udi <udij@google.com>
2020-01-09 15:04:39 -08:00
udinator
0d6ccbf1f6
Update google_riscv-dv to google/riscv-dv@5b1dd4e ( #523 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 5b1dd4e2eb11d49d3275da80953efc0c50f90447
* Add compliance mode to coverage model (google/riscv-dv#361 )
(taoliug)
* Revert " Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357 )" (google/riscv-
dv#360) (taoliug)
* Fix script issue (google/riscv-dv#358 ) (taoliug)
* Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357 ) (Hai Hoang Dang)
* Remove unused variable (google/riscv-dv#348 ) (Hai Hoang Dang)
* Functional coverage improvement (google/riscv-dv#356 ) (taoliug)
* Fix list access exception thrown when parsing ovpsim illegal
instruction (Udi Jonnalagadda)
* Add compliance mode and RTL mode to the coverage model
(google/riscv-dv#354 ) (taoliug)
* Fix lr/sc sequence (google/riscv-dv#353 ) (taoliug)
* Fix minor illegal instruction issue (google/riscv-dv#351 ) (taoliug)
* Migrate to new instruction class (google/riscv-dv#350 ) (taoliug)
* misc issue fixes (google/riscv-dv#349 ) (taoliug)
* Update README to add contact info for the collaboration request
(google/riscv-dv#347 ) (taoliug)
* Support running specific multiple tests (google/riscv-dv#346 ) (Hai
Hoang Dang)
* Fix rv64 coverage model issue (google/riscv-dv#344 ) (taoliug)
* Fix the link for yaml/base_testlist.yaml (google/riscv-dv#343 ) (Hai
Hoang Dang)
* refactor debug ROM generation (Udi Jonnalagadda)
* Add a runtime option to run with experimental features
(google/riscv-dv#341 ) (taoliug)
* Fix a few issues with the new instruction class (google/riscv-
dv#340) (taoliug)
* Improve performance of new experimental instruction class
(google/riscv-dv#339 ) (taoliug)
* Fix CSR randomization bug when generating loops (google/riscv-
dv#337) (udinator)
* Add support coverage flow for qrun, and minor fix for cov.py
(google/riscv-dv#335 ) (Hai Hoang Dang)
* [ovpsim] Coding style fixes, fix floating point compare mismatch
(google/riscv-dv#334 ) (taoliug)
* Fix ius flow issue (google/riscv-dv#333 ) (taoliug)
* Fix a few new instruction class issues (google/riscv-dv#332 )
(taoliug)
* Added two includes and starting variables for adding bitmanip
extension (google/riscv-dv#328 ) (simond-imperas)
* Integrate experimental instruction class (google/riscv-dv#331 )
(taoliug)
* Minor fixes to run.py (google/riscv-dv#330 ) (taoliug)
* Run.py: minor refactor the code for compile, and simulate
(google/riscv-dv#326 ) (Hai Hoang Dang)
* Add requirements for install dependencies (google/riscv-dv#325 ) (Hai
Hoang Dang)
* Adding support qrun simulator (google/riscv-dv#324 ) (Hai Hoang Dang)
* Add new experimental instruction class (google/riscv-dv#323 )
(taoliug)
* Added command line control of coverage and added hooks for vector
coverage development (google/riscv-dv#317 ) (simond-imperas)
* Fix compilation issue (google/riscv-dv#322 ) (taoliug)
Signed-off-by: Udi <udij@google.com>
2019-12-16 11:47:53 -08:00
udinator
6a582cc11f
Update google_riscv-dv to google/riscv-dv@39ca859 ( #486 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 39ca85903eea94350d3a610256307346da407e5b
* Add directed stream to access higher privilege CSRs (google/riscv-
dv#316) (udinator)
* add config knob for mstatus.tw (Udi Jonnalagadda)
* Fix ovpsim floating point instruction parsing issue (google/riscv-
dv#313) (taoliug)
* Fix SATP configure issue (google/riscv-dv#312 ) (taoliug)
* Support import testlist (google/riscv-dv#311 ) (taoliug)
* Add a rand address load/store test (google/riscv-dv#310 ) (taoliug)
* Fix ovpsim log parsing issue (google/riscv-dv#309 ) (taoliug)
* Add a generic approach to check command return value (google/riscv-
dv#308) (taoliug)
* Fix compile issue (google/riscv-dv#307 ) (taoliug)
* Basic U-mode support (Udi Jonnalagadda)
Signed-off-by: Udi <udij@google.com>
2019-11-21 11:22:34 -08:00
udinator
6ce8b6ecf2
Update google_riscv-dv to google/riscv-dv@4b333ba ( #462 )
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Update code from upstream repository https://github.com/google/riscv-
dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e
* cg instantion based on supported_isa (google/riscv-dv#303 )
(udinator)
* Fix coverage collection issue, change default target to rv32imc
(google/riscv-dv#302 ) (taoliug)
* Integrate whisper(swerv-ISS) (google/riscv-dv#301 ) (taoliug)
* Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode
(google/riscv-dv#299 ) (taoliug)
* Fix jalr handling issue for ovpsim (google/riscv-dv#298 ) (taoliug)
* Add noclean option, change default output directory of coverage
collection (google/riscv-dv#297 ) (taoliug)
* Enable using core trace logs for coverage collection (google/riscv-
dv#291) (udinator)
* Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296 )
(taoliug)
* fixed line widths (x2) and check error returns for any questa
simalator (google/riscv-dv#293 ) (simond-imperas)
* Unknown instruction fix (google/riscv-dv#290 ) (simond-imperas)
* Fix ovpsim log process issue (google/riscv-dv#289 ) (udinator)
* adding riscvOVPsim vector instruction trace to csv processing -
start (3rd Attempt) (google/riscv-dv#288 ) (simond-imperas)
Signed-off-by: Udi <udij@google.com>
2019-11-12 14:39:22 -08:00
udinator
f3f3f3de09
Update google_riscv-dv to google/riscv-dv@cce71d2 ( #445 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision cce71d24b56f641d994fbf69b8b50aa3756b9322
* Add handshake documentation (Udi)
* Fix coverage debug mode (google/riscv-dv#281 ) (taoliug)
* Fix coverage script issue (google/riscv-dv#280 ) (taoliug)
* code block highlight (google/riscv-dv#279 ) (taoliug)
* Replace setting directory with a default target (google/riscv-
dv#278) (taoliug)
* fixed trace handling issues (google/riscv-dv#274 ) (eroom)
* Allow running the script from other directory (google/riscv-dv#277 )
(taoliug)
* Add dummy writes to status and ie CSRs (Udi)
* Script typo fix (google/riscv-dv#272 ) (Dan Petrisko)
* Fix misa setup issue (google/riscv-dv#271 ) (taoliug)
* Enable mie.mtie for timer interrupts (Udi)
* Update illegal system instr generation (Udi)
* Fix duplicate (google/riscv-dv#268 ) (taoliug)
* Add experimental instruction distribution control (google/riscv-
dv#267) (taoliug)
* Update README to clarify the flow setup instructions (google/riscv-
dv#265) (taoliug)
* Remove debug logging (google/riscv-dv#264 ) (taoliug)
* Fix compressed instruction test setup (google/riscv-dv#263 )
(taoliug)
* adding __init__ in the scripts dir since python3.7 requires that for
directories to be recognized as modules (google/riscv-dv#252 )
(Jielun Tan)
* Fix riscvOVPsim.ic (google/riscv-dv#261 ) (taoliug)
* Fix ovpsim sim problem (google/riscv-dv#260 ) (taoliug)
* Add alternative command options for directed instruction stream
(google/riscv-dv#254 ) (taoliug)
* Fix dsim compilation issue (google/riscv-dv#253 ) (taoliug)
2019-11-04 10:48:02 -08:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc ( #417 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead
* Incorrect deletion (google/riscv-dv#249 ) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248 )
(eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247 ) (taoliug)
* Coverage model fixes (google/riscv-dv#246 ) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244 )
(taoliug)
* Functional coverage improvement (google/riscv-dv#243 ) (taoliug)
* Functional coverage improvement (google/riscv-dv#242 ) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240 )
(taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239 )
(taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238 ) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234 )
(taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233 )
(eroom)
* Refine README structure (google/riscv-dv#231 ) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230 )
(taoliug)
2019-10-23 10:46:31 -07:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf ( #406 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd
* Add more ebreak generation control (google/riscv-dv#229 ) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228 ) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226 )
(taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225 )
(Greg Chadwick)
* Minor README typo (google/riscv-dv#219 ) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220 )
(taoliug)
* Fix floating point comparison issue (google/riscv-dv#218 ) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217 ) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215 )
(Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
(google/riscv-dv#214 ) (Hai Hoang Dang)
2019-10-16 17:50:23 -07:00
udinator
4a1806f16f
Update google_riscv-dv to google/riscv-dv@ad6fe56 ( #385 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2
* Workaround for dsim compile issue (google/riscv-dv#211 ) (taoliug)
* Add a --seed_yaml option to rerun a regression with the same seed of
a prior regression (google/riscv-dv#210 ) (taoliug)
* Update questa covearge options (google/riscv-dv#209 ) (taoliug)
* Fix disable_compressed_instr option (google/riscv-dv#205 ) (taoliug)
* Fix non-compressed instruction test (google/riscv-dv#203 ) (taoliug)
* Debug single step functionality and config knobs (Udi)
* Fix no_branch_jump option (google/riscv-dv#200 ) (taoliug)
* Add more functional covergroup (google/riscv-dv#199 ) (taoliug)
* Allow randomly reserve GPR for TP/SP, improve functional coverage
(google/riscv-dv#198 ) (taoliug)
* Allow running the coverage script with LSF (google/riscv-dv#195 )
(taoliug)
* Add support for disable_compressed_instr (google/riscv-dv#194 )
(taoliug)
* Improve coverage collection performance (google/riscv-dv#193 )
(taoliug)
* Signature_addr_reg constraint update (Udi)
* Add a debug mode for functional coverage (google/riscv-dv#191 )
(taoliug)
* Fix typo in README (google/riscv-dv#189 ) (taoliug)
* Constrain scratch_reg (google/riscv-dv#188 ) (udinator)
* Update README for the coverage flow (google/riscv-dv#187 ) (taoliug)
* Add basic privileged CSR cover group (google/riscv-dv#186 ) (taoliug)
* Fix cover point definition (google/riscv-dv#185 ) (taoliug)
* Fix ovpsim log compare issue (google/riscv-dv#183 ) (udinator)
2019-10-08 14:22:05 -07:00
udinator
1e8381bfa1
Update google_riscv-dv to google/riscv-dv@4450592 ( #347 )
...
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44505927a70a6234b996d15f2e51bd1e2632b68e
* Dump performance counters to testbench at EOT (Udi)
* Fix a constraint issue (google/riscv-dv#174 ) (taoliug)
* Allow split a long test to small batches (google/riscv-dv#173 )
(taoliug)
* Fix ius compile problem (google/riscv-dv#172 ) (taoliug)
* Add basic functional coverage for RV64IMC (google/riscv-dv#171 )
(taoliug)
* Initial prototype of functional coverage (google/riscv-dv#169 )
(taoliug)
2019-09-23 18:08:16 -07:00
