* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line
* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF.
* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line
* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present
* [rtl] Changed the default number of performance counters from 0 to 10 (#214)
* Implementation of sequential equivalence checking option using Yosys EQY.
* [sec] Automatic removal of new IO when performing SEC against (current) golden design with Yosys EQY
* [rtl] Changed the default number of performance counters from 0 to 10 (#214)
* [rtl] Turning debug halt and exception addresses from parameters into signals (#269)
* [doc] Updating the docs regarding the turning of debug halt and exception addresses into signals (#269)
* Adding buildsim.log to .gitignore, as it is created by some make targets
* Adding Reset-value and detailed table to MISA register in the CV32E20 UM
* Adding detailed table to MISA register in the CV32E20 UM
* Replace Hardcoded Values with Parameters
* Removing RVB Comment
The relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following
priorities for resolving multiple concurrent reasons for entering debug mode....
DCSR.cause : Explains why Debug Mode was entered.
When there are multiple reasons to enter Debug Mode in a single cycle,
hardware should set cause to the cause with the highest priority.
1: An ebreak instruction was executed. (priority 3)
2: A Trigger Module trigger fired with action=1. (priority 4)
3: The debugger requested entry to Debug Mode using haltreq. (priority 1)
4: The hart single stepped because step was set. (priority 0, lowest)
5: The hart halted directly out of reset due to resethaltreq. (priority 2)
It is also acceptable to report 3 when this happens.
6: The hart halted because it’s part of a halt group. (priority 5, highest)
Harts may report 3 for this cause instead.
Other values are reserved for future use.
Co-authored-by: Harry Callahan <hcallahan@lowrisc.org>
