This change will cause the ID stage to stall if there is a potential
debug mode entry until instructions in both ID and WB have completed.
This fixes an issue with incorrect behaviour around hardware breakpoints
and exceptions that could cause exception entry to be missed, hardware
breakpoints to be triggered incorrectly or missed entirely.
In addition single step control logic is altered to work correctly with
the new debug mode entry behaviour.
this test is arbitrarily failing in regressions on a Spike timeout,
temporarily remove this to avoid blocking.
@udinator to fix this in the near future.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
Changes the ECC granularity in the data RAMs from 64bit to 32bit. This
is to align with an upcoming change in bus ECC. Relates to
lowRISC/opentitan#5450
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This PR adds functionality to filter out tests during regressions for a
particular config.
e.g. if a full regression is kicked off using the `small` config, we
don't want to attempt to run any PMP and bitmanip tests as the RTL
parameter-set will not support it.
To do this, a new YAML field called `rtl_params` is added to relevant
test entries, to indicate what parameters (if any) are required to be
able to run the particular test, along with the required value of said
parameters.
`sim.py` will then parse this field (if it exists), and using
information from `ibex_configs.yaml` pertaining to the current config,
will remove tests from being run on-the-fly.
This also gives us the convenient side effect of not having to re-run
instruction generation if there is a parameter/config mismatch, we can
just rerun the RTL compilation and simulation stages safely.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
This commit adds the MCOUNTEREN CSR as required by the RISC-V spec.
The register is defined as WARL. At the moment, Ibex doesn't enable U-mode
access to the performance montiors. Consequently, writes to the register are
ignored and it reads as zero which is okay according to the spec.
This resolveslowRISC/Ibex#1278 .
Currently, the `cov` step in the DV Makefile will only merge coverage
databases emitted directly from Ibex simulations, and will not pick up
any coverage databases generated by the RISCV-DV functional coverage
flow.
This PR updates the `gen_cov()` function in `sim.py` to recursively
search for any generated coverage directories and then merges them all.
Resultant coverage reports include all code coverage, Ibex functional
coverage, and RISCV-DV functional coverage.
The coverage-related targets in the Makefile have also been renamed to
improve clarity.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
Anyone who needs to disassemble their generated ELF can probably just
call objdump directly and the precise set of flags have already
confused at least one potential contributor[1].
We're keeping the canned objdump command for "engineers that know
where to look" because some have said they find it useful. Run it with
e.g.
make -C examples/sw/simple_system/hello_test disassemble
[1] https://github.com/lowRISC/ibex/issues/1263
Prior to this change Ibex had multiple feedthrough paths from the data
memory interface to the instruction memory interface. This existed
because Ibex would hold off doing a instruction fetch for a jump or
branch if there was a outstanding memory request. It would wait for the
response to be available so either the jump or branch would occur or an
exception was taken.
With this change the branch or jump will speculatively begin the
instruction fetch whilst there is an outstanding memory request. Should
an exception result from the memory request the fetch will be discarded
and the exception taken as normal.
An alternative fix would not factor the data error response
(data_err_i) directly into the controller logic for branches and jumps.
With this option new stall cycles would be introduced anywhere a branch
or jump immediately follows a memory instruction which would have an
adverse impact on performance.
* `if` in `DBG_TAKEN_IF` is needless as the conditions it checks will be
true if controller enters `DBG_TAKEN_IF` state
* flop `enter_debug_mode` so `FLUSH` state looks at what
`enter_debug_mode` was when it was seen in `DECODE` state rather than
what it has become. In particular the controller could enter `FLUSH`
on the basis of performing a WFI then divert down the debug control
path due to a new debug request being raised. In this instance it is
preferable for the WFI to complete entering `SLEEP` before the debug
request wakes the core back up.
We were using the old html_context which has been deprecated
for a while. This PR switches to html_css_files instead.
See sphinx-doc/sphinx#8885 for more information.
The UVM log should be checked for failures before attempting to process
the core trace log. A simulation failure could mean the trace log
doesn't exist and is is preferable to report the simulation error from
the log rather than trace not found as a failure cause.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b625258549e733082c12e5dc749f05aefb07d5a
* Add a knob to use rounding mode from the instruction (google/riscv-
dv#767) (taoliug)
* Add rounding mode support for floating point arithmetic instructions
(google/riscv-dv#766) (taoliug)
* Fix syntax issue (google/riscv-dv#765) (taoliug)
* Add riscv_amo_instr (aneels3)
* convert string to enum type (ishita71)
* Remove unintended errors in the coverage flow (google/riscv-dv#757)
(taoliug)
* Fix c_test handling in the YAML testlist (google/riscv-dv#756)
(taoliug)
* Add support for new Spike trace format (google/riscv-dv#755) (Daniel
Bates)
* Fixgoogle/riscv-dv#751 for floating point coverage (Weicai Yang)
* Fix issues with implemented TODO's (aneels3)
* fix randomize_gpr (aneels3)
* Add file riscv_b_instr.py (ishita71)
* add std_randomize todo (pvipsyash)
* Add todo for floating_point test (ShraddhaDevaiya)
* Add scripts to integrate with Metrics regression platform (Aimee
Sutton)
Includes a fix to dv/uvm/core_ibex/sim.py to use `asm_test` rather than
`asm_tests` due to changes in RISCV-DV
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
The assembly for the CSR test is generated by a script from RISCV-DV. A
.org directive is required to put the generated code at the correct
start address for the instantiated Ibex core.
riscv_interrupt_instr_test and riscv_debug_instr_test aim to produce
interrupt and debug requests once per unique instruction they've seen.
One exception to this is WFI instructions, as these always require an
interrupt or debug request to wake the core. This fixes two timeout
issues with WFI instructions.
1. The return value of `decode_instruction` is used to determine whether
an instruction should have an interrupt or debug request generated
for it. For WFI this must always happen or the test will hang.
2. Before calling check_stimulus in a test the testbench waits for 50
clock cycles. For the riscv_interrupt_instr_test and
riscv_debug_instr_test if a WFI is executed during these 50 cycles
the test will hang. This adds a check to see if the core has gone to
sleep in those tests and if so sends interrupt/debug stimulus to wake
it up.
The `driver_tick` DPI call drove inputs directly but was being scheduled
in an undefined order with other always_ff blocks. This results in a
race condition where some always_ff blocks see old inputs and others see
new in the same clock tick. Instead use values from `driver_tick` to
perform NBA updates and avoid the race condition.
This implemements the RISC-V Trusted Execution Environment (TEE) working
group proposal 'PMP Enhancements for memory access and execution
prevention on Machine mode'. The proposal is awaiting ratification and
is not expected to change beyond minor tweaks before it becomes part of
the RISC-V priviledged specification.
No seperate 'classic' PMP only mode is provided as different PMP
behaviour only occurs when the MSECCFG CSR is written to. This CSR is
introduced by the proposal and has no specified function in the current
RISC-V priviledged specification.
* Handle missing log files with error messages rather than terminating
on unhandled exceptions
* Output potential failure causes from sim log file into regression log
* Alter per test output to make it clearer what line corresponds to what
test
* Only output [PASSED] or [FAILED] a single time per test
* Don't output [PASSED] where sim log is good but ISS comparison is not
In UVM 1.2, at least, uvm_component (a base class of
core_ibex_base_test) still has a method called run(). Ironically, this
has been renamed to "run_phase" to avoid conflicting with user names,
but the old-style phase names still exist at the moment.
Rename our copy of the phase object to cur_run_phase, which doesn't
conflict. Also, set it back to null at the end of the run_phase()
task. We shouldn't ever use it afterwards, and it's probably a good
idea to explode with a null object error if we do.
The previous code contained
wait (dut_vif.dut_cb.priv_mode === select_mode())
and VCS warns that this wait block will only trigger on changes to
explicit arguments. That is, if the in_nested_trap field changes, so
the return value of the select_mode() method would change to match
priv_mode, the wait statement won't finish.
This patch explicitly stores a snapshot of the value of select_mode()
just before the wait line. I think this is the intended behaviour, and
will no longer trigger warnings from VCS.
This silences VCS warnings about the DUT having missing port
connections. It doesn't add any actual testing for these signals.
The patch also re-orders the signals to match the order in
ibex_core_tracing.sv, to make it easier to spot what's going on by
eye.
I wonder whether we could use some form of quoting to allow
"32'h8000_0000" to get through Riviera's TCL, but we don't have any
way to test, so let's go with the easy option.
This should match what's going on a bit more accurately. The link to
OVPsim now points at the (free of cost) commercial tool: riscv-ovpsim
doesn't support the bitmanip specification that we're using at the
moment.
The -Wwarn-IMPERFECTSCH flag is suggested in the Verilator docs (to
help spot if we get a clock gating hint wrong). The waiver is no
longer needed because we now add the relevant hint in the
RTL (vendored in prim_generic_clock_gating.sv from OpenTitan).
The previous change was wrong: it was trying to define a signal with
DbgHwNumLen bits that contained DbgHwBreakNum - 1. Unfortunately, '1
is *not* the same as a zero-extended version of 1'b1.
DbgHwBreakNum - 1 is an int, so generates a warning if it's assigned
to tselect_d (of type logic [DbgHwNumLen-1:0]). Explicitly generate
the value we need as a localparam.
This lint warning doesn't appear by default in the Ibex repository,
because DbgTriggerEn is disabled. It does, however, appear in
OpenTitan because we enable it there.
This commit modifies the encoding of SROI, RORI, SBEXTI, GREVI and GORCI by
forcing Bit 26 to zero to prevent overlapping encodings with FSRI.
The bitmanip draft spec doesn't explicitly state that Bit 26 for those
instructions must be zero. However, those instructions only ever use
log2(XLEN) LSBs of the immediate. This means they don't use Bit 26 in RV32.
Instead, whenever Bit 26 is set, these instructions are instead decoded as
FSRI.
This fixes a bug where .csv.rpt files weren't being generated properly.
OpenSTA was outputting a simple 'Q' or 'D' for start and end path points
where the full instance name was required (which is then fed to yosys to
translate to a human readable name). The issue was in the `timing_report`
proc in syn/tcl/sta_utils.tcl which needed to request the full name of
the start and end points.
The syn README is updated to note which tool versions have been used to
test the flow.
Fixes#1193
