* `if` in `DBG_TAKEN_IF` is needless as the conditions it checks will be
true if controller enters `DBG_TAKEN_IF` state
* flop `enter_debug_mode` so `FLUSH` state looks at what
`enter_debug_mode` was when it was seen in `DECODE` state rather than
what it has become. In particular the controller could enter `FLUSH`
on the basis of performing a WFI then divert down the debug control
path due to a new debug request being raised. In this instance it is
preferable for the WFI to complete entering `SLEEP` before the debug
request wakes the core back up.
We were using the old html_context which has been deprecated
for a while. This PR switches to html_css_files instead.
See sphinx-doc/sphinx#8885 for more information.
The UVM log should be checked for failures before attempting to process
the core trace log. A simulation failure could mean the trace log
doesn't exist and is is preferable to report the simulation error from
the log rather than trace not found as a failure cause.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b625258549e733082c12e5dc749f05aefb07d5a
* Add a knob to use rounding mode from the instruction (google/riscv-
dv#767) (taoliug)
* Add rounding mode support for floating point arithmetic instructions
(google/riscv-dv#766) (taoliug)
* Fix syntax issue (google/riscv-dv#765) (taoliug)
* Add riscv_amo_instr (aneels3)
* convert string to enum type (ishita71)
* Remove unintended errors in the coverage flow (google/riscv-dv#757)
(taoliug)
* Fix c_test handling in the YAML testlist (google/riscv-dv#756)
(taoliug)
* Add support for new Spike trace format (google/riscv-dv#755) (Daniel
Bates)
* Fixgoogle/riscv-dv#751 for floating point coverage (Weicai Yang)
* Fix issues with implemented TODO's (aneels3)
* fix randomize_gpr (aneels3)
* Add file riscv_b_instr.py (ishita71)
* add std_randomize todo (pvipsyash)
* Add todo for floating_point test (ShraddhaDevaiya)
* Add scripts to integrate with Metrics regression platform (Aimee
Sutton)
Includes a fix to dv/uvm/core_ibex/sim.py to use `asm_test` rather than
`asm_tests` due to changes in RISCV-DV
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
The assembly for the CSR test is generated by a script from RISCV-DV. A
.org directive is required to put the generated code at the correct
start address for the instantiated Ibex core.
riscv_interrupt_instr_test and riscv_debug_instr_test aim to produce
interrupt and debug requests once per unique instruction they've seen.
One exception to this is WFI instructions, as these always require an
interrupt or debug request to wake the core. This fixes two timeout
issues with WFI instructions.
1. The return value of `decode_instruction` is used to determine whether
an instruction should have an interrupt or debug request generated
for it. For WFI this must always happen or the test will hang.
2. Before calling check_stimulus in a test the testbench waits for 50
clock cycles. For the riscv_interrupt_instr_test and
riscv_debug_instr_test if a WFI is executed during these 50 cycles
the test will hang. This adds a check to see if the core has gone to
sleep in those tests and if so sends interrupt/debug stimulus to wake
it up.
The `driver_tick` DPI call drove inputs directly but was being scheduled
in an undefined order with other always_ff blocks. This results in a
race condition where some always_ff blocks see old inputs and others see
new in the same clock tick. Instead use values from `driver_tick` to
perform NBA updates and avoid the race condition.
This implemements the RISC-V Trusted Execution Environment (TEE) working
group proposal 'PMP Enhancements for memory access and execution
prevention on Machine mode'. The proposal is awaiting ratification and
is not expected to change beyond minor tweaks before it becomes part of
the RISC-V priviledged specification.
No seperate 'classic' PMP only mode is provided as different PMP
behaviour only occurs when the MSECCFG CSR is written to. This CSR is
introduced by the proposal and has no specified function in the current
RISC-V priviledged specification.
* Handle missing log files with error messages rather than terminating
on unhandled exceptions
* Output potential failure causes from sim log file into regression log
* Alter per test output to make it clearer what line corresponds to what
test
* Only output [PASSED] or [FAILED] a single time per test
* Don't output [PASSED] where sim log is good but ISS comparison is not
In UVM 1.2, at least, uvm_component (a base class of
core_ibex_base_test) still has a method called run(). Ironically, this
has been renamed to "run_phase" to avoid conflicting with user names,
but the old-style phase names still exist at the moment.
Rename our copy of the phase object to cur_run_phase, which doesn't
conflict. Also, set it back to null at the end of the run_phase()
task. We shouldn't ever use it afterwards, and it's probably a good
idea to explode with a null object error if we do.
The previous code contained
wait (dut_vif.dut_cb.priv_mode === select_mode())
and VCS warns that this wait block will only trigger on changes to
explicit arguments. That is, if the in_nested_trap field changes, so
the return value of the select_mode() method would change to match
priv_mode, the wait statement won't finish.
This patch explicitly stores a snapshot of the value of select_mode()
just before the wait line. I think this is the intended behaviour, and
will no longer trigger warnings from VCS.
This silences VCS warnings about the DUT having missing port
connections. It doesn't add any actual testing for these signals.
The patch also re-orders the signals to match the order in
ibex_core_tracing.sv, to make it easier to spot what's going on by
eye.
I wonder whether we could use some form of quoting to allow
"32'h8000_0000" to get through Riviera's TCL, but we don't have any
way to test, so let's go with the easy option.
This should match what's going on a bit more accurately. The link to
OVPsim now points at the (free of cost) commercial tool: riscv-ovpsim
doesn't support the bitmanip specification that we're using at the
moment.
The -Wwarn-IMPERFECTSCH flag is suggested in the Verilator docs (to
help spot if we get a clock gating hint wrong). The waiver is no
longer needed because we now add the relevant hint in the
RTL (vendored in prim_generic_clock_gating.sv from OpenTitan).
The previous change was wrong: it was trying to define a signal with
DbgHwNumLen bits that contained DbgHwBreakNum - 1. Unfortunately, '1
is *not* the same as a zero-extended version of 1'b1.
DbgHwBreakNum - 1 is an int, so generates a warning if it's assigned
to tselect_d (of type logic [DbgHwNumLen-1:0]). Explicitly generate
the value we need as a localparam.
This lint warning doesn't appear by default in the Ibex repository,
because DbgTriggerEn is disabled. It does, however, appear in
OpenTitan because we enable it there.
This commit modifies the encoding of SROI, RORI, SBEXTI, GREVI and GORCI by
forcing Bit 26 to zero to prevent overlapping encodings with FSRI.
The bitmanip draft spec doesn't explicitly state that Bit 26 for those
instructions must be zero. However, those instructions only ever use
log2(XLEN) LSBs of the immediate. This means they don't use Bit 26 in RV32.
Instead, whenever Bit 26 is set, these instructions are instead decoded as
FSRI.
This fixes a bug where .csv.rpt files weren't being generated properly.
OpenSTA was outputting a simple 'Q' or 'D' for start and end path points
where the full instance name was required (which is then fed to yosys to
translate to a human readable name). The issue was in the `timing_report`
proc in syn/tcl/sta_utils.tcl which needed to request the full name of
the start and end points.
The syn README is updated to note which tool versions have been used to
test the flow.
Fixes#1193
Forward a currently unused parameter.
Disable error exit for warnings. Newer Verilator versions will fail if
for example parameters are unused. As this test does not cover
everything, allow those warning to be printed, but not fail the build.
The parameters are not used as the instructions are not yet widely
supported.
Keep definitions so they can be easily activated later.
Tracked in issue lowrisc/ibex#1228
In the past, we did explicitly install pyyaml through PIP to get a
version newer than the one provided in Ubuntu 18.04. Since then we
changed the calling code to not rely on newer pyyaml features and
are thus able to rely on an older version of pyyaml.
The distro-provided version of pyyaml is built with C bindings, which
are significantly faster than the pip-installed version, which uses a
pure Python-implementation of the parser/dumper.
Xcelium 19.03 doesn't support the `->` (binary logical) operator, but
using `|->` (overlapping implication) is equivalent here and supported;
use this operator instead.
Fixes#1213
The GitHub UI shows apparently the name of the template at
https://github.com/lowRISC/ibex/issues/new/choose, which I thought was
just an internal identifier. Use the longer-form version there as well.
Add two issue templates to the GitHub project: one for questions, and
one for reporting bugs. These templates are not mandatory, users can
freely change them, or get a blank issue template instead.
To avoid having too much description/example text in the final issue the
instructions are written in HTML comments (which is not beautiful, but
should do the trick and seen commonly in projects).
These changes correspond to similar changes in the prefetch buffer to
support branch prediction. A registered version of fill_ext_done was
required to prevent a combinational loop from branch_i in to valid_o
out.
Multiplexing priorities for fifo_addr have been swapped to match
fetch_addr_d in the same module and all similar multiplexing in the
icache (prioritize incoming branch_i over branch_mispredict_i). Note
however that it is not expected that these conditions will actually
occur together, and an assertion has been added to check that.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Remove the SpeculativeRequest parameter, and replace it with a
policy. If the cache is disabled, make the request on the basis that we
definitely won't hit in the cache and so should make the bus request
asap.
Stop fill buffers from fetching complete cache lines when the cache is
disabled. When the core branches into the middle of a line, the lower
words would normally be fetched to complete the line. This is
unnecessary when the cache is disabled since those words will just be
thrown away and the core will stall while they are being fetched.
These two changes make the performance using the disabled icache the
same as using non-icache prefetch buffer.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Amusingly, there was also actually a bug in the combo sequence logic:
it took seq_idx to be the number of sequences that we'd run so far,
but it is actually an index that chooses which sequence we're about to
run.
