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69 lines
2.5 KiB
Systemverilog
69 lines
2.5 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Writeback passthrough
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*
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* The writeback stage is not present therefore this module acts as
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* a simple passthrough to write data direct to the register file.
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*/
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`include "prim_assert.sv"
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`include "dv_fcov_macros.svh"
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module cve2_wb #(
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic en_wb_i,
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input logic instr_is_compressed_id_i,
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input logic instr_perf_count_id_i,
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output logic perf_instr_ret_wb_o,
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output logic perf_instr_ret_compressed_wb_o,
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input logic [4:0] rf_waddr_id_i,
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input logic [31:0] rf_wdata_id_i,
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input logic rf_we_id_i,
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input logic [31:0] rf_wdata_lsu_i,
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input logic rf_we_lsu_i,
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output logic [4:0] rf_waddr_wb_o,
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output logic [31:0] rf_wdata_wb_o,
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output logic rf_we_wb_o,
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input logic lsu_resp_valid_i,
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input logic lsu_resp_err_i
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);
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import cve2_pkg::*;
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// 0 == RF write from ID
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// 1 == RF write from LSU
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logic [31:0] rf_wdata_wb_mux [2];
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logic [1:0] rf_wdata_wb_mux_we;
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// without writeback stage just pass through register write signals
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assign rf_waddr_wb_o = rf_waddr_id_i;
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assign rf_wdata_wb_mux[0] = rf_wdata_id_i;
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assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
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// Increment instruction retire counters for valid instructions which are not lsu errors.
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assign perf_instr_ret_wb_o = instr_perf_count_id_i & en_wb_i &
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~(lsu_resp_valid_i & lsu_resp_err_i);
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assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i;
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assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i;
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assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
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// RF write data can come from ID results (all RF writes that aren't because of loads will come
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// from here) or the LSU (RF writes for load data)
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assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
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({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
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assign rf_we_wb_o = |rf_wdata_wb_mux_we;
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`ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
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endmodule
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