cve2/rtl
Davide Schiavone 468b3595cd
add X-IF 1.0 (#284)
* Core-V eXtension Interface (CV-X-IF) integration (#277)

* minor fixes (#283)

* minor fix again

* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line (#289)

* Fix remaining sec inconsistency regarding the X-IF addition (#291)

* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line

* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* Clean Verilator warning about X-IF addition while keeping the RTL SEC-safe (#292)

* Changes to make the X_if addition compatible with the golden version of the core, minus the rf_we line

* [rt][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* [rtl][sec][xif] Made the length of the cve2_id_stage's rf_wdata_sel dependent on the whether the X-IF is present

* [rtl][xif][verilator] Clean warnings about enum-logic[] width mismatch on Verilator, while keeping the design logically equivalent. This is due to the cve2_decoder's rf_wdata_sel_o signal, which has its width dependent of the X-IF.

* fix xif

---------

Co-authored-by: FrancescoDeMalde-synthara <167969440+FrancescoDeMalde-synthara@users.noreply.github.com>
Co-authored-by: Cairo Caplan <cairo.caplan@eclipse-foundation.org>
2025-04-10 14:06:34 +02:00
..
cve2_alu.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_branch_predict.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_compressed_decoder.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_controller.sv removed unused irq_enable signal in controller (#178) 2023-12-12 13:40:59 +01:00
cve2_core.f Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_core.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_counter.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_cs_registers.sv RVFI CSRs improvements (#266) 2024-06-19 14:02:12 +02:00
cve2_csr.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_decoder.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_ex_block.sv add fetch_enable_i (#118) 2023-06-01 14:41:31 +02:00
cve2_fetch_fifo.sv fix design compiler (#270) 2024-05-27 15:23:26 +02:00
cve2_id_stage.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_if_stage.sv Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286) 2025-03-03 16:56:26 +01:00
cve2_load_store_unit.sv Feature/remove writeback stage (#56) 2023-05-31 14:44:59 +02:00
cve2_multdiv_fast.sv Feature/remove writeback stage (#56) 2023-05-31 14:44:59 +02:00
cve2_multdiv_slow.sv Feature/remove security (#52) 2023-02-28 14:03:42 +01:00
cve2_pkg.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_pmp.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_pmp_reset_default.svh Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_prefetch_buffer.sv remove branch predictor (#49) 2023-07-20 16:40:10 +02:00
cve2_register_file_ff.sv fix verilator and add clk gating cell (#114) 2023-05-24 15:18:26 +02:00
cve2_top.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_top_tracing.sv add X-IF 1.0 (#284) 2025-04-10 14:06:34 +02:00
cve2_tracer.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_tracer_pkg.sv Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
cve2_wb.sv add fetch_enable_i (#118) 2023-06-01 14:41:31 +02:00