github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-20 03:57:25 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
cve2/syn/tcl
History
Exact
szbieg b94bca939e
Adapt Yosys synthesis script to latch based register file and cve2_clock_gate (#125) 
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-07-28 15:06:10 +02:00
..
flow_utils.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
lr_synth_flow_var_setup.tcl Rename all modules to cve2 (#25) 2023-01-05 10:27:24 +01:00
sta_common.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
sta_open_design.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
sta_run_reports.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
sta_utils.tcl [syn] Fix timing reports in synthesis flow 2021-01-19 10:24:53 +00:00
yosys_common.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
yosys_post_synth.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
yosys_pre_map.tcl [syn] Synth flow improvements 2020-01-07 14:09:17 +00:00
yosys_run_synth.tcl Adapt Yosys synthesis script to latch based register file and cve2_clock_gate (#125) 2023-07-28 15:06:10 +02:00