cve2/vendor/google_riscv-dv/README.md at x_if

mirror of https://github.com/openhwgroup/cve2.git synced 2025-04-23 13:37:20 -04:00

Udi 216ba1a42d Update google_riscv-dv to google/riscv-dv@3cf691d

Update code from upstream repository https://github.com/google/riscv-
dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804

* remove hardcoded CSR names (Udi Jonnalagadda)
* initial custom CSR support (Udi Jonnalagadda)
* Add support for segmented load/store instructions (google/riscv-
  dv#656) (taoliug)
* fix post_randomize issue (aneels3)
* add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator)
* Ignore log and asm file (aneels3)
* Add Command Line Support (aneels3)
* support for command-line arguments (pvipsyash)
* Reorder import statements (aneels3)
* Modified function randomize_gpr in instr_stream file
  (ShraddhaDevaiya)
* Updated riscv_instr_sequence file and modified other python files to
  get main block in asm file. (ShraddhaDevaiya)
* Modify get_rand_instr() (aneels3)
* added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk)
* Aldec Riviera-PRO compiler command line arguments modified.
  (google/riscv-dv#638) (Dariusz Stachańczyk)
* allow coverage compilation to be run on LSF (google/riscv-dv#637)
  (udinator)
* Add CHIPS Alliance work group information to the README
  (google/riscv-dv#633) (taoliug)
* Add indexed/strided vector load/store instrution stream
  (google/riscv-dv#632) (taoliug)
* Add constraint for mtvec alignment in vectored interrupt mode
  (google/riscv-dv#631) (taoliug)
* Add bitstring requirement to pygen/experimental README
  (google/riscv-dv#630) (taoliug)
* Add unsupported load/store instruction filtering (google/riscv-
  dv#629) (taoliug)
* Add different methods to initialize the vregs (google/riscv-dv#627)
  (Josep Sans)
* Support a vetor instruction only mode (google/riscv-dv#626)
  (taoliug)
* Add riscv_instr_stream.py file (aneels3)
* Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari
  Esfeden)
* update pygen_src files (google/riscv-dv#612) (BharathNR1030)
* Fix typo (google/riscv-dv#624) (taoliug)
* Fix B-ext instruction generation issue (google/riscv-dv#620)
  (taoliug)

Signed-off-by: Udi <udij@google.com>

2020-07-24 00:09:07 -07:00

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Overview

RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification. It currently supports the following features:

Supported instruction set: RV32IMAFDC, RV64IMAFDC
Supported privileged mode: machine mode, supervisor mode, user mode
Page table randomization and exception
Privileged CSR setup randomization
Privileged CSR test suite
Trap/interrupt handling
Test suite to stress test MMU
Sub-program generation and random program calls
Illegal instruction and HINT instruction generation
Random forward/backward branch instructions
Supports mixing directed instructions with random instruction stream
Debug mode support, with fully randomized debug ROM
Instruction generation coverage model
Handshake communication with testbench
Support handcoded assembly test
Co-simulation with multiple ISS : spike, riscv-ovpsim, whisper, sail-riscv

Getting Started

Prerequisites

To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. Please make sure the EDA tool environment is properly setup before running the generator.

Install RISCV-DV

Getting the source

git clone https://github.com/google/riscv-dv.git

There are two ways that you can run scripts from riscv-dv.

For developers which may work on multiple clones in parallel, using directly run by python3 script is highly recommended. Example:

pip3 install -r requirements.txt    # install dependencies (only once)
python3 run.py --help

For normal users, using the python package is recommended. First, cd to the directory where riscv-dv is cloned and run:

export PATH=$HOME/.local/bin/:$PATH  # add ~/.local/bin to the $PATH (only once)
pip3 install --user -e .

This installs riscv-dv in a mode where any changes within the repo are immediately available simply by running run/cov. There is no need to repeatedly run pip install . after each change. Example for running:

run --help
cov --help

Use below command to install Verible, which is the tool to check Verilog style

verilog_style/build-verible.sh

This is the command to run Verilog style check. It's recommended to run and clean up all the style violations before submit a PR

verilog_style/run.sh

Document

To understand how to setup and customize the generator, please check the full document under docs directory. You can use the makefile to generate the document. HTML preview. You can find the prebuilt document under docs/build/singlehtml/index.html

External contributions and collaborations

RISC-V DV is now contributed to CHIPS Alliance. We have regular meetings to discuss the issues, feature priorities, development progress etc. Please join the mail group for latest status.

Please refer to CONTRIBUTING.md for license related questions.

Supporting model

Please file an issue under this repository for any bug report / integration issue / feature request. We are looking forward to knowing your experience of using this flow and how we can make it better together.

Disclaimer

This is not an officially supported Google product.

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