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Author SHA1 Message Date
Udi
216ba1a42d Update google_riscv-dv to google/riscv-dv@3cf691d 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804

* remove hardcoded CSR names (Udi Jonnalagadda)
* initial custom CSR support (Udi Jonnalagadda)
* Add support for segmented load/store instructions (google/riscv-
  dv#656) (taoliug)
* fix post_randomize issue (aneels3)
* add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator)
* Ignore log and asm file (aneels3)
* Add Command Line Support (aneels3)
* support for command-line arguments (pvipsyash)
* Reorder import statements (aneels3)
* Modified function randomize_gpr in instr_stream file
  (ShraddhaDevaiya)
* Updated riscv_instr_sequence file and modified other python files to
  get main block in asm file. (ShraddhaDevaiya)
* Modify get_rand_instr() (aneels3)
* added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk)
* Aldec Riviera-PRO compiler command line arguments modified.
  (google/riscv-dv#638) (Dariusz Stachańczyk)
* allow coverage compilation to be run on LSF (google/riscv-dv#637)
  (udinator)
* Add CHIPS Alliance work group information to the README
  (google/riscv-dv#633) (taoliug)
* Add indexed/strided vector load/store instrution stream
  (google/riscv-dv#632) (taoliug)
* Add constraint for mtvec alignment in vectored interrupt mode
  (google/riscv-dv#631) (taoliug)
* Add bitstring requirement to pygen/experimental README
  (google/riscv-dv#630) (taoliug)
* Add unsupported load/store instruction filtering (google/riscv-
  dv#629) (taoliug)
* Add different methods to initialize the vregs (google/riscv-dv#627)
  (Josep Sans)
* Support a vetor instruction only mode (google/riscv-dv#626)
  (taoliug)
* Add riscv_instr_stream.py file (aneels3)
* Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari
  Esfeden)
* update pygen_src files (google/riscv-dv#612) (BharathNR1030)
* Fix typo (google/riscv-dv#624) (taoliug)
* Fix B-ext instruction generation issue (google/riscv-dv#620)
  (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-07-24 00:09:07 -07:00
Udi
2be109ecca Update google_riscv-dv to google/riscv-dv@42264b7 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 42264b7782a10848935e995063c212893820e561

* fix pmp generation in bare program mode (Udi Jonnalagadda)
* Use literal instead array concatenation (Daniel Mlynek)
* fix access rights (Daniel Mlynek)
* fix in WA fo Aldec Riviera rand cannot be defined in packed struct
  (Daniel Mlynek)
* Fix ius compile error (Weicai Yang)
* fix pmp randomization to adhere to max offset (Udi Jonnalagadda)
* Add options to enable bitmanip by group (google/riscv-dv#532)
  (weicaiyang)
* [pmp] Relative addressing scheme to configure pmpaddr (google/riscv-
  dv#534) (udinator)
* redunant variable ALDEC_PATH removed (danielmlynek)
* riviera 2020.04 beta initial support (danielmlynek)
* Removed  system function call from the gen_section() function
  arguments list. (google/riscv-dv#531) (Dariusz Stachańczyk)
* Dynamic arrays declared as parameter changed to const variables.
  (google/riscv-dv#530) (danielmlynek)
* enhance pmp configuration to make safe region configurable (Udi
  Jonnalagadda)
* Fix a typo in riscvOVPsim (google/riscv-dv#529) (weicaiyang)

Signed-off-by: Udi <udij@google.com>
 2020-04-17 17:06:42 -07:00
udinator
f98cd607af
Update google_riscv-dv to google/riscv-dv@6bd3233 (#617) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6bd323385d454858ea5e50dedd42a563b37931fe

* VCS compile option fix (Udi Jonnalagadda)
* Improve pmp config object - enable cmdline args (Udi Jonnalagadda)
* Fix ovpsim setting (google/riscv-dv#478) (taoliug)
* IUS - enable rand structs in simulation (google/riscv-dv#477)
  (udinator)
* fix macro definition compile issue (Udi Jonnalagadda)
* add ISS command line options (google/riscv-dv#474) (udinator)
* Add style check (Weicai Yang)

Signed-off-by: Udi <udij@google.com>
 2020-02-20 15:07:12 -08:00
udinator
2be7413ac8
Update google_riscv-dv to google/riscv-dv@e63c542 (#587) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e63c5427b0bf543aebb9c62bba8217065b029a76

* Add pmp configuration object (Udi Jonnalagadda)
* add path for the prebuilt document (google/riscv-dv#469) (taoliug)
* Update document for directed assembly/C test (google/riscv-dv#467)
  (taoliug)
* Fix broken document link (google/riscv-dv#466) (taoliug)
* Add a runtime option to fix stack pointer (google/riscv-dv#465)
  (taoliug)
* Fix LR/SC instruction issue for RV32A (google/riscv-dv#464)
  (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-02-06 11:03:22 -08:00
udinator
3d8089c235
Update google_riscv-dv to google/riscv-dv@a655f34 (#564) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision a655f34eb5058da442b38ca010b0d008291c11b5

* Support running C test (google/riscv-dv#453) (Hai Hoang Dang)
* run.py: Do not compare csv file when specified -debug switch
  (google/riscv-dv#451) (Hai Hoang Dang)
* adjust location of nested interrupt mstatus.mie enable
  (google/riscv-dv#444) (udinator)
* Implement storing the commands that would be executed as a script
  (google/riscv-dv#450) (Hai Hoang Dang)
* Move document from README to docs, add HTML preview for the new doc
  (google/riscv-dv#448) (taoliug)
* Use single HTML format (google/riscv-dv#447) (taoliug)
* Update HTML document (google/riscv-dv#446) (taoliug)
* Add framework for custom extensions (google/riscv-dv#442) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-01-23 15:10:14 -08:00
udinator
8ce399dbe6
Update google_riscv-dv to google/riscv-dv@d23da38 (#549) 
* update vendor.hjson to exclude generated pdf file

* Update google_riscv-dv to google/riscv-dv@d23da38

Update code from upstream repository https://github.com/google/riscv-
dv to revision d23da3862f95954e6374aaec787e0fb0c1878a16

* fix matched_list and directed_list size comparisons (Udi
  Jonnalagadda)
* Add run_cmd_output for reporting all debug command lines
  (google/riscv-dv#436) (Hai Hoang Dang)
*  Resolve: missing pass gcc_opts from YAML for GCC compile command
  (google/riscv-dv#435) (Hai Hoang Dang)
* Sphinx: Add generating pdf file (google/riscv-dv#431) (Hai Hoang
  Dang)
* integrate directed asm_tests with yaml flow (Udi Jonnalagadda)
* Fix running cov without arguments (google/riscv-dv#433) (Hai Hoang
  Dang)
* Add setup Travis CI for tracking build docs, and install
  (google/riscv-dv#430) (Hai Hoang Dang)
* Add handling KeyboardInterrupt for run_cmd and run_parallel_cmd
  (google/riscv-dv#424) (Hai Hoang Dang)
* Sphinx: add basic page for structure of the document (google/riscv-
  dv#428) (Hai Hoang Dang)
* README.md: Update the information relating to usage (google/riscv-
  dv#426) (Hai Hoang Dang)
* Add initial Sphinx docs (google/riscv-dv#427) (Hai Hoang Dang)
* Fix typo in the testlist (google/riscv-dv#423) (taoliug)
* Add try-except for handling KeyboardInterrupt (google/riscv-dv#421)
  (Hai Hoang Dang)
* Update information about instruction for running scripts
  (google/riscv-dv#420) (Hai Hoang Dang)
* Add vector permutation, reduction, mask instructions (google/riscv-
  dv#422) (taoliug)
* Python package (google/riscv-dv#419) (Hai Hoang Dang)
* Refactor the code for cov.py (google/riscv-dv#416) (Hai Hoang Dang)
* Update ovpsim config for vector extesion (google/riscv-dv#415)
  (taoliug)
* Fix coverage flow issue (google/riscv-dv#414) (taoliug)
* Add missing license header (google/riscv-dv#412) (taoliug)
* Fix typo in cov_test (google/riscv-dv#410) (taoliug)
* Add vector floating point instructions (google/riscv-dv#409)
  (taoliug)
* Add fixed point arithmetic vector instruction (google/riscv-dv#408)
  (taoliug)
* cov.py: Generate error when it cannot find spike_sim directory
  (google/riscv-dv#407) (Hai Hoang Dang)
* Add vector CSR initialization routine (google/riscv-dv#405)
  (taoliug)
* Create vector extension target, add basic enums (google/riscv-
  dv#404) (taoliug)
* Fix qrun sim warning (google/riscv-dv#402) (taoliug)
* Try fix qrun constraint solver issue (google/riscv-dv#401) (taoliug)
* Fix simulation warning (google/riscv-dv#400) (taoliug)
* run.py: Generate error for gcc compile when it cannot find assembly
  files (google/riscv-dv#398) (Hai Hoang Dang)
* Add numeric corner case test, misc coverage fixes (google/riscv-
  dv#396) (taoliug)
* Switch to new CSV format (google/riscv-dv#395) (taoliug)
* misc fixes for the coverage model (google/riscv-dv#394) (taoliug)
* Fix new CSV coverage flow issue (google/riscv-dv#392) (taoliug)
* Integrate new trace CSV format with coverage flow (google/riscv-
  dv#390) (taoliug)
* Add experimental script for the new CSV format (google/riscv-dv#389)
  (taoliug)
* Support flexible running directed assembly tests (google/riscv-
  dv#386) (Hai Hoang Dang)
* run.py: Enhance passing argument for gen function (google/riscv-
  dv#382) (Hai Hoang Dang)
* Fix qrun issue, take 2 (google/riscv-dv#384) (taoliug)
* Attempt to fix qrun issue (google/riscv-dv#383) (taoliug)
* Fix (google/riscv-dv#381) (taoliug)
* Fix typo (google/riscv-dv#380) (taoliug)
* Fix qrun simulation issue (google/riscv-dv#379) (taoliug)
* Cleaning the output directory by default. Using exist output
  directory (google/riscv-dv#377) (Hai Hoang Dang)
* Fix ius compilation error temporarily (google/riscv-dv#378)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#376) (taoliug)
* Add unaligned jump instruction support (google/riscv-dv#375)
  (taoliug)
* move handcoded asm_test generation into separate output directory
  (Udi Jonnalagadda)
* Ignore return code for ovpsim sim (google/riscv-dv#371) (taoliug)
* Fix mie compare mismatch (google/riscv-dv#370) (taoliug)
* Fix directory/file name for assembly test flow (google/riscv-dv#369)
  (taoliug)
* Fix error in README (google/riscv-dv#368) (taoliug)
* Add sample rv32imc test (google/riscv-dv#367) (taoliug)
* Fix typo (google/riscv-dv#366) (taoliug)
* Support running regression with hand-coded assembly tests
  (google/riscv-dv#365) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-01-09 15:04:39 -08:00
udinator
0d6ccbf1f6
Update google_riscv-dv to google/riscv-dv@5b1dd4e (#523) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 5b1dd4e2eb11d49d3275da80953efc0c50f90447

* Add compliance mode to coverage model (google/riscv-dv#361)
  (taoliug)
* Revert " Make assign_operand become a method of class
  RiscvInstructionTraceEntry  (google/riscv-dv#357)" (google/riscv-
  dv#360) (taoliug)
* Fix script issue (google/riscv-dv#358) (taoliug)
*  Make assign_operand become a method of class
  RiscvInstructionTraceEntry  (google/riscv-dv#357) (Hai Hoang Dang)
* Remove unused variable (google/riscv-dv#348) (Hai Hoang Dang)
* Functional coverage improvement (google/riscv-dv#356) (taoliug)
* Fix list access exception thrown when parsing ovpsim illegal
  instruction (Udi Jonnalagadda)
* Add compliance mode and RTL mode to the coverage model
  (google/riscv-dv#354) (taoliug)
* Fix lr/sc sequence (google/riscv-dv#353) (taoliug)
* Fix minor illegal instruction issue (google/riscv-dv#351) (taoliug)
* Migrate to new instruction class (google/riscv-dv#350) (taoliug)
* misc issue fixes (google/riscv-dv#349) (taoliug)
* Update README to add contact info for the collaboration request
  (google/riscv-dv#347) (taoliug)
* Support running specific multiple tests (google/riscv-dv#346) (Hai
  Hoang Dang)
* Fix rv64 coverage model issue (google/riscv-dv#344) (taoliug)
* Fix the link for yaml/base_testlist.yaml (google/riscv-dv#343) (Hai
  Hoang Dang)
* refactor debug ROM generation (Udi Jonnalagadda)
* Add a runtime option to run with experimental features
  (google/riscv-dv#341) (taoliug)
* Fix a few issues with the new instruction class (google/riscv-
  dv#340) (taoliug)
* Improve performance of new experimental instruction class
  (google/riscv-dv#339) (taoliug)
* Fix CSR randomization bug when generating loops (google/riscv-
  dv#337) (udinator)
* Add support coverage flow for qrun, and minor fix for cov.py
  (google/riscv-dv#335) (Hai Hoang Dang)
* [ovpsim] Coding style fixes, fix floating point compare mismatch
  (google/riscv-dv#334) (taoliug)
* Fix ius flow issue (google/riscv-dv#333) (taoliug)
* Fix a few new instruction class issues (google/riscv-dv#332)
  (taoliug)
* Added two includes and starting variables for adding bitmanip
  extension (google/riscv-dv#328) (simond-imperas)
* Integrate experimental instruction class (google/riscv-dv#331)
  (taoliug)
* Minor fixes to run.py (google/riscv-dv#330) (taoliug)
* Run.py: minor refactor the code for compile, and simulate
  (google/riscv-dv#326) (Hai Hoang Dang)
* Add requirements for install dependencies (google/riscv-dv#325) (Hai
  Hoang Dang)
* Adding support qrun simulator (google/riscv-dv#324) (Hai Hoang Dang)
* Add new experimental instruction class (google/riscv-dv#323)
  (taoliug)
* Added command line control of coverage and added hooks for vector
  coverage development (google/riscv-dv#317) (simond-imperas)
* Fix compilation issue (google/riscv-dv#322) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2019-12-16 11:47:53 -08:00
udinator
6ce8b6ecf2
Update google_riscv-dv to google/riscv-dv@4b333ba (#462) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e

* cg instantion based on supported_isa (google/riscv-dv#303)
  (udinator)
* Fix coverage collection issue, change default target to rv32imc
  (google/riscv-dv#302) (taoliug)
* Integrate whisper(swerv-ISS) (google/riscv-dv#301) (taoliug)
* Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode
  (google/riscv-dv#299) (taoliug)
* Fix jalr handling issue for ovpsim (google/riscv-dv#298) (taoliug)
* Add noclean option, change default output directory of coverage
  collection (google/riscv-dv#297) (taoliug)
* Enable using core trace logs for coverage collection (google/riscv-
  dv#291) (udinator)
* Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296)
  (taoliug)
* fixed line widths (x2) and check error returns for any questa
  simalator (google/riscv-dv#293) (simond-imperas)
* Unknown instruction fix (google/riscv-dv#290) (simond-imperas)
* Fix ovpsim log process issue (google/riscv-dv#289) (udinator)
* adding riscvOVPsim vector instruction trace to csv processing -
  start (3rd Attempt) (google/riscv-dv#288) (simond-imperas)

Signed-off-by: Udi <udij@google.com>
 2019-11-12 14:39:22 -08:00
udinator
f3f3f3de09
Update google_riscv-dv to google/riscv-dv@cce71d2 (#445) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cce71d24b56f641d994fbf69b8b50aa3756b9322

* Add handshake documentation (Udi)
* Fix coverage debug mode (google/riscv-dv#281) (taoliug)
* Fix coverage script issue (google/riscv-dv#280) (taoliug)
* code block highlight (google/riscv-dv#279) (taoliug)
* Replace setting directory with a default target (google/riscv-
  dv#278) (taoliug)
* fixed trace handling issues (google/riscv-dv#274) (eroom)
* Allow running the script from other directory (google/riscv-dv#277)
  (taoliug)
* Add dummy writes to status and ie CSRs (Udi)
* Script typo fix (google/riscv-dv#272) (Dan Petrisko)
* Fix misa setup issue (google/riscv-dv#271) (taoliug)
* Enable mie.mtie for timer interrupts (Udi)
* Update illegal system instr generation (Udi)
* Fix duplicate (google/riscv-dv#268) (taoliug)
* Add experimental instruction distribution control (google/riscv-
  dv#267) (taoliug)
* Update README to clarify the flow setup instructions (google/riscv-
  dv#265) (taoliug)
* Remove debug logging (google/riscv-dv#264) (taoliug)
* Fix compressed instruction test setup (google/riscv-dv#263)
  (taoliug)
* adding __init__ in the scripts dir since python3.7 requires that for
  directories to be recognized as modules (google/riscv-dv#252)
  (Jielun Tan)
* Fix riscvOVPsim.ic (google/riscv-dv#261) (taoliug)
* Fix ovpsim sim problem (google/riscv-dv#260) (taoliug)
* Add alternative command options for directed instruction stream
  (google/riscv-dv#254) (taoliug)
* Fix dsim compilation issue (google/riscv-dv#253) (taoliug)
 2019-11-04 10:48:02 -08:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead

* Incorrect deletion (google/riscv-dv#249) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248)
  (eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247) (taoliug)
* Coverage model fixes (google/riscv-dv#246) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#243) (taoliug)
* Functional coverage improvement (google/riscv-dv#242) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
  dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240)
  (taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239)
  (taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234)
  (taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233)
  (eroom)
* Refine README structure (google/riscv-dv#231) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230)
  (taoliug)
 2019-10-23 10:46:31 -07:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf (#406) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd

* Add more ebreak generation control (google/riscv-dv#229) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226)
  (taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225)
  (Greg Chadwick)
* Minor README typo (google/riscv-dv#219) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
  dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220)
  (taoliug)
* Fix floating point comparison issue (google/riscv-dv#218) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215)
  (Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
  (google/riscv-dv#214) (Hai Hoang Dang)
 2019-10-16 17:50:23 -07:00
udinator
4a1806f16f
Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2

* Workaround for dsim compile issue (google/riscv-dv#211) (taoliug)
* Add a --seed_yaml option to rerun a regression with the same seed of
  a prior regression (google/riscv-dv#210) (taoliug)
* Update questa covearge options (google/riscv-dv#209) (taoliug)
* Fix disable_compressed_instr option (google/riscv-dv#205) (taoliug)
* Fix non-compressed instruction test (google/riscv-dv#203) (taoliug)
* Debug single step functionality and config knobs (Udi)
* Fix no_branch_jump option (google/riscv-dv#200) (taoliug)
* Add more functional covergroup (google/riscv-dv#199) (taoliug)
* Allow randomly reserve GPR for TP/SP, improve functional coverage
  (google/riscv-dv#198) (taoliug)
* Allow running the coverage script with LSF (google/riscv-dv#195)
  (taoliug)
* Add support for disable_compressed_instr (google/riscv-dv#194)
  (taoliug)
* Improve coverage collection performance (google/riscv-dv#193)
  (taoliug)
* Signature_addr_reg constraint update (Udi)
* Add a debug mode for functional coverage (google/riscv-dv#191)
  (taoliug)
* Fix typo in README (google/riscv-dv#189) (taoliug)
* Constrain scratch_reg (google/riscv-dv#188) (udinator)
* Update README for the coverage flow (google/riscv-dv#187) (taoliug)
* Add basic privileged CSR cover group (google/riscv-dv#186) (taoliug)
* Fix cover point definition (google/riscv-dv#185) (taoliug)
* Fix ovpsim log compare issue (google/riscv-dv#183) (udinator)
 2019-10-08 14:22:05 -07:00
udinator
95a82f8be8
Update google_riscv-dv to google/riscv-dv@d341944 (#353) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision d3419444ca2fdb499a204587b2d36c6f5c1e0c44

* Update README (Udi)
* Add knob to enable full CSR randomization, fix mstatus.spp (Udi)
 2019-09-25 18:40:36 -07:00
udinator
2c71a26680
Update google_riscv-dv to google/riscv-dv@0d2b5b7 (#321) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0d2b5b7b8b1cdbce74d9e123a427052b12accd7b

* Add user extension support (google/riscv-dv#163) (taoliug)
* Update README (google/riscv-dv#162) (taoliug)
* Fix compilation issue (google/riscv-dv#161) (taoliug)
* Fix compilation issue (google/riscv-dv#160) (taoliug)
* Adding dsim support (google/riscv-dv#159) (taoliug)
* Fix RV64A typo (google/riscv-dv#158) (taoliug)
 2019-09-16 13:43:35 -07:00
udinator
3fcf5a634d
Update google_riscv-dv to google/riscv-dv@c98d89c (#312) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (google/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (google/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (google/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (google/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (google/riscv-dv#148) (taoliug)
* Remove temp files (google/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (google/riscv-dv#144)
  (taoliug)
* Fix typo (google/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (google/riscv-dv#139) (taoliug)
* Remove obsolete sample program (google/riscv-dv#138) (taoliug)
* Update readme (google/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (google/riscv-dv#135) (taoliug)
* Re-organize text and data section (google/riscv-dv#134) (taoliug)
* Refine the bare program mode (google/riscv-dv#133) (taoliug)
* Add a bare program mode (google/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (google/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (google/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (google/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (google/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (google/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix google/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)
 2019-09-13 14:34:56 -07:00
udinator
ce8be4f2fd
Update google_riscv-dv to google/riscv-dv@faddfa4 (#263) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision faddfa49f456f3f8ef8c4231865994b7b13aa96d

* Obsolete test clean up (Tao Liu)
* Remove the old flow (Tao Liu)
* minor fix, update README for A extension support (Tao Liu)
* Add basic atomic instruction test (Tao Liu)
* Add RV32A/RV64A instructions (google/riscv-dv#95) (Tao Liu)
* Fix the missing GPR save operations for exception handling (Tao Liu)
* Generate handshake sequence to communicate with testbench (Udi)
* Fix compare error (Tao Liu)
* Fix compare error (Tao Liu)
* Initial signature enum for handshake protocol (Udi)
 2019-08-26 11:41:37 -07:00
taoliug
a752277247
Update google_riscv-dv to 73274f2 (#254) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 73274f227000f1316cb201a8503aad437e427948

* Merge pull request #88 from google/dev (taoliug)
* Fix spike log processing issue (Tao Liu)
* Merge pull request #87 from google/dev (udinator)
* Add vectored interrupt support (Tao Liu)
* Merge pull request #85 from udinator/debug (udinator)
* Add debug sub-programs, and extra options to generator (Udi)
* Merge pull request #84 from imphil/fix-apache-urls (taoliug)
* Fix license URLs in comments (Philipp Wagner)
 2019-08-21 17:14:15 -07:00
udinator
6ccd2b698d Update google_riscv-dv to google/riscv-dv@7cce16c (#246) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 7cce16c0a212c8713a82516fbf8f2570d3dc4505

* Update spike log processing script to include full trace information
  (Tao Liu)
* Add new tests (Tao Liu)
* Add basic debug test functionality (Udi)
* fix spelling error, fix output directory arg (Udi)
* Add shorten option (dang hai)
* Support SAIL-RISCV ISSi, update README (Tao Liu)
* Fix CSR map copy issue (Tao Liu)
 2019-08-16 09:43:27 -07:00
udinator
97105f42b1 Update google_riscv-dv to google/riscv-dv@e905e9f (#234) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e905e9f134e0b7cf7da491218d1a30c75ce8649a

* add pass_val and fail_val into csr test flow for EOT correctness
  checking (Udi)
* Support unaligned load/store (Tao Liu)
* refactored test generation logic (Udi)
* refactored test generation logic (Udi)
* Give error when mutually exclusive between -co, and -so argument
  (dang hai)
* documentation, and small fixes (Udi)
* no_iss bug (Udi)
* no_iss/no_post_compare optional, CSR read_only is now only specified
  at field level granularity (Udi)
* made no_iss optional (Udi)
* rm print (Udi)
* setup_logging call (Udi)
* undo overriding --verbose in run.py, comment cleanup in csr gen
  script (Udi)
* missed verbose arguments (Udi)
* verbose arg (Udi)
* updated csr description, integrated csr test into flow (Udi)
* updated csr description, integrated csr test into flow (Udi)
* Enhance verbose information by logging instead of using print (dang
  hai)
* Report date time for output directory (dang hai)
* Add main entry point for run.py (dang hai)
* Separate command line parser by function (dang hai)
* Skip generating S/U mode program for machine mode test (Tao Liu)
* minor update to README.md (Tao Liu)
* Update the README.md to match command reference from --help (Tao
  Liu)
* Ignore untrack file from python script (dang hai)
* Make questa work for new YAML based regression flow (dang hai)
* Fix typo in README (Tao Liu)
* Fix README google/riscv-dv#54 (Tao Liu)
* changed formatting of generator option table (Udi)
 2019-08-12 16:22:07 -07:00
taoliug
ba5c63b8d1 Update google_riscv-dv to a07e0a7 (#203) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision a07e0a726edf0230314c08d31546eecbed23054b

* Merge pull request #53 from google/flow (taoliug)
* Update README file for the new flow (Tao Liu)
* Merge pull request #52 from google/flow (taoliug)
* Add timeout mechanism to the flow (Tao Liu)
* Merge pull request #51 from google/flow (taoliug)
* Simulation flow update (Tao Liu)
* Merge pull request #50 from udinator/master (taoliug)
* added license for csr_template.yaml (Udi)
* Merge pull request #49 from google/dev (taoliug)
* Update log process script (Tao Liu)
* Merge pull request #48 from google/dev (taoliug)
* Fix illegal instruction issue (Tao Liu)
* Merge pull request #47 from google/dev (taoliug)
* Refactor the simulation flow (Tao Liu)
* Merge pull request #45 from danghai/master (taoliug)
* Add .gitignore to remove untracked files (danghai)
* Fix warning from Questa optmize (danghai)
* Add optimize log file for Questa simulator (danghai)
* New YAML based simulation flow (Tao Liu)
* Merge pull request #40 from scottj97/typos-redone (taoliug)
* Fix typos in comments (Scott Johnson)
* Fix typos/grammar in README (Scott Johnson)
* Merge pull request #43 from udinator/master (taoliug)
* use hex format in YAML description (Udi)
* CSR test description (Udi)
* removed run script (Udi)
* Modified CSR test generation code to adhere to style guidelines.
  (Udi)
* Merge pull request #41 from vandanaprabhu/questa (taoliug)
* CSR Generation Script and YAML template (Udi)
* Prevent Xcelium from attempting to run a simulation during the
  compile step (Scott Johnson)
* Document support for Questa (Scott Johnson)
* Fix simulation-time warnings from Mentor Questa (Scott Johnson)
* Fix compile warnings from Mentor Questa (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Adding support for using the Questa simulator (Vandana Prabhu)
* Pass proper seed to Cadence Xcelium simulator (Scott Johnson)
* Convert compile commands to functions instead of variables (Scott
  Johnson)
 2019-08-01 09:53:26 -07:00
Tao Liu
bdb089d456 Update google_riscv-dv to 215e064 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 215e0646ae9909aa0e78d6e91f4f33ed77f95e43
 2019-05-31 17:39:28 +01:00