The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Sven Stucki 10bc98382e More cleanup, fixed more warnings		2015-07-24 02:53:55 +02:00
include	Fixed Verilator width warnings where appropriate	2015-07-23 01:59:45 +02:00
alu.sv	Fixed Verilator width warnings where appropriate	2015-07-23 01:59:45 +02:00
compressed_decoder.sv	Fixed Verilator width warnings where appropriate	2015-07-23 01:59:45 +02:00
controller.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
cs_registers.sv	Fixed inferred latches in RV	2015-06-05 12:23:35 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
exc_controller.sv	RiscV: exception controller and CSR core and synthesis update	2015-05-26 00:08:44 +02:00
id_stage.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
if_stage.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
instr_core_interface.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
load_store_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
mult.sv	Fixed Verilator width warnings where appropriate	2015-07-23 01:59:45 +02:00
register_file.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
riscv_core.sv	More cleanup, fixed more warnings	2015-07-24 02:53:55 +02:00
wb_stage.sv	More warnings fixed	2015-07-23 02:30:44 +02:00