The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Sven Stucki 186245bc49 Cleanup; removed carry and overflow (mostly)		2015-07-23 01:20:57 +02:00
include	Another compressed instruction, include guards for verilator	2015-07-21 17:57:49 +02:00
alu.sv	Realigned RiscV with Or10n, code cleanup	2015-05-24 23:04:36 +02:00
compressed_decoder.sv	Another compressed instruction, include guards for verilator	2015-07-21 17:57:49 +02:00
controller.sv	Cleanup; removed carry and overflow (mostly)	2015-07-23 01:20:57 +02:00
cs_registers.sv	Fixed inferred latches in RV	2015-06-05 12:23:35 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	Cleanup; removed carry and overflow (mostly)	2015-07-23 01:20:57 +02:00
exc_controller.sv	RiscV: exception controller and CSR core and synthesis update	2015-05-26 00:08:44 +02:00
id_stage.sv	Cleanup; removed carry and overflow (mostly)	2015-07-23 01:20:57 +02:00
if_stage.sv	Major RiscV update, now supports compressed instructions (partially, work-in-progress until full standard is released)	2015-06-12 19:26:16 +02:00
instr_core_interface.sv	Fixed space/tab mixture and indentation in instr_core_interface	2015-04-16 15:21:03 +02:00
load_store_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
mult.sv	Realigned RiscV with Or10n, code cleanup	2015-05-24 23:04:36 +02:00
register_file.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
riscv_core.sv	Cleanup; removed carry and overflow (mostly)	2015-07-23 01:20:57 +02:00
wb_stage.sv	Fixed inferred latches in RV	2015-06-05 12:23:35 +02:00