The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Andreas Traber 33987fcc6c Handle boot address correctly		2016-02-09 17:38:41 +01:00
docs/datasheet	Allow nested interrupts and save current value of MSTATUS to MESTATUS	2016-02-09 09:21:26 +01:00
include	Finish sim checker. It passes coremark on pulpino, so relatively mature :-)	2016-02-07 13:21:08 +01:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Clean headers	2015-12-14 16:39:16 +01:00
compressed_decoder.sv	Clean headers	2015-12-14 16:39:16 +01:00
controller.sv	Allow nested interrupts and save current value of MSTATUS to MESTATUS	2016-02-09 09:21:26 +01:00
cs_registers.sv	Allow nested interrupts and save current value of MSTATUS to MESTATUS	2016-02-09 09:21:26 +01:00
debug_unit.sv	Clean headers	2015-12-14 16:39:16 +01:00
decoder.sv	Change to new encoding from Eric	2016-01-21 13:08:16 +01:00
ex_stage.sv	Remove mscratch and change the way csr works	2015-12-26 00:15:00 +01:00
exc_controller.sv	Allow nested interrupts and save current value of MSTATUS to MESTATUS	2016-02-09 09:21:26 +01:00
hwloop_controller.sv	Clean headers	2015-12-14 16:39:16 +01:00
hwloop_regs.sv	Clean headers	2015-12-14 16:39:16 +01:00
id_stage.sv	Allow nested interrupts and save current value of MSTATUS to MESTATUS	2016-02-09 09:21:26 +01:00
if_stage.sv	only jump once even when there are stalls	2015-12-26 13:30:44 +01:00
LICENSE	Added LICENSE file and started adding headers	2015-12-11 17:20:07 +01:00
load_store_unit.sv	Clean headers	2015-12-14 16:39:16 +01:00
mult.sv	Clean headers	2015-12-14 16:39:16 +01:00
prefetch_buffer.sv	Make sure the address is kept stable when we are waiting for a gnt	2016-01-23 00:35:01 +01:00
prefetch_L0_buffer.sv	Clean headers	2015-12-14 16:39:16 +01:00
register_file.sv	Clean headers	2015-12-14 16:39:16 +01:00
register_file_ff.sv	Clean headers	2015-12-14 16:39:16 +01:00
riscv_core.sv	Handle boot address correctly	2016-02-09 17:38:41 +01:00
riscv_simchecker.sv	Handle boot address correctly	2016-02-09 17:38:41 +01:00
riscv_tracer.sv	Simchecker now also supports rvc	2016-02-08 13:08:56 +01:00
src_files.txt	added src_files.txt	2016-02-03 17:27:24 +01:00