mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-23 05:27:30 -04:00
Handle boot address correctly
This commit is contained in:
parent
c39e27f3ac
commit
33987fcc6c
2 changed files with 7 additions and 2 deletions
|
@ -767,6 +767,8 @@ module riscv_core
|
|||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.fetch_enable ( fetch_enable_i ),
|
||||
.boot_addr ( boot_addr_i ),
|
||||
.core_id ( core_id_i ),
|
||||
.cluster_id ( cluster_id_i ),
|
||||
|
||||
|
|
|
@ -33,6 +33,8 @@ module riscv_simchecker
|
|||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic fetch_enable,
|
||||
input logic [31:0] boot_addr,
|
||||
input logic [4:0] core_id,
|
||||
input logic [4:0] cluster_id,
|
||||
|
||||
|
@ -110,8 +112,9 @@ module riscv_simchecker
|
|||
// simchecker initialization
|
||||
initial
|
||||
begin
|
||||
#1;
|
||||
dpi_simdata = riscv_checker_init(32'h80, core_id, cluster_id);
|
||||
wait(rst_n == 1'b1);
|
||||
wait(fetch_enable == 1'b1);
|
||||
dpi_simdata = riscv_checker_init(boot_addr, core_id, cluster_id);
|
||||
end
|
||||
|
||||
// virtual ID/EX pipeline
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue