e37c81a1c1
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 067272a253f4eeed4ae58a9171ee266256528117 * [dv/common] initial support for shadow register (Cindy Chen) * [rtl/prince] Small fixes for PRINCE cipher logic (Udi Jonnalagadda) * [dv doc] Fix rendered testplan table (Srikrishna Iyer) * [prim/dv] Enable coverage collection for PRESENT (Udi Jonnalagadda) * [dvsim/syn] Minor fix in message reporting (Michael Schaffner) * [prim] Make prim_clock_inverter a tech specific prim (Michael Schaffner) * [vsg] fix _i/_o for several modules (Scott Johnson) * [doc] Update Licence Headers to fit agreed style (Sam Elliott) * [vsg] fix _i/_o usage on sram_arbiter (Scott Johnson) * [vsg] fix _i/_o usage on prim_fifo (Scott Johnson) * switch to host, primary, or over-arching as appropriate (Scott Johnson) * [dvsim/lint/syn] Properly set the errors_seen value to return nonzero status (Michael Schaffner) * [dvsim] Fix open() call with Pathlib for older Python versions (Michael Schaffner) * [style-lint] Last round of minor fixes to get all targets clean (Michael Schaffner) * [prim] Add shadow register primitive (Pirmin Vogel) * [flash_ctrl] Cosmetic updates enum literals (Srikrishna Iyer) * [tool/script] delete clean section in make files (Cindy Chen) * [dvsim] Add git commit and branch info to reports (Michael Schaffner) * [dvsim/syn/lint] Add options to selectively sanitize reports (Michael Schaffner) * [lint] Update waiver file for prim_generic_pad_wrapper (Michael Schaffner) * [prim_pad_wrapper] Update pad wrapper (Michael Schaffner) * [alert_handler/rtl] priority between ping_ok and sig_int_err (Cindy Chen) * [prim] Add a few prim cells needed for clock / resets (Timothy Chen) * [dv] added default timeout message to DV_SPINWAIT (Srikrishna Iyer) * [dv] Add mechanism to configure vseq via knobs (Srikrishna Iyer) * Make the wmask assertion in prim_generic_ram_*p only apply to writes (Rupert Swarbrick) * [prim_gate_gen] Recalibrate gate generator for new std cells (Michael Schaffner) * [primgen] Use SafeDumper for YAML (Philipp Wagner) * [primgen] Fix some flake8-reported style issues (Philipp Wagner) * [prim] Improve extraction of parameter port list (Philipp Wagner) * [prim] Remove outdated comment from primgen (Philipp Wagner) * Added missing include prim_assert.sv (Dawid Zimonczyk) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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| ci | ||
| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
| rtl | ||
| shared | ||
| syn | ||
| util | ||
| vendor | ||
| .clang-format | ||
| .gitignore | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_core_tracing.core | ||
| ibex_icache.core | ||
| ibex_pkg.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
| src_files.yml | ||
| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.
This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|
| Features | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 2.47 | 3.13 | 3.05 |
| Area - Yosys (kGE) | 33.15 | 39.03 | 63.32 |
| Area - Commercial (estimated kGE) | ~27 | ~31 | ~50 |
| Verification status | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform.
Note that different ISAs (use of B and C extensions) give the best results for different configurations.
See the Benchmarks README for more information.
The "maxperf-pmp-bmfull" configuration sets a
SpecBranchparameter inibex_core.sv; this helps timing but has a small negative performance impact. - Yosys synthesis area numbers are based on the Ibex basic synthesis flow.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a new configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.