cve2/rtl
Pirmin Vogel e9a6295e57 [rtl] By default, forward incoming instruction in C decoder
This commit modifies the compressed decoder to forward the incoming
instruction to the output. It is marked as legal, unless:
1) the decoder cannot determine if the instruction is compressed (e.g.
   because of unknown selector bits), or
2) the instruction is compressed but
    a) it cannot be successfully decompressed (e.g. because of unknown
       selector bits), or
    b) it is indeed illegal.

In the case of 2b) the compressed decoder may output an illegal
decompressed instruction instead of the incoming instruction.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2019-12-20 10:09:09 +01:00
..
ibex_alu.sv [rtl] Remove unused set-less-or-equal-than ALU ops 2019-11-01 11:51:25 +00:00
ibex_compressed_decoder.sv [rtl] By default, forward incoming instruction in C decoder 2019-12-20 10:09:09 +01:00
ibex_controller.sv [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_core.f Add local fast interrupts, remove legacy interrupts 2019-07-24 14:22:00 +01:00
ibex_core.sv [RTL] Only restore from mstack in nmi mode 2019-12-16 19:51:22 +00:00
ibex_core_tracing.sv [dbg] Add minimal hardware breakpoint support 2019-12-11 15:02:06 +00:00
ibex_cs_registers.sv [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_decoder.sv [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_ex_block.sv Error synthesis in Vivado 2019-10-28 20:36:37 +00:00
ibex_fetch_fifo.sv [rtl] Use macros for all SystemVerilog assertions 2019-12-20 10:09:09 +01:00
ibex_id_stage.sv [rtl] Use macros for all SystemVerilog assertions 2019-12-20 10:09:09 +01:00
ibex_if_stage.sv [rtl] Use macros for all SystemVerilog assertions 2019-12-20 10:09:09 +01:00
ibex_load_store_unit.sv [rtl] Use macros for all SystemVerilog assertions 2019-12-20 10:09:09 +01:00
ibex_multdiv_fast.sv [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_multdiv_slow.sv [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
ibex_pkg.sv [dbg] Add minimal hardware breakpoint support 2019-12-11 15:02:06 +00:00
ibex_pmp.sv [RTL PMP] Fix address matching bugs 2019-10-03 10:41:29 +01:00
ibex_prefetch_buffer.sv [rtl] Implement FENCE.I 2019-11-27 08:47:26 +00:00
ibex_register_file_ff.sv Mention CREDITS.md in license header 2019-08-27 18:10:02 +01:00
ibex_register_file_latch.sv Register file: update comments 2019-08-29 15:24:18 +01:00
ibex_tracer.sv [RTL/Tracer] Fix compressed jump RD write (#416) 2019-10-23 10:30:11 -07:00
ibex_tracer_pkg.sv Implement Verilator-compatible tracer, and use it 2019-10-02 18:28:26 +01:00