mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Merge branch 'openhwgroup:main' into main
This commit is contained in:
Lee Moore
GitHub
commit
0a0d6dd25e
63 changed files with 2780 additions and 2074 deletions
4
Makefile
4
Makefile
|
|
@ -4,8 +4,8 @@
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|||
|
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all:
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make install
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make testfloat
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make riscof
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make riscof
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make testfloat
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make verify
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make coverage
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make benchmarks
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|
|
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@ -6,7 +6,10 @@
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## Modified:
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##
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## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
|
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## separate files, one for each program.x4
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## separate files, one for each program.
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## Input: branch log file generated by modelsim
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## output: outputs to directory branch a collection of files with the branch outcomes
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## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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##
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|
|
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619
bin/parseHPMC.py
619
bin/parseHPMC.py
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@ -1,8 +1,8 @@
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#!/usr/bin/python3
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###########################################
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## Written: Ross Thompson ross1728@gmail.com
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## Created: 4 Jan 2022
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## Written: Rose Thompson ross1728@gmail.com
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## Created: 20 September 2023
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## Modified:
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##
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## Purpose: Parses the performance counters from a modelsim trace.
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@ -28,106 +28,30 @@
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import os
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import sys
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import matplotlib.pyplot as plt
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import re
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import math
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import numpy as np
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import argparse
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#RefData={'twobitCModel' :(['6', '8', '10', '12', '14', '16'],
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# [11.0680836450622, 8.53864970807778, 7.59565430177984, 6.38741598498948, 5.83662961500838, 5.83662961500838]),
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# 'gshareCModel' : (['6', '8', '10', '12', '14', '16'],
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# [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015])
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#}
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RefData = [('twobitCModel6', 'twobitCModel', 64, 9.65280765420711), ('twobitCModel8', 'twobitCModel', 256, 8.75120245829945), ('twobitCModel10', 'twobitCModel', 1024, 8.1318382397263),
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('twobitCModel12', 'twobitCModel', 4096, 7.53026646633342), ('twobitCModel14', 'twobitCModel', 16384, 6.07679338544009), ('twobitCModel16', 'twobitCModel', 65536, 6.07679338544009),
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('gshareCModel6', 'gshareCModel', 64, 10.6602835418646), ('gshareCModel8', 'gshareCModel', 256, 8.38384710559667), ('gshareCModel10', 'gshareCModel', 1024, 6.36847432155534),
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('gshareCModel12', 'gshareCModel', 4096, 3.91108491151983), ('gshareCModel14', 'gshareCModel', 16384, 2.83926519215395), ('gshareCModel16', 'gshareCModel', 65536, .60213659066941)]
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|
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RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
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('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
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('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
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('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
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|
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|
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def ComputeCPI(benchmark):
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'Computes and inserts CPI into benchmark stats.'
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(nameString, opt, dataDict) = benchmark
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CPI = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
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dataDict['CPI'] = CPI
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|
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def ComputeBranchDirMissRate(benchmark):
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'Computes and inserts branch direction miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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branchDirMissRate = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
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dataDict['BDMR'] = branchDirMissRate
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|
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def ComputeBranchTargetMissRate(benchmark):
|
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'Computes and inserts branch target miss prediction rate.'
|
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# *** this is wrong in the verilog test bench
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(nameString, opt, dataDict) = benchmark
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branchTargetMissRate = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
|
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dataDict['BTMR'] = branchTargetMissRate
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|
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def ComputeRASMissRate(benchmark):
|
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'Computes and inserts return address stack miss prediction rate.'
|
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(nameString, opt, dataDict) = benchmark
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RASMPR = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
|
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dataDict['RASMPR'] = RASMPR
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|
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def ComputeInstrClassMissRate(benchmark):
|
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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ClassMPR = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
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dataDict['ClassMPR'] = ClassMPR
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def ParseBranchListFile(path):
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'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
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is formated in row columns. Each row is a trace with the file, branch predictor type, and the parameters.
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parameters can be any number and depend on the predictor type. Returns a list of lists.'''
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lst = []
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BranchList = open(path, 'r')
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for line in BranchList:
|
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tokens = line.split()
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predictorLog = os.path.dirname(path) + '/' + tokens[0]
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predictorType = tokens[1]
|
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predictorParams = tokens[2::]
|
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lst.append([predictorLog, predictorType, predictorParams])
|
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#print(predictorLog, predictorType, predictorParams)
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return lst
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def ComputeICacheMissRate(benchmark):
|
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'Computes and inserts instruction class miss prediction rate.'
|
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(nameString, opt, dataDict) = benchmark
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ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
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dataDict['ICacheMR'] = ICacheMR
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def ComputeICacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['I Cache Miss'])
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if(cycles == 0): ICacheMR = 0
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else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
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dataDict['ICacheMT'] = ICacheMR
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|
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def ComputeDCacheMissRate(benchmark):
|
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
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dataDict['DCacheMR'] = DCacheMR
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def ComputeDCacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['D Cache Miss'])
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if(cycles == 0): DCacheMR = 0
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else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
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dataDict['DCacheMT'] = DCacheMR
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def ComputeAll(benchmarks):
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for benchmark in benchmarks:
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ComputeCPI(benchmark)
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ComputeBranchDirMissRate(benchmark)
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ComputeBranchTargetMissRate(benchmark)
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ComputeRASMissRate(benchmark)
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ComputeInstrClassMissRate(benchmark)
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ComputeICacheMissRate(benchmark)
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ComputeICacheMissTime(benchmark)
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ComputeDCacheMissRate(benchmark)
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ComputeDCacheMissTime(benchmark)
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def printStats(benchmark):
|
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(nameString, opt, dataDict) = benchmark
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print('Test', nameString)
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print('Compile configuration', opt)
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print('CPI \t\t\t %1.2f' % dataDict['CPI'])
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print('Branch Dir Pred Miss Rate %2.2f' % dataDict['BDMR'])
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print('Branch Target Pred Miss Rate %2.2f' % dataDict['BTMR'])
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print('RAS Miss Rate \t\t %1.2f' % dataDict['RASMPR'])
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print('Instr Class Miss Rate %1.2f' % dataDict['ClassMPR'])
|
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print('I Cache Miss Rate %1.4f' % dataDict['ICacheMR'])
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print('I Cache Miss Ave Cycles %1.4f' % dataDict['ICacheMT'])
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print('D Cache Miss Rate %1.4f' % dataDict['DCacheMR'])
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print('D Cache Miss Ave Cycles %1.4f' % dataDict['DCacheMT'])
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print()
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|
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def ProcessFile(fileName):
|
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'''Extract preformance counters from a modelsim log. Outputs a list of tuples for each test/benchmark.
|
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The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
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|
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@ -145,43 +69,37 @@ def ProcessFile(fileName):
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HPMClist = { }
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elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
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countToken = line.split('=')[1].split()
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value = int(countToken[0])
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value = int(countToken[0]) if countToken[0] != 'x' else 0
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name = ' '.join(countToken[1:])
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HPMClist[name] = value
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elif ('is done' in line):
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benchmarks.append((testName, opt, HPMClist))
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return benchmarks
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def ComputeArithmeticAverage(benchmarks):
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average = {}
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index = 0
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for (testName, opt, HPMClist) in benchmarks:
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for field in HPMClist:
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value = HPMClist[field]
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if field not in average:
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average[field] = value
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else:
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average[field] += value
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index += 1
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benchmarks.append(('All', '', average))
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def FormatToPlot(currBenchmark):
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names = []
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values = []
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for config in currBenchmark:
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#print ('config' , config)
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names.append(config[0])
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values.append(config[1])
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return (names, values)
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def ComputeStats(benchmarks):
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for benchmark in benchmarks:
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(nameString, opt, dataDict) = benchmark
|
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dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
|
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dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
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dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
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dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
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dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
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dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
|
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|
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cycles = int(dataDict['I Cache Miss'])
|
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if(cycles == 0): ICacheMR = 0
|
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else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
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dataDict['ICacheMT'] = ICacheMR
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|
||||
dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
|
||||
|
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(nameString, opt, dataDict) = benchmark
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cycles = int(dataDict['D Cache Miss'])
|
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if(cycles == 0): DCacheMR = 0
|
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else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
|
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dataDict['DCacheMT'] = DCacheMR
|
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|
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def GeometricAverage(benchmarks, field):
|
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Product = 1
|
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index = 0
|
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for (testName, opt, HPMCList) in benchmarks:
|
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#print(HPMCList)
|
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Product *= HPMCList[field]
|
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index += 1
|
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return Product ** (1.0/index)
|
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|
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def ComputeGeometricAverage(benchmarks):
|
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fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
|
||||
|
|
@ -191,129 +109,362 @@ def ComputeGeometricAverage(benchmarks):
|
|||
index = 0
|
||||
for (testName, opt, HPMCList) in benchmarks:
|
||||
#print(HPMCList)
|
||||
Product *= HPMCList[field]
|
||||
value = HPMCList[field]
|
||||
if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
|
||||
index += 1
|
||||
AllAve[field] = Product ** (1.0/index)
|
||||
benchmarks.append(('All', '', AllAve))
|
||||
benchmarks.append(('Mean', '', AllAve))
|
||||
|
||||
if(sys.argv[1] == '-b'):
|
||||
configList = []
|
||||
summery = 0
|
||||
if(sys.argv[2] == '-s'):
|
||||
summery = 1
|
||||
sys.argv = sys.argv[1::]
|
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for config in sys.argv[2::]:
|
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benchmarks = ProcessFile(config)
|
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#ComputeArithmeticAverage(benchmarks)
|
||||
ComputeAll(benchmarks)
|
||||
ComputeGeometricAverage(benchmarks)
|
||||
#print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR')))
|
||||
configList.append((config.split('.')[0], benchmarks))
|
||||
def GenerateName(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
|
||||
return predictorType + predictorParams[0]
|
||||
elif(predictorParams == 'local'):
|
||||
return predictorType + predictorParams[0] + '_' + predictorParams[1]
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
# Merge all configruations into a single list
|
||||
benchmarkAll = []
|
||||
for (config, benchmarks) in configList:
|
||||
#print(config)
|
||||
def ComputePredNumEntries(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
|
||||
return 2**int(predictorParams[0])
|
||||
elif(predictorType == 'ras'):
|
||||
return int(predictorParams[0])
|
||||
elif(predictorParams == 'local'):
|
||||
return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
def BuildDataBase(predictorLogs):
|
||||
# Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
|
||||
# raw performance counter data and the processed data on a per benchmark basis. It also includes the geometric mean.
|
||||
# list
|
||||
# branch predictor configuration 0 (tuple)
|
||||
# benchmark name
|
||||
# compiler optimization
|
||||
# data (dictionary)
|
||||
# dictionary of performance counters
|
||||
# branch predictor configuration 1 (tuple)
|
||||
# benchmark name (dictionary)
|
||||
# compiler optimization
|
||||
# data
|
||||
# dictionary of performance counters
|
||||
# ...
|
||||
performanceCounterList = []
|
||||
for trace in predictorLogs:
|
||||
predictorLog = trace[0]
|
||||
predictorType = trace[1]
|
||||
predictorParams = trace[2]
|
||||
# Extract the performance counter data
|
||||
performanceCounters = ProcessFile(predictorLog)
|
||||
ComputeStats(performanceCounters)
|
||||
ComputeGeometricAverage(performanceCounters)
|
||||
#print(performanceCounters)
|
||||
performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
|
||||
return performanceCounterList
|
||||
|
||||
def ReorderDataBase(performanceCounterList):
|
||||
# Reorder the data so the benchmark name comes first, then the branch predictor configuration
|
||||
benchmarkFirstList = []
|
||||
for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
|
||||
for benchmark in benchmarks:
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
#print("BENCHMARK")
|
||||
#print(nameString)
|
||||
#print(opt)
|
||||
#print(dataDict)
|
||||
benchmarkAll.append((nameString, opt, config, dataDict))
|
||||
#print('ALL!!!!!!!!!!')
|
||||
#for bench in benchmarkAll:
|
||||
# print('BENCHMARK')
|
||||
# print(bench)
|
||||
#print('ALL!!!!!!!!!!')
|
||||
benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
|
||||
return benchmarkFirstList
|
||||
|
||||
def ExtractSelectedData(benchmarkFirstList):
|
||||
# now extract all branch prediction direction miss rates for each
|
||||
# namestring + opt, config
|
||||
benchmarkDict = { }
|
||||
for benchmark in benchmarkAll:
|
||||
(name, opt, config, dataDict) = benchmark
|
||||
if name+'_'+opt in benchmarkDict:
|
||||
benchmarkDict[name+'_'+opt].append((config, dataDict['BDMR']))
|
||||
for benchmark in benchmarkFirstList:
|
||||
(name, opt, config, prefixName, entries, dataDict) = benchmark
|
||||
if opt == 'bd_speedopt_speed': NewName = name+'Sp'
|
||||
elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
|
||||
else: NewName = name
|
||||
#print(NewName)
|
||||
#NewName = name+'_'+opt
|
||||
if NewName in benchmarkDict:
|
||||
benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
|
||||
else:
|
||||
benchmarkDict[name+'_'+opt] = [(config, dataDict['BDMR'])]
|
||||
benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
|
||||
return benchmarkDict
|
||||
|
||||
size = len(benchmarkDict)
|
||||
index = 1
|
||||
if(summery == 0):
|
||||
#print('Number of plots', size)
|
||||
def ReportAsTable(benchmarkDict):
|
||||
refLine = benchmarkDict['Mean']
|
||||
FirstLine = []
|
||||
SecondLine = []
|
||||
for (name, typ, size, val) in refLine:
|
||||
FirstLine.append(name)
|
||||
SecondLine.append(size)
|
||||
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
(names, values) = FormatToPlot(currBenchmark)
|
||||
print(names, values)
|
||||
plt.subplot(6, 7, index)
|
||||
plt.bar(names, values)
|
||||
plt.title(benchmarkName)
|
||||
plt.ylabel('BR Dir Miss Rate (%)')
|
||||
#plt.xlabel('Predictor')
|
||||
index += 1
|
||||
else:
|
||||
combined = benchmarkDict['All_']
|
||||
# merge the reference data into rtl data
|
||||
combined.extend(RefData)
|
||||
(name, value) = FormatToPlot(combined)
|
||||
lst = []
|
||||
dct = {}
|
||||
category = []
|
||||
length = []
|
||||
accuracy = []
|
||||
for index in range(0, len(name)):
|
||||
match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I)
|
||||
percent = 100 -value[index]
|
||||
if match:
|
||||
(PredType, size) = match.groups()
|
||||
category.append(PredType)
|
||||
length.append(size)
|
||||
accuracy.append(percent)
|
||||
if(PredType not in dct):
|
||||
dct[PredType] = ([size], [percent])
|
||||
else:
|
||||
(currSize, currPercent) = dct[PredType]
|
||||
currSize.append(size)
|
||||
currPercent.append(percent)
|
||||
dct[PredType] = (currSize, currPercent)
|
||||
print(dct)
|
||||
sys.stdout.write('benchmark\t\t')
|
||||
for name in FirstLine:
|
||||
if(len(name) < 8): sys.stdout.write('%s\t\t' % name)
|
||||
else: sys.stdout.write('%s\t' % name)
|
||||
sys.stdout.write('\n')
|
||||
sys.stdout.write('size\t\t\t')
|
||||
for size in SecondLine:
|
||||
if(len(str(size)) < 8): sys.stdout.write('%d\t\t' % size)
|
||||
else: sys.stdout.write('%d\t' % size)
|
||||
sys.stdout.write('\n')
|
||||
|
||||
if(args.summary):
|
||||
sys.stdout.write('Mean\t\t\t')
|
||||
for (name, typ, size, val) in refLine:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
if(not args.summary):
|
||||
for benchmark in benchmarkDict:
|
||||
length = len(benchmark)
|
||||
if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
|
||||
elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
|
||||
else: sys.stdout.write('%s\t' % benchmark)
|
||||
for (name, typ, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
def ReportAsText(benchmarkDict):
|
||||
if(args.summary):
|
||||
mean = benchmarkDict['Mean']
|
||||
print('Mean')
|
||||
for (name, typ, size, val) in mean:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
|
||||
if(not args.summary):
|
||||
for benchmark in benchmarkDict:
|
||||
print(benchmark)
|
||||
for (name, type, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
|
||||
def Inversion(lst):
|
||||
return [x if not args.invert else 100 - x for x in lst]
|
||||
|
||||
def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName):
|
||||
index = 0
|
||||
NumberInGroup = len(seriesDict)
|
||||
# Figure out width of bars. NumberInGroup bars + want 2 bar space
|
||||
# the space between groups is 1
|
||||
EffectiveNumInGroup = NumberInGroup + 2
|
||||
barWidth = 1 / EffectiveNumInGroup
|
||||
fig = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
|
||||
colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
|
||||
for name in seriesDict:
|
||||
xpos = np.arange(BenchPerRow)
|
||||
xpos = [x + index*barWidth for x in xpos]
|
||||
values = seriesDict[name]
|
||||
plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
|
||||
index += 1
|
||||
plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
|
||||
plt.xlabel('Benchmark')
|
||||
if(not args.invert): plt.ylabel('Misprediction Rate (%)')
|
||||
else: plt.ylabel('Prediction Accuracy (%)')
|
||||
plt.legend(loc='upper left', ncol=2)
|
||||
plt.savefig(FileName)
|
||||
|
||||
def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
|
||||
seriesDictTrunk = {}
|
||||
for benchmarkName in seriesDictBig:
|
||||
lst = seriesDictBig[benchmarkName]
|
||||
seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
|
||||
xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
|
||||
return(xlabelListTrunk, seriesDictTrunk)
|
||||
|
||||
|
||||
def ReportAsGraph(benchmarkDict, bar):
|
||||
def FormatToPlot(currBenchmark):
|
||||
names = []
|
||||
sizes = []
|
||||
values = []
|
||||
typs = []
|
||||
for config in currBenchmark:
|
||||
names.append(config[0])
|
||||
sizes.append(config[1])
|
||||
values.append(config[2])
|
||||
typs.append(config[3])
|
||||
return (names, sizes, values, typs)
|
||||
titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
|
||||
'BTMR' : 'Branch Target Accuracy',
|
||||
'RASMPR': 'RAS Accuracy',
|
||||
'ClassMPR': 'Class Prediction Accuracy'}
|
||||
titles = {'BDMR' : 'Branch Direction Misprediction',
|
||||
'BTMR' : 'Branch Target Misprediction',
|
||||
'RASMPR': 'RAS Misprediction',
|
||||
'ClassMPR': 'Class Misprediction'}
|
||||
if(args.summary):
|
||||
markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
|
||||
colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
|
||||
temp = benchmarkDict['Mean']
|
||||
|
||||
# the benchmarkDict['Mean'] contains sequencies of results for multiple
|
||||
# branch predictors with various parameterizations
|
||||
# group the parameterizations by the common typ.
|
||||
sequencies = {}
|
||||
for (name, typ, size, value) in benchmarkDict['Mean']:
|
||||
if not typ in sequencies:
|
||||
sequencies[typ] = [(size, value)]
|
||||
else:
|
||||
sequencies[typ].append((size,value))
|
||||
# then graph the common typ as a single line+scatter plot
|
||||
# finally repeat for all typs of branch predictors and overlay
|
||||
fig, axes = plt.subplots()
|
||||
marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
|
||||
colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
|
||||
for cat in dct:
|
||||
(x, y) = dct[cat]
|
||||
x=[int(2**int(v)) for v in x]
|
||||
#print(x, y)
|
||||
print(cat)
|
||||
axes.plot(x,y, color=colors[cat])
|
||||
axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
|
||||
#plt.scatter(x, y, label=cat)
|
||||
#plt.plot(x, y)
|
||||
#axes.set_xticks([4, 6, 8, 10, 12, 14])
|
||||
index = 0
|
||||
if(args.invert): plt.title(titlesInvert[ReportPredictorType])
|
||||
else: plt.title(titles[ReportPredictorType])
|
||||
for branchPredName in sequencies:
|
||||
data = sequencies[branchPredName]
|
||||
(xdata, ydata) = zip(*data)
|
||||
if args.invert: ydata = [100 - x for x in ydata]
|
||||
axes.plot(xdata, ydata, color=colors[index])
|
||||
axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
|
||||
index = (index + 1) % len(markers)
|
||||
axes.legend(loc='upper left')
|
||||
axes.set_xscale("log")
|
||||
axes.set_ylabel('Prediction Accuracy')
|
||||
axes.set_xlabel('Entries')
|
||||
axes.set_xticks([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.set_xticklabels([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.set_xticks(xdata)
|
||||
axes.set_xticklabels(xdata)
|
||||
axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
|
||||
plt.show()
|
||||
|
||||
|
||||
else:
|
||||
# steps 1 and 2
|
||||
benchmarks = ProcessFile(sys.argv[1])
|
||||
print(benchmarks[0])
|
||||
ComputeAll(benchmarks)
|
||||
ComputeGeometricAverage(benchmarks)
|
||||
# 3 process into useful data
|
||||
# cache hit rates
|
||||
# cache fill time
|
||||
# branch predictor status
|
||||
# hazard counts
|
||||
# CPI
|
||||
# instruction distribution
|
||||
for benchmark in benchmarks:
|
||||
printStats(benchmark)
|
||||
plt.show()
|
||||
|
||||
|
||||
# if(not args.summary):
|
||||
# size = len(benchmarkDict)
|
||||
# sizeSqrt = math.sqrt(size)
|
||||
# isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
|
||||
# numCol = math.floor(sizeSqrt)
|
||||
# numRow = numCol + (0 if isSquare else 1)
|
||||
# index = 1
|
||||
# fig = plt.figure()
|
||||
# for benchmarkName in benchmarkDict:
|
||||
# currBenchmark = benchmarkDict[benchmarkName]
|
||||
# (names, typs, sizes, values) = FormatToPlot(currBenchmark)
|
||||
# #axes.plot(numRow, numCol, index)
|
||||
# ax = fig.add_subplot(numRow, numCol, index)
|
||||
# ax.bar(names, values)
|
||||
# ax.title.set_text(benchmarkName)
|
||||
# #plt.ylabel('BR Dir Miss Rate (%)')
|
||||
# #plt.xlabel('Predictor')
|
||||
# index += 1
|
||||
|
||||
if(not args.summary):
|
||||
size = len(benchmarkDict)
|
||||
sizeSqrt = math.sqrt(size)
|
||||
isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
|
||||
numCol = math.floor(sizeSqrt)
|
||||
numRow = numCol + (0 if isSquare else 1)
|
||||
index = 1
|
||||
BenchPerRow = 7
|
||||
|
||||
xlabelList = []
|
||||
seriesDict = {}
|
||||
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelList.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
if(name not in seriesDict):
|
||||
seriesDict[name] = [value]
|
||||
else:
|
||||
seriesDict[name].append(value)
|
||||
if(index >= BenchPerRow): break
|
||||
index += 1
|
||||
|
||||
xlabelListBig = []
|
||||
seriesDictBig = {}
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelListBig.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
if(name not in seriesDictBig):
|
||||
seriesDictBig[name] = [value]
|
||||
else:
|
||||
seriesDictBig[name].append(value)
|
||||
|
||||
#The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
|
||||
# on each piece.
|
||||
for row in range(0, math.ceil(39 / BenchPerRow)):
|
||||
(xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
|
||||
FileName = 'barSegment%d.png' % row
|
||||
groupLen = len(xlabelListTrunk)
|
||||
BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName)
|
||||
|
||||
|
||||
# main
|
||||
parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
|
||||
|
||||
# parse program arguments
|
||||
metric = parser.add_mutually_exclusive_group()
|
||||
metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
|
||||
metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
|
||||
metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
|
||||
metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
|
||||
|
||||
parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
|
||||
parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
|
||||
parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s. If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
|
||||
parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
|
||||
|
||||
displayMode = parser.add_mutually_exclusive_group()
|
||||
displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
parser.add_argument('sources', nargs=1)
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
# Figure what we are reporting
|
||||
ReportPredictorType = 'BDMR' # default
|
||||
if(args.ras): ReportPredictorType = 'RASMPR'
|
||||
if(args.target): ReportPredictorType = 'BTMR'
|
||||
if(args.iclass): ReportPredictorType = 'ClassMPR'
|
||||
|
||||
# Figure how we are displaying the data
|
||||
ReportMode = 'gui' # default
|
||||
if(args.text): ReportMode = 'text'
|
||||
if(args.table): ReportMode = 'table'
|
||||
if(args.debug): ReportMode = 'debug'
|
||||
|
||||
# read the questa sim list file.
|
||||
# row, col format. each row is a questa sim run with performance counters and a particular
|
||||
# branch predictor type and size. size can be multiple parameters for more complex predictors like
|
||||
# local history and tage.
|
||||
# <file> <type> <size>
|
||||
predictorLogs = ParseBranchListFile(args.sources[0]) # digests the traces
|
||||
performanceCounterList = BuildDataBase(predictorLogs) # builds a database of performance counters by trace and then by benchmark
|
||||
benchmarkFirstList = ReorderDataBase(performanceCounterList) # reorder first by benchmark then trace
|
||||
benchmarkDict = ExtractSelectedData(benchmarkFirstList) # filters to just the desired performance counter metric
|
||||
|
||||
if(args.reference): benchmarkDict['Mean'].extend(RefData)
|
||||
#print(benchmarkDict['Mean'])
|
||||
#print(benchmarkDict['aha-mont64Speed'])
|
||||
#print(benchmarkDict)
|
||||
|
||||
# table format
|
||||
if(ReportMode == 'table'):
|
||||
ReportAsTable(benchmarkDict)
|
||||
|
||||
if(ReportMode == 'text'):
|
||||
ReportAsText(benchmarkDict)
|
||||
|
||||
if(ReportMode == 'gui'):
|
||||
ReportAsGraph(benchmarkDict, args.bar)
|
||||
|
||||
# *** this is only needed of -b (no -s)
|
||||
|
||||
# debug
|
||||
#config0 = performanceCounterList[0][0]
|
||||
#data0 = performanceCounterList[0][1]
|
||||
#bench0 = data0[0]
|
||||
#bench0name = bench0[0]
|
||||
#bench0data = bench0[2]
|
||||
#bench0BrCount = bench0data['Br Count']
|
||||
#bench1 = data0[1]
|
||||
|
||||
#print(data0)
|
||||
#print(bench0)
|
||||
#print(bench1)
|
||||
|
||||
#print(bench0name)
|
||||
#print(bench0BrCount)
|
||||
|
|
|
|||
|
|
@ -120,8 +120,8 @@ sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl
|
|||
sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
|
||||
cd $RISCV
|
||||
git clone https://github.com/verilator/verilator # Only first time
|
||||
unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
|
||||
unset VERILATOR_ROOT # For bash
|
||||
# unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
|
||||
unset VERILATOR_ROOT # For bash
|
||||
cd verilator
|
||||
git pull # Make sure git repository is up-to-date
|
||||
git checkout master # Use development branch (e.g. recent bug fixes)
|
||||
|
|
@ -157,6 +157,8 @@ opam install sail -y
|
|||
eval $(opam config env)
|
||||
git clone https://github.com/riscv/sail-riscv.git
|
||||
cd sail-riscv
|
||||
# For now, use checkout that is stable for Wally
|
||||
git checkout 72b2516d10d472ac77482fd959a9401ce3487f60
|
||||
make -j ${NUM_THREADS}
|
||||
ARCH=RV32 make -j ${NUM_THREADS}
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
|
||||
|
|
|
|||
|
|
@ -142,6 +142,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
|
|
@ -157,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 1;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -156,6 +156,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd12;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -170,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
|
|||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 1;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -158,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -141,10 +141,22 @@ localparam PLIC_UART_ID = 32'd10;
|
|||
localparam PLIC_SDC_ID = 32'd9;
|
||||
|
||||
localparam BPRED_SUPPORTED = 1;
|
||||
// this is an annoying hack for the branch predictor parameterization override.
|
||||
`ifdef BPRED_OVERRIDE
|
||||
localparam BPRED_TYPE = `BPRED_TYPE;
|
||||
localparam BPRED_SIZE = `BPRED_SIZE;
|
||||
`else
|
||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_SIZE = 32'd16;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
`endif
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
`ifdef BTB_OVERRIDE
|
||||
localparam BTB_SIZE = `BTB_SIZE;
|
||||
localparam RAS_SIZE = `RAS_SIZE;
|
||||
`else
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
`endif
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -159,6 +171,12 @@ localparam ZBB_SUPPORTED = 1;
|
|||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 1;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -144,6 +144,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -158,6 +159,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -143,6 +143,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -157,6 +158,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -160,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -147,8 +147,9 @@ localparam PLIC_SDC_ID = 32'd9;
|
|||
localparam BPRED_SUPPORTED = 1;
|
||||
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_SIZE = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 1;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -163,6 +164,12 @@ localparam ZBB_SUPPORTED = 1;
|
|||
localparam ZBC_SUPPORTED = 1;
|
||||
localparam ZBS_SUPPORTED = 1;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 1;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -146,6 +146,7 @@ localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
|
|||
localparam BPRED_SIZE = 32'd10;
|
||||
localparam BPRED_NUM_LHR = 32'd6;
|
||||
localparam BTB_SIZE = 32'd10;
|
||||
localparam RAS_SIZE = 32'd16;
|
||||
|
||||
localparam SVADU_SUPPORTED = 0;
|
||||
localparam ZMMUL_SUPPORTED = 0;
|
||||
|
|
@ -160,6 +161,12 @@ localparam ZBB_SUPPORTED = 0;
|
|||
localparam ZBC_SUPPORTED = 0;
|
||||
localparam ZBS_SUPPORTED = 0;
|
||||
|
||||
// New compressed instructions
|
||||
localparam ZCB_SUPPORTED = 0;
|
||||
localparam ZCA_SUPPORTED = 0;
|
||||
localparam ZCF_SUPPORTED = 0;
|
||||
localparam ZCD_SUPPORTED = 0;
|
||||
|
||||
// Memory synthesis configuration
|
||||
localparam USE_SRAM = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -89,12 +89,17 @@ localparam cvw_t P = '{
|
|||
BPRED_SIZE : BPRED_SIZE,
|
||||
BPRED_NUM_LHR : BPRED_NUM_LHR,
|
||||
BTB_SIZE : BTB_SIZE,
|
||||
RAS_SIZE : RAS_SIZE,
|
||||
RADIX : RADIX,
|
||||
DIVCOPIES : DIVCOPIES,
|
||||
ZBA_SUPPORTED : ZBA_SUPPORTED,
|
||||
ZBB_SUPPORTED : ZBB_SUPPORTED,
|
||||
ZBC_SUPPORTED : ZBC_SUPPORTED,
|
||||
ZBS_SUPPORTED : ZBS_SUPPORTED,
|
||||
ZCA_SUPPORTED : ZCA_SUPPORTED,
|
||||
ZCB_SUPPORTED : ZCB_SUPPORTED,
|
||||
ZCD_SUPPORTED : ZCD_SUPPORTED,
|
||||
ZCF_SUPPORTED : ZCF_SUPPORTED,
|
||||
USE_SRAM : USE_SRAM,
|
||||
M_MODE : M_MODE,
|
||||
S_MODE : S_MODE,
|
||||
|
|
|
|||
123
docs/divsqrt_tex/div2.tex
Normal file
123
docs/divsqrt_tex/div2.tex
Normal file
|
|
@ -0,0 +1,123 @@
|
|||
\documentclass[12pt]{article}
|
||||
|
||||
\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
|
||||
|
||||
\usepackage{arydshln}
|
||||
|
||||
\parindent = 0in
|
||||
|
||||
\pagestyle{empty}
|
||||
|
||||
%==========
|
||||
%==========
|
||||
|
||||
\begin{document}
|
||||
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Initialization&$D$&$0001.1010\ 000$&\\
|
||||
&$-D=\overline{D}+1$&$1110.0101\ 111$&(+ 1 ulp)\\
|
||||
&&&\\
|
||||
&$WS_{-1}=X$&$0001.0000\ 010$&\\
|
||||
&$WC_{-1}$&$0000.0000\ 000$&\\
|
||||
\hdashline\\
|
||||
Step 0:&$WS_{-1}$&$0001.0000\ 010$&\\
|
||||
&$WC_{-1}$&$0000.0000\ 00\mathbf{1}$&($W_{msbs}=0001\ \text{so}\ q_0=1$)\\
|
||||
&$-q_0D$&$1110.0101\ 111$&\\
|
||||
\cline{2-3}
|
||||
&$sum$&$1111.0101\ 100$&$\ll1$\\
|
||||
&$carry$&$0000.0000\ 110$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 1:&$WS_0$&$1110.1011\ 000$&\\
|
||||
&$WC_0$&$0000.0001\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_1=-1$)\\
|
||||
&$-q_1D$&$0001.1010\ 000$&\\
|
||||
\cline{2-3}
|
||||
&$sum$&$1111.0000\ 100$&$\ll1$\\
|
||||
&$carry$&$0001.0110\ 000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 2:&$WS_1$&$1110.0001\ 000$&\\
|
||||
&$WC_1$&$0010.1100\ 00\mathbf{1}$&($W_{msbs}=0000\ \text{so}\ q_2=1$)\\
|
||||
&$-q_2D$&$1110.0101\ 111$&\\
|
||||
\cline{2-3}
|
||||
&$sum$&$0010.1000\ 110$&$\ll1$\\
|
||||
&$carry$&$1100.1010\ 010$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 3:&$WS_2$&$0101.0001\ 100$&\\
|
||||
&$WC_2$&$1001.0100\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_3=-1$)\\
|
||||
&$-q_3D$&$0001.1010\ 000$&\\
|
||||
\cline{2-3}
|
||||
&$sum$&$1101.1111\ 000$&\\
|
||||
&$carry$&$0010.0001\ 000$&$sum+carry=0$, terminate.\\
|
||||
\hdashline\\
|
||||
Terminate&Quotient&0.101
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
X = 1.0110\ 011 (179/128)
|
||||
|
||||
D = 1.0011\ 000 (152/128)
|
||||
|
||||
Q = 1.0010\ 1101\ 0
|
||||
|
||||
D[1.3] = 1.001, so we use the ``"1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Initialization&$D$&$0001.0011\ 000$&\\
|
||||
&$2D$&$0010.0110\ 000$&\\
|
||||
&$-D=\overline{D}+1$&$1110.1100\ 111$&(+ 1 ulp)\\
|
||||
&$-2D=\overline{2D}+1$&$1101.1001\ 111$&(+ 1 ulp)\\
|
||||
&&&\\
|
||||
&$X=WS$&$0001.0110\ 011$&\\
|
||||
&$WC$&$0000.0000\ 000$&\\
|
||||
\hdashline\\
|
||||
Step 4:&$WS$&$0001.0110\ 011$&\\
|
||||
&$WC$&$0000.0000\ 00\mathbf{1}$&($RW_{msbs}=0001.010\ \text{so}\ q_4=1$)\\
|
||||
&$-q_7D$&$1110.1100\ 111$&\\
|
||||
\cline{2-3}
|
||||
&$WS$&$1111.1010\ 101$&$\ll2$\\
|
||||
&$WC$&$0000.1000\ 110$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 3:&$WS$&$1110.1010\ 100$&\\
|
||||
&$WC$&$0010.0011\ 000$&($RW_{msbs}=0000.110\ \text{so}\ q_3=1$)\\
|
||||
&$-q_6D$&$0000.0000\ 000$&\\
|
||||
\cline{2-3}
|
||||
&$WS$&$1100.1001\ 100$&$\ll2$\\
|
||||
&$WC$&$0100.0100\ 000$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 2:&$WS$&$0010.0110\ 000$&\\
|
||||
&$WC$&$0001.0000\ 00\mathbf{1}$&($RW_{msbs}=0011.010\ \text{so}\ q_2=-1$)\\
|
||||
&$-q_5D$&$1110.0101\ 111$&\\
|
||||
\cline{2-3}
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
|
||||
page 269 306
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
\large{\bf{
|
||||
Math for the recurrence relation}}
|
||||
|
||||
**going to have to change notation for sure, change the subscripts for steps and might have to get rid of some exponents**
|
||||
\begin{align*}
|
||||
w[j+1] &= r^{j+1}\big(x-S[j+1]^2\big)\\
|
||||
&= r^{j+1}\big(x-(S[j]+s_{j+1}r^{-(j+1)})^2\big)\\
|
||||
&= r^{j+1}x-r^{j+1}\big(S[j]^2+2S[j]s_{j+1}r^{-(j+1)}+s^2_{j+1}r^{-2(j+1)}\big)\\
|
||||
&= r^{j+1}\big(x-S[j]^2\big)-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
|
||||
&= rw[j]-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
|
||||
&= rw[j]+F[j]
|
||||
\end{align*}
|
||||
where
|
||||
\begin{align*}
|
||||
F[j]=-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)
|
||||
\end{align*}
|
||||
|
||||
Since there is a term of $S$ in the expression of $F$, we must come up with a way to represent $S$ using only zeros and ones, rather than using the bit set $\{-a,\ldots,a\}$. This is done using on-the-fly conversion just as we did to compute the quotient for the divider. We keep a running copy of $S$, but we also keep the value $SM=S-1$. The logic is still the same for computing $S$ and $SM$ on the next step; see figure 13.15.
|
||||
|
||||
Now that $S$ is in a form such that we can use it in a CSA, we need to compute $F$. To do so,
|
||||
|
||||
\end{document}
|
||||
84
docs/divsqrt_tex/div4.tex
Normal file
84
docs/divsqrt_tex/div4.tex
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
\documentclass[12pt]{article}
|
||||
|
||||
\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
|
||||
|
||||
\usepackage{arydshln}
|
||||
|
||||
\parskip = .2in
|
||||
\parindent = 0in
|
||||
|
||||
\pagestyle{empty}
|
||||
|
||||
%==========
|
||||
%==========
|
||||
|
||||
\begin{document}
|
||||
|
||||
|
||||
X = 1.0000\ 1101 (269/256)
|
||||
|
||||
D = 1.0011\ 0110 (310/256)
|
||||
|
||||
Q = 0.1101\ 1110 (222/256)
|
||||
|
||||
D[1.3] = 1.001, so we use the ``1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Initialization&$D$&$0001.0011\ 0110\ 00$&\\
|
||||
&$2D$&$0010.0110\ 1100\ 00$&\\
|
||||
&$-D=\overline{D}+1$&$1110.1100\ 1001\ 11$&(+ 1 ulp)\\
|
||||
&$-2D=\overline{2D}+1$&$1101.1001\ 0011\ 11$&(+ 1 ulp)\\
|
||||
&&&\\
|
||||
&$WS_{-1}=X$&$0001.0000\ 1101\ 00$&\\
|
||||
&$WC_{-1}$&$0000.0000\ 0000\ 00$&\\
|
||||
\hdashline\\
|
||||
Step 0: &$WS_{-1} $&$0001.0000\ 1101\ 00$&\\
|
||||
&$WC_{-1} $&$0000.0000\ 0000\ 0\mathbf{1}$&($W_{msbs}=0001.000\ \text{so}\ q_0=1$)\\
|
||||
&$-q_0D $&$1110.1100\ 1001\ 11$&\\
|
||||
\cline{2-3}
|
||||
&$sum $&$1111.1100\ 0100\ 10$&$\ll2$\\
|
||||
&$carry $&$0000.0001\ 0010\ 10$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS_0 $&$1111.0001\ 0010\ 00$&\\
|
||||
&$WC_0 $&$0000.0100\ 1010\ 0\mathbf{0}$&($W_{msbs}=1111.010\ \text{so}\ q_1=-1$)\\
|
||||
&$-q_1D $&$0001.0011\ 0110\ 00$&\\
|
||||
\cline{2-3}
|
||||
&$sum $&$1110.0110\ 1110\ 00$&$\ll2$\\
|
||||
&$carry $&$0010.0010\ 0100\ 00$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS_1 $&$1001.1011\ 1000\ 00$&\\
|
||||
&$WC_1 $&$1000.1001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.010\ \text{so}\ q_2=2$)\\
|
||||
&$-q_2D $&$1101.1001\ 0011\ 11$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$1100.1011\ 1011\ 10$&$\ll2$\\
|
||||
&$carry $&$0011.0010\ 0000\ 10$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS_2 $&$0010.1110\ 1110\ 00$&\\
|
||||
&$WC_2 $&$1100.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=1111.011\ \text{so}\ q_3=-1$)\\
|
||||
&$-q_3D $&$0001.0011\ 0110\ 00$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$1111.0101\ 1010\ 00$&$\ll2$\\
|
||||
&$carry $&$0001.0100\ 0100\ 00$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS_3 $&$1101.0110\ 1000\ 00$&\\
|
||||
&$WC_3 $&$0101.0001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.011\ \text{so}\ q_4=2$)\\
|
||||
&$-q_4D $&$1101.1001\ 0011\ 11$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$0101.1110\ 1011\ 10$&$\ll2$\\
|
||||
&$carry $&$1010.0010\ 0000\ 10$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Step 5: &$WS_4 $&$0111.1010\ 1110\ 00$&\\
|
||||
&$WC_4 $&$1000.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=0000.001\ \text{so}\ q_5=0$)\\
|
||||
&$-q_5D $&$0000.0000\ 0000\ 00$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$1111.0010\ 1100\ 00$&$\ll2$\\
|
||||
&$carry $&$0001.0000\ 0100\ 00$&$\ll2$\\
|
||||
\hdashline\\
|
||||
Terminate&Quotient&$00.11\ 01\ 11\ 10\ (00\ 1)$
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
\end{document}
|
||||
385
docs/divsqrt_tex/sqrt2.tex
Normal file
385
docs/divsqrt_tex/sqrt2.tex
Normal file
|
|
@ -0,0 +1,385 @@
|
|||
\documentclass[12pt]{article}
|
||||
\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
|
||||
\usepackage{arydshln}
|
||||
|
||||
\parskip = .2in
|
||||
\parindent = 0in
|
||||
|
||||
\pagestyle{empty}
|
||||
|
||||
%==========
|
||||
%==========
|
||||
|
||||
\begin{document}
|
||||
|
||||
X = 0.0111 0011 1001 (1849/4096)
|
||||
|
||||
S = 0.1010 1100 0000 (2752/4096)
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{ccccc}
|
||||
&$X $&$ 0000.0111\ 0011\ 1001 $& &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
|
||||
&$WS_0=2(X-1) $&$ 1110.1110\ 0111\ 0010 $& &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &$K_0=0001.0000\ 0000\ 0000\ $\\
|
||||
& & & &$C_0=1111.0000\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS_0 $&$ 1110.1110\ 0111\ 0010 $& &\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &($W_{msbs}=1110\ \text{so}\ s_1=-1$)\\
|
||||
&$F_1=2S_0-K_1 $&${\color{blue}0001.1}000\ 0000\ 0000$& &$S_1={\color{blue}0000.1}000\ 0000\ 0000$\\
|
||||
& & & &$SM_1={\color{blue}0000.0}000\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0110\ 0111\ 0010 $&$\ll1 $&$K_1=0000.1000\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0001.0000\ 0000\ 0000 $&$\ll1 $&$C_1=1111.1000\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS_1 $&$ 1110.1100\ 1110\ 0100 $& &\\
|
||||
&$WC_1 $&$ 0010.0000\ 0000\ 0000 $& &($W_{msbs}=0000\ \text{so}\ s_2=1$)\\
|
||||
&$F_2=-2S_1-K_2$&${\color{blue}1110.11}00\ 0000\ 0000$& &$S_2={\color{blue}0000.11}00\ 0000\ 0000$\\
|
||||
& & & &$SM_2={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0010.0000\ 1110\ 0100 $&$\ll1 $&$K_2=0000.0100\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 1101.1000\ 0000\ 0000 $&$\ll1 $&$C_2=1111.1100\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS_2 $&$ 0100.0001\ 1100\ 1000 $& &\\
|
||||
&$WC_2 $&$ 1011.0000\ 0000\ 0000 $& &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
|
||||
&$F_3=0 $&${\color{blue}0000.000}0\ 0000\ 0000$& &$S_3={\color{blue}0000.110}0\ 0000\ 0000$\\
|
||||
& & & &$SM_3={\color{blue}0000.101}0\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0001\ 1100\ 1000 $&$\ll1 $&$K_3=0000.0010\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0000.0000\ 0000\ 0000 $&$\ll1 $&$C_3=1111.1110\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS_3 $&$ 1110.0011\ 1001\ 0000 $& &\\
|
||||
&$WC_3 $&$ 0000.0000\ 0000\ 0000 $& &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
|
||||
&$F_4=2S_3-K_4 $&${\color{blue}0001.0111}\ 0000\ 0000$& &$S_4={\color{blue}0000.1011}\ 0000\ 0000$\\
|
||||
& & & &$SM_4={\color{blue}0000.1010}\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0100\ 1001\ 0000 $&$\ll1 $&$K_4=0000.0001\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0000.0110\ 0000\ 0000 $&$\ll1 $&$C_4=1111.1111\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 5: &$WS_4 $&$ 1110.1001\ 0010\ 0000 $& &\\
|
||||
&$WC_4 $&$ 0000.1100\ 0000\ 0000 $& &($W_{msbs}=1110\ \text{so}\ s_5=-1$)\\
|
||||
&$F_5=2S_4-K_5 $&${\color{blue}0001.0101\ 1}000\ 0000$& &$S_5={\color{blue}0000.1010\ 1}000\ 0000$\\
|
||||
& & & &$SM_5={\color{blue}0000.1010\ 0}000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0000\ 1010\ 0000 $&$\ll1 $&$K_5=0000.0000\ 1000\ 0000\ $\\
|
||||
&$carry $&$ 0001.1010\ 0000\ 0000 $&$\ll1 $&$C_5=1111.1111\ 1000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 6: &$WS_5 $&$ 1110.0001\ 0100\ 0000 $& &\\
|
||||
&$WC_5 $&$ 0011.0100\ 0000\ 0000 $& &($W_{msbs}=0001\ \text{so}\ s_6=1$)\\
|
||||
&$F_6=-2S_5-K_6$&${\color{blue}1110.1010\ 11}00\ 0000$& &$S_6={\color{blue}0000.1010\ 11}00\ 0000$\\
|
||||
& & & &$SM_6={\color{blue}0000.1010\ 10}00\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0011.1111\ 1000\ 0000 $&$\ll1 $&$K_6=0000.0000\ 0100\ 0000\ $\\
|
||||
&$carry $&$ 1100.0000\ 1000\ 0000 $&$\ll1 $&$C_6=1111.1111\ 1100\ 0000\,$\\
|
||||
& & & &$sum+carry=0$, terminate\\
|
||||
\hdashline\\
|
||||
Terminate&Square Root&0.101011
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
\hdashline\\
|
||||
Step 6: &$WS $&$0111.1111\ 0000\ 00$&\\
|
||||
&$WC $&$1000.0001\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_6=0$)\\
|
||||
&$F $&$0000.0000\ 0000\ 00$&$S_6=\mathbf{1.0101\ 10}00\ 00$\\
|
||||
& & &$SM_6=\mathbf{1.0101\ 01}00\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1110\ 0000\ 00$&$\ll1$\\
|
||||
&$WC $&$0000.0010\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 7: &$WS $&$1111.1100\ 0000\ 00$&\\
|
||||
&$WC $&$0000.0100\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_7=0$)\\
|
||||
&$F $&$0000.0000\ 0000\ 00$&$S_7=\mathbf{1.0101\ 100}0\ 00$\\
|
||||
& & &$SM_7=\mathbf{1.0101\ 011}0\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1000\ 0000\ 00$&$\ll1$\\
|
||||
&$WC $&$0000.1000\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 8: &$WS $&$1111.0000\ 0000\ 00$&\\
|
||||
&$WC $&$0001.0000\ 0000\ 00$&($W_{msbs}=0000\ \text{so}\ s_8=1$)\\
|
||||
&$F $&$1110.1010\ 0111\ 10$&$S_8=\mathbf{1.0101\ 1001}\ 00$\\
|
||||
& & &$SM_8=\mathbf{1.0101\ 1000}\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$0000.1010\ 0111\ 10$&$\ll1$\\
|
||||
&$WC $&$1110.0000\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 9: &$WS $&$0001.0100\ 1111\ 00$&\\
|
||||
&$WC $&$1100.0000\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_9=-1$)\\
|
||||
&$F $&$0001.0101\ 1000\ 11$&$S_9=\mathbf{1.0101\ 1000\ 1}0$\\
|
||||
& & &$SM_9=\mathbf{1.0101\ 1000\ 0}0\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1100.0001\ 0111\ 11$&$\ll1$\\
|
||||
&$WC $&$0010.1001\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 10:&$WS $&$1000.0010\ 1111\ 10$&\\
|
||||
&$WC $&$0101.0010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{10}=-1$)\\
|
||||
&$F $&$0001.0101\ 1000\ 01$&$S_{10}=\mathbf{1.0101\ 1000\ 01}$\\
|
||||
& & &$SM_{10}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1100.0001\ 0111\ 11$&$\ll1$\\
|
||||
&$WC $&$0010.0101\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 11:&$WS $&$1000.0010\ 1111\ 10$&\\
|
||||
&$WC $&$0100.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{11}=-1$)\\
|
||||
&$F $&$0001.0101\ 1000\ 00$&$S_{11}=\mathbf{1.0101\ 1000\ 00}$\\
|
||||
& & &$SM_{11}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1101.1101\ 0111\ 10$&$\ll1$\\
|
||||
&$WC $&$0000.0101\ 0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 12:&$WS $&$1101.1000\ 0111\ 10$&\\
|
||||
&$WC $&$0000.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{12}=-1$)\\
|
||||
&$F $&$0001.0101\ 1000\ 00$&$S_{12}=\mathbf{1.0101\ 1000\ 00}$\\
|
||||
& & &$SM_{12}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1100.0111\ 1111\ 10$&$\ll1$\\
|
||||
&$WC $&$0011.0000\ 0000\ 00$&$\ll1$\\
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Step 13:&$WS $&$1000.1111\ 1111\ 00$&\\
|
||||
&$WC $&$0110.0000\ 0000\ 00$&($W_{msbs}=1110\ \text{so}\ s_{13}=-1$)\\
|
||||
&$F $&$0001.0101\ 1000\ 00$&$S_{13}=\mathbf{1.0101\ 1000\ 00}$\\
|
||||
& & &$SM_{13}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1010\ 0111\ 10$&$\ll1$\\
|
||||
&$WC $&$0000.1011\ 0000\ 00$&$\ll1$\\
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{ccccc}
|
||||
&$X $&$ 0000.1100\ 0000 $& &$S_0={\color{blue}0001}.0000\ 0000\ 00$\\
|
||||
&$WS=X-1 $&$ 1111.1100\ 0000 $& &$SM_0={\color{blue}0000}.0000\ 0000\ 00\phantom{M}$\\
|
||||
&$WC $&$ 0000.0000\ 0000 $& &$K_0=0000.0100\ 0000\ 00\ $\\
|
||||
& & & &$C_0=1111.1100\ 0000\ 00\,$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS $&$ 1111.1100\ 0000 $& &\\
|
||||
&$WC $&$ 0000.0000\ 0000 $& &($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
|
||||
&$F_1=0 $&${\color{blue}0000.00}00\ 0000$& &$S_1={\color{blue}0001.0}000\ 0000\ 00$\\
|
||||
& & & &$SM_1={\color{blue}0000.1}000\ 0000\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$ 1111.1100\ 0000 $&$\ll1 $&$K_1=0000.0010\ 0000\ 00\ $\\
|
||||
&$WC $&$ 0000.0000\ 0000 $&$\ll1 $&$C_1=1111.1110\ 0000\ 00\,$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS $&$ 1111.1000\ 0000 $& &\\
|
||||
&$WC $&$ 0000.0000\ 0000 $& &($W_{msbs}=1111\ \text{so}\ s_2=0$)\\
|
||||
&$F_2=0 $&${\color{blue}0000.000}0\ 0000$& &$S_2={\color{blue}0001.00}00\ 0000\ 00$\\
|
||||
& & & &$SM_2={\color{blue}0000.11}00\ 0000\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$ 1111.1000\ 0000 $&$\ll1 $&$K_2=0000.0001\ 0000\ 00\ $\\
|
||||
&$WC $&$ 0000.0000\ 0000 $&$\ll1 $&$C_2=1111.1111\ 0000\ 00\,$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS $&$ 1111.0000\ 0000 $& &\\
|
||||
&$WC $&$ 0000.0000\ 0000 $& &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
|
||||
&$F_3=0 $&${\color{blue}0000.0000}\ 0000$& &$S_3={\color{blue}0001.000}0\ 0000\ 00$\\
|
||||
& & & &$SM_3={\color{blue}0000.111}0\ 0000\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.0000\ 0000 $&$\ll1 $&$K_3=0000.0000\ 1000\ 00\ $\\
|
||||
&$WC $&$0000.0000\ 0000 $&$\ll1 $&$C_3=1111.1111\ 1000\ 00\,$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS $&$1110.0000\ 0000 $& &\\
|
||||
&$WC $&$0000.0000\ 0000 $& &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
|
||||
&$F_4=S_3-K_3 $&${\color{blue}0000.1111\ 1}000$& &$S_4={\color{blue}0000.1111}\ 0000\ 00$\\
|
||||
& & & &$SM_4={\color{blue}0000.1110}\ 0000\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1110.1111\ 1000 $&$\ll1 $&$K_4=0000.0000\ 0100\ 00\ $\\
|
||||
&$WC $&$0000.0000\ 0000 $&$\ll1 $&$C_4=1111.1111\ 1100\ 00\,$\\
|
||||
\hdashline\\
|
||||
Step 5: &$WS $&$1101.1111\ 0000 $& &\\
|
||||
&$WC $&$0000.0000\ 0000 $& &($W_{msbs}=1101\ \text{so}\ s_5=-1$)\\
|
||||
&$F_5=S_4-K_4 $&${\color{blue}0000.1110\ 11}00$& &$S_5={\color{blue}0000.1110\ 1}000\ 00$\\
|
||||
& & & &$SM_5={\color{blue}0001.1110\ 0}000\ 00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1101.0001\ 1100 $&$\ll1 $&$K_5=0000.0000\ 0010\ 00\ $\\
|
||||
&$WC $&$0001.1100\ 0000 $&$\ll1 $&$C_5=1111.1111\ 1110\ 00\,$\\
|
||||
Terminate
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
X = 0.1010101101(685/1024)
|
||||
|
||||
S = 0.1101000110(838/1024)
|
||||
|
||||
once R4 sslc gets here i can fill this in
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
X = 1.1001 (25/16)
|
||||
|
||||
S = 1.0100 (20/16)
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Attempt 1:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q4.0\\
|
||||
&&&\\
|
||||
&$X $&$0001.1001$&\\
|
||||
&$WS=X-1$&$0000.1001$& $s_0=1$\\
|
||||
&$WC $&$0000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
|
||||
\hdashline\\
|
||||
Step 1: &$WS $&$0000.1001$&\\
|
||||
&$WC $&$0000.0000$&($W_{msbs}=0000\ \text{so}\ s_1=1$)\\
|
||||
&$F $&$1110.1100$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1110.0101$&$\ll1$\\
|
||||
&$WC $&$0001.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS $&$1100.1010$&\\
|
||||
&$WC $&$0010.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
|
||||
&$F $&$0001.0110$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1110$&$\ll1$\\
|
||||
&$WC $&$0000.0010$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS $&$1111.1100$&\\
|
||||
&$WC $&$0000.0100$&($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
|
||||
&$-q_3D $&$0000.0000$&$S_3=\mathbf{1.010}0,\quad SM_3=\mathbf{1.001}0$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1000$&$\ll1$\\
|
||||
&$WC $&$0000.1000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS $&$1111.0000$&\\
|
||||
&$WC $&$0001.0000$&($W_{msbs}=0000\ \text{so}\ s_4=1$)\\
|
||||
&$F $&$0000.0000$&$S_4=\mathbf{1.0101},\quad SM_4=\mathbf{1.0100}$\\
|
||||
Terminate&&&
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Attempt 2:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q3.1\\
|
||||
&&&\\
|
||||
&$X $&$001.1001$&\\
|
||||
&$WS=X-1$&$000.1001$& $s_0=1$\\
|
||||
&$WC $&$000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
|
||||
\hdashline\\
|
||||
Step 1: &$WS $&$000.1001$&\\
|
||||
&$WC $&$000.0000$&($W_{msbs}=000.1\ \text{so}\ s_1=1$)\\
|
||||
&$F $&$110.1000$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$110.0001$&$\ll1$\\
|
||||
&$WC $&$001.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS $&$100.0010$&\\
|
||||
&$WC $&$010.0000$&($W_{msbs}=110.0\ \text{so}\ s_2=-1$)\\
|
||||
&$F $&$001.0100$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$111.0110$&$\ll1$\\
|
||||
&$WC $&$000.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS $&$110.1100$&\\
|
||||
&$WC $&$000.0000$&($W_{msbs}=110.1\ \text{so}\ s_3=-1$)\\
|
||||
&$-q_3D $&$001.0010$&$S_3=\mathbf{1.001}0,\quad SM_3=\mathbf{1.000}0$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$111.1110$&$\ll1$\\
|
||||
&$WC $&$000.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS $&$111.1110$&\\
|
||||
&$WC $&$000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
|
||||
&$F $&$000.0000$&$S_4=\mathbf{1.0010},\quad SM_4=\mathbf{1.0001}$\\
|
||||
Terminate&&&
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Attempt 3:& $X$ is normalized& to $1<X<4$&$W_{msbs}$ looks at Q4.0\\
|
||||
&&&\\
|
||||
&$X $&$0001.1001$&\\
|
||||
&$WS=X-2$&$1111.1001$& $s_{-1}=10$\\
|
||||
&$WC $&$0000.0000$&$S_{-1}=\mathbf{1}0.0000,\quad SM_{-1}=\mathbf{0}0.0000$ \\
|
||||
\hdashline\\
|
||||
Step 0: &$WS $&$1111.1001$&\\
|
||||
&$WC $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_0=0$)\\
|
||||
&$F $&$0000.0000$&$S_0=\mathbf{10}.0000,\quad SM_0=\mathbf{01}.0000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1001$&$\ll1$\\
|
||||
&$WC $&$0000.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS $&$1111.0010$&\\
|
||||
&$WC $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
|
||||
&$F $&$0000.0000$&$S_1=\mathbf{10.0}000,\quad SM_1=\mathbf{01.1}000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.0010$&$\ll1$\\
|
||||
&$WC $&$0000.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS $&$1110.0100$&\\
|
||||
&$WC $&$0000.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
|
||||
&$-q_3D $&$0001.1100$&$S_2=\mathbf{01.01}00,\quad SM_2=\mathbf{01.00}00$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1000$&$\ll1$\\
|
||||
&$WC $&$0000.1000$&$\ll1$\\
|
||||
Terminate&&&
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
\vfill
|
||||
\eject
|
||||
|
||||
X = 0.011001 (25/64)
|
||||
|
||||
S = 0.101000 (40/64)
|
||||
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{cccc}
|
||||
Attempt 4:& $X$ is normalized& to $1/4<X<1$&$W_{msbs}$ looks at Q3.1\\
|
||||
&&&\\
|
||||
&$X $&$000.0110\ 01$&\\
|
||||
&$WS=X-1$&$111.0110\ 01$& $s_0=1$\\
|
||||
&$WC $&$000.0000\ 00$&$S_0=\mathbf{1}.000000,\quad SM_0=\mathbf{0}.000000$ \\
|
||||
\hdashline\\
|
||||
Step 1: &$WS $&$111.0110\ 01$&\\
|
||||
&$WC $&$000.0000\ 00$&($W_{msbs}=111.0\ \text{so}\ s_1=-1$)\\
|
||||
&$F $&$000.1000\ 00$&$S_1=\mathbf{0.1}00000,\quad SM_1=\mathbf{0.0}00000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$111.1110\ 01$&$\ll1$\\
|
||||
&$WC $&$000.0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS $&$111.1100\ 10$&\\
|
||||
&$WC $&$000.0000\ 00$&($W_{msbs}=111.1\ \text{so}\ s_2=0$)\\
|
||||
&$F $&$000.0000\ 00$&$S_2=\mathbf{0.10}0000,\quad SM_2=\mathbf{0.01}0000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$111.1100\ 10$&$\ll1$\\
|
||||
&$WC $&$000.0000\ 00$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS $&$111.1001\ 00$&\\
|
||||
&$WC $&$000.0000\ 00$&($W_{msbs}=010.0\ \text{so}\ s_3=1$)\\
|
||||
&$-q_3D $&$111.0010\ 00$&$S_3=\mathbf{0.111}000,\quad SM_3=\mathbf{0.110}000$\\
|
||||
\cline{2-3}
|
||||
&$WS $&$1111.1110$&$\ll1$\\
|
||||
&$WC $&$0000.0000$&$\ll1$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS $&$1111.1110$&\\
|
||||
&$WC $&$0000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
|
||||
&$F $&$0000.0000$&$S_4=\mathbf{1.0010}00,\quad SM_4=\mathbf{1.0001}00$\\
|
||||
Terminate&&&
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
|
||||
\end{document}
|
||||
147
docs/divsqrt_tex/sqrt4.tex
Normal file
147
docs/divsqrt_tex/sqrt4.tex
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
\documentclass[12pt]{article}
|
||||
|
||||
\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
|
||||
|
||||
\usepackage{arydshln}
|
||||
|
||||
\parskip = .2in
|
||||
\parindent = 0in
|
||||
|
||||
\pagestyle{empty}
|
||||
|
||||
%==========
|
||||
%==========
|
||||
|
||||
\begin{document}
|
||||
|
||||
|
||||
|
||||
X = 0.1011 0111 10 (734/1024)
|
||||
|
||||
S = 0.1101 1000 11\ 00 (3468/4096), negative sticky bit
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{ccccc}
|
||||
&$X $&$ 0000.1011\ 0111\ 1000 $& &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
|
||||
&$WS_0=4(X-1) $&$ 1110.1101\ 1110\ 0000 $& &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &$K_0=0001.0000\ 0000\ 0000\ $\\
|
||||
& & & &$C_0=1111.0000\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS_0 $&$ 1110.1101\ 1110\ 0000 $& &\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &($W_{msbs}=1110.110\ \text{so}\ s_1=-1$)\\
|
||||
&$F_1=2S_0-K_1$&${\color{blue}0001.11}00\ 0000\ 0000$& &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
|
||||
& & & &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0001\ 1110\ 0000 $&$\ll2 $&$K_1=0000.0100\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0001.1000\ 0000\ 0000 $&$\ll2 $&$C_1=1111.1100\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS_1 $&$ 1100.0111\ 1000\ 0000 $& &\\
|
||||
&$WC_1 $&$ 0110.0000\ 0000\ 0000 $& &($W_{msbs}=0010.011\ \text{so}\ s_2=2$)\\
|
||||
&$F_2=-4S_1-4K_2$&${\color{blue}1100.1100}\ 0000\ 0000$& &$S_2={\color{blue}0000.1110}\ 0000\ 0000$\\
|
||||
& & & &$SM_2={\color{blue}0000.1101}\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0110.1011\ 1000\ 0000 $&$\ll2 $&$K_2=0000.0001\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 1000.1000\ 0000\ 0000 $&$\ll2 $&$C_2=1111.1111\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS_2 $&$ 1010.1110\ 0000\ 0000 $& &\\
|
||||
&$WC_2 $&$ 0010.0000\ 0000\ 0000 $& &($W_{msbs}=1100.111\ \text{so}\ s_3=-2$)\\
|
||||
&$F_3=4S_2-4K_3$&${\color{blue}0011.0111\ 00}00\ 0000$& &$S_3={\color{blue}0000.1101\ 10}00\ 0000$\\
|
||||
& & & &$SM_3={\color{blue}0000.1101\ 01}00\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1011.1001\ 0000\ 0000 $&$\ll2 $&$K_3=0000.0000\ 0100\ 0000\ $\\
|
||||
&$carry $&$ 0100.1100\ 0000\ 0000 $&$\ll2 $&$C_3=1111.1111\ 1100\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS_3 $&$ 1110.0100\ 0000\ 0000 $& &\\
|
||||
&$WC_3 $&$ 0011.0000\ 0000\ 0000 $& &($W_{msbs}=0001.010\ \text{so}\ s_4=1$)\\
|
||||
&$F_4=-2S_3-K_4$&${\color{blue}1110.0100\ 1111}\ 0000$& &$S_4={\color{blue}0000.1101\ 1001}\ 0000$\\
|
||||
& & & &$SM_4={\color{blue}0000.1101\ 1000}\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0011.0000\ 1111\ 0000 $&$\ll2 $&$K_4=0000.0000\ 0001\ 0000\ $\\
|
||||
&$carry $&$ 1100.1000\ 0000\ 0000 $&$\ll2 $&$C_4=1111.1111\ 1111\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 5: &$WS_4 $&$ 1100.0011\ 1100\ 0000 $& &\\
|
||||
&$WC_4 $&$ 0010.0000\ 0000\ 0000 $& &($W_{msbs}=1110.001\ \text{so}\ s_5=-1$)\\
|
||||
&$F_5=2S_4-K_5 $&${\color{blue}0001.1011\ 0001\ 11}00$& &$S_5={\color{blue}0000.1101\ 1000\ 11}00$\\
|
||||
& & & &$SM_5={\color{blue}0000.1101\ 1000\ 10}00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.1000\ 1101\ 1100 $&$\ll2 $&$K_5=0000.0000\ 0000\ 0100\ $\\
|
||||
&$carry $&$ 0000.0110\ 0000\ 0000 $&$\ll2 $&$C_5=1111.1111\ 1111\ 1100\,$\\
|
||||
\hdashline\\
|
||||
Step 6: &$WS_5 $&$ 1110.0011\ 0111\ 0000 $& &\\
|
||||
&$WC_5 $&$ 0001.1000\ 0000\ 0000 $& &($W_{msbs}=1111.101\ \text{so}\ s_6=0$)\\
|
||||
&$F_6=0 $&${\color{blue}0000.0000\ 0000\ 0000}$& &$S_6={\color{blue}0000.1101\ 1000\ 1100}$\\
|
||||
& & & &$SM_6={\color{blue}0000.1101\ 1000\ 1011}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.1011\ 0111\ 0111 $&$\ll2 $&$K_6=0000.0000\ 0000\ 0001\ $\\
|
||||
&$carry $&$ 0000.0000\ 0000\ 0000 $&$\ll2 $&$C_6=1111.1111\ 1111\ 1111\,$\\
|
||||
\hdashline\\
|
||||
Terminate&Square Root&0000.11 01\ 10 00\ 10 (11)
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
X = 0.1001\ 0101\ 00 (596/1024)
|
||||
|
||||
S = 0.1100 0011 01\ 01 (3125/4096)
|
||||
{\small
|
||||
\begin{center}
|
||||
\begin{tabular}{ccccc}
|
||||
&$X $&$ 0000.1001\ 0101\ 0000 $& &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
|
||||
&$WS_0=4(X-1) $&$ 1110.0101\ 0100\ 0000 $& &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &$K_0=0001.0000\ 0000\ 0000\ $\\
|
||||
& & & &$C_0=1111.0000\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 1: &$WS_0 $&$ 1110.0101\ 0100\ 0000 $& &\\
|
||||
&$WC_0 $&$ 0000.0000\ 0000\ 0000 $& &($W_{msbs}=1110.010\ \text{so}\ s_1=-1$)\\
|
||||
&$F_1=2S_0-K_1 $&${\color{blue}0001.11}00\ 0000\ 0000$& &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
|
||||
& & & &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.1001\ 0100\ 0000 $&$\ll2 $&$K_1=0000.0100\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0000.1000\ 0000\ 0000 $&$\ll2 $&$C_1=1111.1100\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 2: &$WS_1 $&$ 1110.0101\ 0000\ 0000 $& &\\
|
||||
&$WC_2 $&$ 0010.0000\ 0000\ 0000 $& &($W_{msbs}=0000.010\ \text{so}\ s_2=0$)\\
|
||||
&$F_2=0 $&${\color{blue}0000.0000}\ 0000\ 0000$& &$S_2={\color{blue}0000.1100}\ 0000\ 0000$\\
|
||||
& & & &$SM_2={\color{blue}0000.1110}\ 0000\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1100.0101\ 0000\ 0000 $&$\ll2 $&$K_2=0000.0001\ 0000\ 0000\ $\\
|
||||
&$carry $&$ 0100.0000\ 0000\ 0000 $&$\ll2 $&$C_2=1111.1111\ 0000\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 3: &$WS_2 $&$ 0001.0100\ 0000\ 0000 $& &\\
|
||||
&$WC_2 $&$ 0000.0000\ 0000\ 0000 $& &($W_{msbs}=0001.010\ \text{so}\ s_3=1$)\\
|
||||
&$F_3=-2S_2-K_3$&${\color{blue}1110.0111\ 11}00\ 0000$& &$S_3={\color{blue}0000.1100\ 01}00\ 0000$\\
|
||||
& & & &$SM_3={\color{blue}0000.1100\ 00}00\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0011\ 1100\ 0000 $&$\ll2 $&$K_3=0000.0000\ 0100\ 0000\ $\\
|
||||
&$carry $&$ 1000.1000\ 0000\ 0000 $&$\ll2 $&$C_3=1111.1111\ 1100\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 4: &$WS_3 $&$ 1100.1111\ 0000\ 0000 $& &\\
|
||||
&$WC_3 $&$ 0010.0000\ 0000\ 0000 $& &($W_{msbs}=1110.111\ \text{so}\ s_4=-1$)\\
|
||||
&$F_4=2S_3-K_3 $&${\color{blue}0001.1000\ 0111}\ 0000$& &$S_4={\color{blue}0000.1100\ 0011}\ 0000$\\
|
||||
& & & &$SM_4={\color{blue}0000.1100\ 0010}\ 0000\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 1111.0111\ 0111\ 0000 $&$\ll2 $&$K_4=0000.0000\ 0001\ 0000\ $\\
|
||||
&$carry $&$ 0001.0000\ 0000\ 0000 $&$\ll2 $&$C_4=1111.1111\ 1111\ 0000\,$\\
|
||||
\hdashline\\
|
||||
Step 5: &$WS_4 $&$ 1101.1101\ 1100\ 0000 $& &\\
|
||||
&$WC_4 $&$ 0100.0000\ 0000\ 0000 $& &($W_{msbs}=0001.110\ \text{so}\ s_5=1$)\\
|
||||
&$F_5=-2S_4-K_4 $&${\color{blue}1110.0111\ 1001\ 11}00$& &$S_5={\color{blue}0000.1100\ 0011\ 01}00$\\
|
||||
& & & &$SM_5={\color{blue}0000.1100\ 0011\ 00}00\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0111.1010\ 0101\ 1100 $&$\ll1 $&$K_5=0000.0000\ 0000\ 0100\ $\\
|
||||
&$carry $&$ 1000.1011\ 0000\ 0000 $&$\ll1 $&$C_5=1111.1111\ 1111\ 1100\,$\\
|
||||
\hdashline\\
|
||||
Step 6: &$WS_5 $&$ 1110.1001\ 0111\ 0000 $& &\\
|
||||
&$WC_5 $&$ 0010.1100\ 0000\ 0000 $& &($W_{msbs}=0001.010\ \text{so}\ s_6=1$)\\
|
||||
&$F_6= $&$ $& &$S_5={\color{blue}0000.1100\ 0011\ 0101}$\\
|
||||
& & & &$SM_5={\color{blue}0000.1100\ 0011\ 0100}\phantom{M}$\\
|
||||
\cline{2-3}
|
||||
&$sum $&$ 0001.1110\ 1001\ 0111 $&$\ll1 $&$K_5=0000.0000\ 0000\ 0001\ $\\
|
||||
&$carry $&$ 1110.0010\ 1100\ 0000 $&$\ll1 $&$C_5=1111.1111\ 1111\ 1111\,$\\
|
||||
\hdashline\\
|
||||
Terminate
|
||||
\end{tabular}
|
||||
\end{center}
|
||||
}
|
||||
|
||||
\end{document}
|
||||
|
|
@ -2,14 +2,13 @@
|
|||
|
||||
CC = gcc
|
||||
CFLAGS = -O3
|
||||
LIBS = -lm
|
||||
LFLAGS = -L.
|
||||
# Link against the riscv-isa-sim version of SoftFloat rather than
|
||||
# the regular version to get RISC-V NaN behavior
|
||||
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
|
||||
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
|
||||
#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
|
||||
#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
|
||||
#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
|
||||
#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
|
||||
IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
|
||||
LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
SRCS = $(wildcard *.c)
|
||||
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
|
||||
|
|
@ -17,7 +16,7 @@ PROGS = $(patsubst %.c,%,$(SRCS))
|
|||
all: $(PROGS)
|
||||
|
||||
%: %.c
|
||||
$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
|
||||
$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
|
||||
|
||||
clean:
|
||||
rm -f $(PROGS)
|
||||
|
|
|
|||
|
|
@ -1,77 +0,0 @@
|
|||
//
|
||||
// softfloat_div.c
|
||||
// james.stine@okstate.edu 12 April 2023
|
||||
//
|
||||
// Demonstrate using SoftFloat to compute 754 fp divide, then print results
|
||||
// (adapted from original C built by David Harris)
|
||||
//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
unsigned short x[2];
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %1.15g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RU: softfloat_round_max
|
||||
// RD: softfloat_round_min
|
||||
// RM: softfloat_round_near_maxMag
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main() {
|
||||
|
||||
// float32_t is typedef in SoftFloat
|
||||
float32_t x, y, r1, r2;
|
||||
sp convx, convy;
|
||||
|
||||
// Choose two random values
|
||||
convx.f = 1.30308703073;
|
||||
convy.f = 1.903038030370;
|
||||
// Convert to SoftFloat format
|
||||
x.v = (convx.x[1] << 16) + convx.x[0];
|
||||
y.v = (convy.x[1] << 16) + convy.x[0];
|
||||
|
||||
printf("Example using SoftFloat\n");
|
||||
|
||||
softfloatInit();
|
||||
r1 = f32_div(x, y);
|
||||
printf("-------\n");
|
||||
printF32("X", x);
|
||||
printF32("Y", y);
|
||||
printF32("result = X/Y", r1);
|
||||
printFlags();
|
||||
|
||||
r2 = f32_sqrt(x);
|
||||
printf("-------\n");
|
||||
printF32("X", x);
|
||||
printF32("result = sqrt(X)", r2);
|
||||
printFlags();
|
||||
|
||||
}
|
||||
88
examples/fp/softfloat_demo/softfloat_demoDP.c
Normal file
88
examples/fp/softfloat_demo/softfloat_demoDP.c
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
// softfloat_demo3.c
|
||||
// james.stine@okstate.edu 15 August 2023
|
||||
//
|
||||
// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#include <quadmath.h> // GCC Quad-Math Library
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
typedef union dp {
|
||||
uint64_t v;
|
||||
double d;
|
||||
} dp;
|
||||
|
||||
typedef union qp {
|
||||
uint64_t v[2];
|
||||
__float128 q;
|
||||
} qp;
|
||||
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printF64 (char *msg, float64_t d) {
|
||||
dp conv;
|
||||
int i, j;
|
||||
conv.v = d.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
|
||||
}
|
||||
|
||||
void printF128 (char *msg, float128_t q) {
|
||||
qp conv;
|
||||
int i, j;
|
||||
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
|
||||
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// rounding modes: RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RP: softfloat_round_max
|
||||
// RM: softfloat_round_min
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main() {
|
||||
|
||||
float64_t x, y, z;
|
||||
float64_t r;
|
||||
|
||||
x.v = 0xBFFF988ECE97DFEB;
|
||||
y.v = 0x3F8EFFFFFFFFFFFF;
|
||||
z.v = 0x4001000000000000;
|
||||
|
||||
softfloatInit();
|
||||
printF64("X", x); printF64("Y", y); printF64("Z", z);
|
||||
r = f64_mulAdd(x, y, z);
|
||||
printf("\n");
|
||||
printF64("r", r);
|
||||
|
||||
}
|
||||
91
examples/fp/softfloat_demo/softfloat_demoQP.c
Normal file
91
examples/fp/softfloat_demo/softfloat_demoQP.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
// softfloat_demo3.c
|
||||
// james.stine@okstate.edu 15 August 2023
|
||||
//
|
||||
// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#include <quadmath.h> // GCC Quad-Math Library
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
typedef union dp {
|
||||
uint64_t v;
|
||||
double d;
|
||||
} dp;
|
||||
|
||||
typedef union qp {
|
||||
uint64_t v[2];
|
||||
__float128 q;
|
||||
} qp;
|
||||
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printF64 (char *msg, float64_t d) {
|
||||
dp conv;
|
||||
int i, j;
|
||||
conv.v = d.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
|
||||
}
|
||||
|
||||
void printF128 (char *msg, float128_t q) {
|
||||
qp conv;
|
||||
int i, j;
|
||||
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
|
||||
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// rounding modes: RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RP: softfloat_round_max
|
||||
// RM: softfloat_round_min
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main() {
|
||||
|
||||
float128_t x, y, z;
|
||||
float128_t r;
|
||||
|
||||
x.v[1] = 0xBFFF988ECE97DFEB;
|
||||
x.v[0] = 0xC3BBA082445B4836;
|
||||
y.v[1] = 0x3F8EFFFFFFFFFFFF;
|
||||
y.v[0] = 0xFFFFFFFFFFFFFFFF;
|
||||
z.v[1] = 0x4001000000000000;
|
||||
z.v[0] = 0x0000000000000000;
|
||||
|
||||
softfloatInit();
|
||||
printF128("X", x); printF128("Y", y); printF128("Z", z);
|
||||
r = f128_mulAdd(x, y, z);
|
||||
printf("\n");
|
||||
printF128("r", r);
|
||||
|
||||
}
|
||||
88
examples/fp/softfloat_demo/softfloat_demoSP.c
Normal file
88
examples/fp/softfloat_demo/softfloat_demoSP.c
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
// softfloat_demo3.c
|
||||
// james.stine@okstate.edu 15 August 2023
|
||||
//
|
||||
// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#include <quadmath.h> // GCC Quad-Math Library
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
typedef union dp {
|
||||
uint64_t v;
|
||||
double d;
|
||||
} dp;
|
||||
|
||||
typedef union qp {
|
||||
uint64_t v[2];
|
||||
__float128 q;
|
||||
} qp;
|
||||
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printF64 (char *msg, float64_t d) {
|
||||
dp conv;
|
||||
int i, j;
|
||||
conv.v = d.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%08x_%08x = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
|
||||
}
|
||||
|
||||
void printF128 (char *msg, float128_t q) {
|
||||
qp conv;
|
||||
int i, j;
|
||||
conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
|
||||
conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// rounding modes: RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RP: softfloat_round_max
|
||||
// RM: softfloat_round_min
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main() {
|
||||
|
||||
float32_t x, y, z;
|
||||
float32_t r;
|
||||
|
||||
x.v = 0xBFFF988E;
|
||||
y.v = 0x3F8EFFFF;
|
||||
z.v = 0x40010000;
|
||||
|
||||
softfloatInit();
|
||||
printF32("X", x); printF32("Y", y); printF32("Z", z);
|
||||
r = f32_mulAdd(x, y, z);
|
||||
printf("\n");
|
||||
printF32("r", r);
|
||||
|
||||
}
|
||||
|
|
@ -5,6 +5,7 @@ WALLY := $(shell dirname $(shell pwd))
|
|||
WALLYLINUX := $(shell pwd)
|
||||
DIS := ${IMAGES}/disassembly
|
||||
BRPACKAGES := $(WALLYLINUX)/buildroot-packages
|
||||
BR2023 := $(WALLYLINUX)/buildroot-config-src/buildroot-2023.05.1
|
||||
|
||||
# Buildroot Config Stuff
|
||||
WALLYBOARDSRC := $(WALLYLINUX)/buildroot-config-src/wally
|
||||
|
|
@ -14,7 +15,7 @@ WALLYBOARD := $(BUILDROOT)/board/wally
|
|||
PACKAGE_SOURCE := ${WALLYLINUX}/buildroot-packages/package-source
|
||||
FPGA_AXI_SDC := ${WALLYLINUX}/buildroot-packages/fpga-axi-sdc
|
||||
DRIVER := ${PACKAGE_SOURCE}/fpga-axi-sdc.c
|
||||
PATCHFILE := $(BRPACKAGES)/package.patch
|
||||
PATCHFILE := $(BRPACKAGES)/package-2023.05.1.patch
|
||||
|
||||
# Device tree files
|
||||
DTS ?= $(shell find -type f -regex ".*\.dts" | sort)
|
||||
|
|
@ -26,6 +27,23 @@ BINARIES := fw_jump.elf vmlinux busybox
|
|||
OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
|
||||
OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
|
||||
|
||||
# LINUXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
|
||||
# LINUXDIR := $(BUILDROOT)/output/build/$(LINUXDIR)
|
||||
# BUSYBOXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' )
|
||||
# BUSYBOXDIR := $(BUILDROOT)/output/build/$(BUSYBOXDIR)
|
||||
|
||||
# Gets Linux and Busybox output folders for objedect dumps
|
||||
# LINUXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
# BUSYBOXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
|
||||
define linuxDir =
|
||||
$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
endef
|
||||
|
||||
define busyboxDir =
|
||||
$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
endef
|
||||
|
||||
.PHONY: all generate disassemble install clean cleanDTB cleanDriver test
|
||||
|
||||
# Generate all device trees -------------------------------------------
|
||||
|
|
@ -41,7 +59,8 @@ all:
|
|||
|
||||
# Temp rule for debugging
|
||||
test:
|
||||
@echo $(OBJDUMPS)
|
||||
@echo $(linuxDir)
|
||||
@echo $(busyboxDir)
|
||||
|
||||
generate: $(DTB) $(IMAGES)
|
||||
|
||||
|
|
@ -68,16 +87,16 @@ $(DIS)/%.objdump: $(IMAGES)/%.elf
|
|||
$(DIS)/%.objdump: $(IMAGES)/%
|
||||
riscv64-unknown-elf-objdump -S $< >> $@
|
||||
|
||||
$(IMAGES)/vmlinux: $(BUILDROOT)/output/build/linux-5.10.7/vmlinux
|
||||
$(IMAGES)/vmlinux: $(call linuxDir)/vmlinux
|
||||
cp $< $@
|
||||
|
||||
$(IMAGES)/busybox: $(BUILDROOT)/output/build/busybox-1.33.0/busybox
|
||||
$(IMAGES)/busybox: $(call busyboxDir)/busybox
|
||||
cp $< $@
|
||||
|
||||
# Generating new Buildroot directories --------------------------------
|
||||
|
||||
# This directive should be run as: make install BUILDROOT=path/to/buildroot
|
||||
install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) $(DRIVER)
|
||||
install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD)
|
||||
cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config
|
||||
|
||||
# CONFIG DEPENDENCIES 2021.05 -----------------------------------------
|
||||
|
|
@ -87,10 +106,16 @@ install: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) $(DRIVER)
|
|||
# $(WALLYBOARD)/linux.config: $(BRPACKAGES)/linux.config $(WALLYBOARD)
|
||||
# cp $(BRPACKAGES)/linux.config $@
|
||||
|
||||
# $(WALLYBOARD): $(BUILDROOT)
|
||||
# cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
|
||||
# cp $(BRPACKAGES)/wally.config $(WALLYBOARD)/main.config
|
||||
# cp $(BRPACKAGES)/linux.config $(WALLYBOARD)/linux.config
|
||||
|
||||
# CONFIG DEPENDENCIES 2023.05.1 ---------------------------------------
|
||||
$(WALLYBOARD): $(BUILDROOT)
|
||||
cp -r $(WALLYBOARDSRC) $(BUILDROOT)/board
|
||||
cp $(BRPACKAGES)/wally.config $(WALLYBOARD)/main.config
|
||||
cp $(BRPACKAGES)/linux.config $(WALLYBOARD)/linux.config
|
||||
cp $(BR2023)/main.config $(WALLYBOARD)/main.config
|
||||
cp $(BR2023)/linux.config $(WALLYBOARD)/linux.config
|
||||
|
||||
# Buildroot Package ---------------------------------------------------
|
||||
$(BUILDROOT)/package/fpga-axi-sdc: $(BUILDROOT) $(PATCHFILE) $(BRPACKAGES)/fpga-axi-sdc
|
||||
|
|
@ -103,14 +128,14 @@ $(PATCHFILE):
|
|||
|
||||
$(BUILDROOT):
|
||||
git clone https://github.com/buildroot/buildroot.git $@
|
||||
# cd $@; git checkout 2023.05.x
|
||||
cd $@; git checkout 2021.05
|
||||
cd $@; git checkout 2023.05.x
|
||||
#cd $@; git checkout 2021.05
|
||||
|
||||
$(DRIVER):
|
||||
@ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
|
||||
cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
|
||||
#$(DRIVER):
|
||||
# @ if [ -d "$(WALLY)/addins/vivado-risc-v" ] ; then git submodule update --init $(WALLY)/addins/vivado-risc-v; fi
|
||||
# cp ../addins/vivado-risc-v/patches/fpga-axi-sdc.c $@
|
||||
# For 2021.05
|
||||
sed -i "s|card_hw_reset|hw_reset|1" $@
|
||||
#sed -i "s|card_hw_reset|hw_reset|1" $@
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -49,4 +49,13 @@ You'll find the resulting disassembled files in `<BUILDROOT>/output/images/disas
|
|||
|
||||
## Creating a Bootable SD Card <a name="sdcard"></a>
|
||||
|
||||
To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `<WALLY>/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `/opt/riscv` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type:
|
||||
|
||||
$ cd sdcard
|
||||
$ ./flash-sd.sh -b <path/to/buildroot> -d <device tree name> <DEVICE>
|
||||
|
||||
for example
|
||||
|
||||
$ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -9,7 +9,7 @@
|
|||
chosen {
|
||||
linux,initrd-end = <0x85c43a00>;
|
||||
linux,initrd-start = <0x84200000>;
|
||||
bootargs = "root=/dev/vda ro";
|
||||
bootargs = "root=/dev/vda ro console=ttyS0,115200";
|
||||
stdout-path = "/soc/uart@10000000";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
chosen {
|
||||
linux,initrd-end = <0x85c43a00>;
|
||||
linux,initrd-start = <0x84200000>;
|
||||
bootargs = "root=/dev/vda ro";
|
||||
bootargs = "console=ttyS0,115200 root=/dev/vda ro";
|
||||
stdout-path = "/soc/uart@10000000";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ BOLDYELLOW="\e[1;33m"
|
|||
NC="\e[0m"
|
||||
NAME="$BOLDGREEN"${0:2}:"$NC"
|
||||
ERRORTEXT="$BOLDRED"ERROR:"$NC"
|
||||
WARNINGTEXT="$BOLDYELLOW"Warning:"$NC"
|
||||
|
||||
# Default values for buildroot and device tree
|
||||
RISCV=/opt/riscv
|
||||
|
|
@ -110,7 +111,7 @@ echo -e "$NAME Device tree block size: $DST_SIZE"
|
|||
echo -e "$NAME OpenSBI FW_JUMP block size: $FW_JUMP_SIZE"
|
||||
echo -e "$NAME Kernel block size: $KERNEL_SIZE"
|
||||
|
||||
read -p "Warning: Doing this will replace all data on this card. Continue? y/n: " -n 1 -r
|
||||
read -p $'\e[1;33mWarning:\e[0m Doing this will replace all data on this card. Continue? y/n: ' -n 1 -r
|
||||
echo
|
||||
if [[ $REPLY =~ ^[Yy]$ ]] ; then
|
||||
DEVBASENAME=$(basename $SDCARD)
|
||||
|
|
@ -150,16 +151,16 @@ if [[ $REPLY =~ ^[Yy]$ ]] ; then
|
|||
|
||||
sleep 3
|
||||
|
||||
echo -e "$NAME: Copying binaries into their partitions."
|
||||
echo -e "$NAME Copying binaries into their partitions."
|
||||
DD_FLAGS="bs=4k iflag=fullblock oflag=direct conv=fsync status=progress"
|
||||
|
||||
echo -e "$NAME: Copying device tree"
|
||||
echo -e "$NAME Copying device tree"
|
||||
sudo dd if=$DEVICE_TREE of="$SDCARD"1 $DD_FLAGS
|
||||
|
||||
echo -e "$NAME: Copying OpenSBI"
|
||||
echo -e "$NAME Copying OpenSBI"
|
||||
sudo dd if=$FW_JUMP of="$SDCARD"2 $DD_FLAGS
|
||||
|
||||
echo -e "$NAME: Copying Kernel"
|
||||
echo -e "$NAME Copying Kernel"
|
||||
sudo dd if=$LINUX_KERNEL of="$SDCARD"3 $DD_FLAGS
|
||||
|
||||
sudo mkfs.ext4 "$SDCARD"4
|
||||
|
|
|
|||
12
sim/bp-results/branch-list.txt
Normal file
12
sim/bp-results/branch-list.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
gshare6.log gshare 6
|
||||
gshare8.log gshare 8
|
||||
gshare10.log gshare 10
|
||||
gshare12.log gshare 12
|
||||
gshare14.log gshare 14
|
||||
gshare16.log gshare 16
|
||||
twobit6.log twobit 6
|
||||
twobit8.log twobit 8
|
||||
twobit10.log twobit 10
|
||||
twobit12.log twobit 12
|
||||
twobit14.log twobit 14
|
||||
twobit16.log twobit 16
|
||||
6
sim/bp-results/btb-list.txt
Normal file
6
sim/bp-results/btb-list.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
btb6.log btb 6
|
||||
btb8.log btb 8
|
||||
btb10.log btb 10
|
||||
btb12.log btb 12
|
||||
btb14.log btb 14
|
||||
btb16.log btb 16
|
||||
6
sim/bp-results/class-list.txt
Normal file
6
sim/bp-results/class-list.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
class6.log class 6
|
||||
class8.log class 8
|
||||
class10.log class 10
|
||||
class12.log class 12
|
||||
class14.log class 14
|
||||
class16.log class 16
|
||||
5
sim/bp-results/ras-list.txt
Normal file
5
sim/bp-results/ras-list.txt
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
ras3.log ras 3
|
||||
ras4.log ras 4
|
||||
ras6.log ras 6
|
||||
ras10.log ras 10
|
||||
ras16.log ras 16
|
||||
|
|
@ -51,7 +51,7 @@ configs = [
|
|||
# for CurrBPType in bpdType:
|
||||
# for CurrBPSize in bpdSize:
|
||||
# name = CurrBPType+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=" + str(bpdType.index(CurrBPType)) + "+define+BPRED_SIZE=" + str(CurrBPSize)
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
|
|
@ -59,20 +59,42 @@ configs = [
|
|||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
LHRSize = [4, 8, 10]
|
||||
bpdType = ['local_repair']
|
||||
for CurrBPType in bpdType:
|
||||
for CurrBPSize in bpdSize:
|
||||
for CurrLHRSize in LHRSize:
|
||||
name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# for CurrBPSize in bpdSize:
|
||||
# name = 'BTB'+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=1 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE"
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
bpdSize = [2, 3, 4, 6, 10, 16]
|
||||
for CurrBPSize in bpdSize:
|
||||
name = 'RAS'+str(CurrBPSize)
|
||||
configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_OVERRIDE +define+BPRED_TYPE=\`BP_GSHARE" + "+define+BPRED_SIZE=16" + "+define+BTB_SIZE=16" + "+define+RAS_SIZE=" + str(CurrBPSize) + "+define+BTB_OVERRIDE+define+RAS_OVERRIDE"
|
||||
tc = TestCase(
|
||||
name=name,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
grepstr="")
|
||||
configs.append(tc)
|
||||
|
||||
# bpdSize = [6, 8, 10, 12, 14, 16]
|
||||
# LHRSize = [4, 8, 10]
|
||||
# bpdType = ['local_repair']
|
||||
# for CurrBPType in bpdType:
|
||||
# for CurrBPSize in bpdSize:
|
||||
# for CurrLHRSize in LHRSize:
|
||||
# name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
|
||||
# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
|
||||
# tc = TestCase(
|
||||
# name=name,
|
||||
# variant="rv32gc",
|
||||
# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
|
||||
# grepstr="")
|
||||
# configs.append(tc)
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
|
|
|||
687
sim/wave.do
687
sim/wave.do
|
|
@ -11,38 +11,38 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
|
|||
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
|
|
@ -68,41 +68,248 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValid
|
|||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOZeroHit
|
||||
add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNotHit2}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
|
||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
|
||||
add wave -noupdate -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
|
||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
|
||||
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
|
||||
add wave -noupdate -expand -group Bpred -divider {class check}
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
|
|
@ -119,6 +326,30 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
|
|||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
|
||||
add wave -noupdate -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MENVCFG_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
|
||||
add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
|
||||
|
|
@ -184,216 +415,6 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
|||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Tag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
|
||||
|
|
@ -493,51 +514,56 @@ add wave -noupdate -group ifu -expand -group icache -expand -group memory /testb
|
|||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold -radix unsigned /testbench/dut/core/ifu/bus/icache/icache/CacheSet
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]}
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
|
||||
|
|
@ -562,17 +588,17 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
|
|||
add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
|
||||
add wave -noupdate -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
|
|
@ -651,8 +677,15 @@ add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/LRUWriteEn
|
|||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/FlushStage
|
||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/CacheEn
|
||||
add wave -noupdate /testbench/dut/core/ifu/CacheableF
|
||||
add wave -noupdate /testbench/loggers/BeginSample
|
||||
add wave -noupdate /testbench/loggers/StartSample
|
||||
add wave -noupdate /testbench/loggers/reset
|
||||
add wave -noupdate -radix ascii /testbench/loggers/TEST
|
||||
add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/IllegalFPUInstrD
|
||||
add wave -noupdate /testbench/dut/core/fpu/fpu/fctrl/STATUS_FS
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/csrsr/STATUS_FS_INT
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {152124 ns} 0} {{Cursor 3} {152766 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 4} {172636 ns} 1} {{Cursor 4} {111958 ns} 0} {{Cursor 3} {152766 ns} 1}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
|
|
@ -668,4 +701,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {152015 ns} {152227 ns}
|
||||
WaveRestoreZoom {37879604 ns} {38203328 ns}
|
||||
|
|
|
|||
6
src/cache/cachefsm.sv
vendored
6
src/cache/cachefsm.sv
vendored
|
|
@ -171,9 +171,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
|
|||
assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
|
||||
(CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
|
||||
// coverage off -item e 1 -fecexprrow 8
|
||||
assign LRUWriteEn = ((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
|
||||
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck) |
|
||||
(CurrState == STATE_WRITE_LINE)) & ~FlushStage;
|
||||
assign LRUWriteEn = (((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
|
||||
(CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
|
||||
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck);
|
||||
// exclusion-tag-start: icache flushdirtycontrols
|
||||
assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty
|
||||
(CurrState == STATE_WRITE_LINE & (CacheRW[0])) |
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ typedef struct packed {
|
|||
int BPRED_NUM_LHR;
|
||||
int BPRED_SIZE;
|
||||
int BTB_SIZE;
|
||||
int RAS_SIZE;
|
||||
|
||||
// FPU division architecture
|
||||
int RADIX;
|
||||
|
|
@ -160,6 +161,12 @@ typedef struct packed {
|
|||
logic ZBC_SUPPORTED;
|
||||
logic ZBS_SUPPORTED;
|
||||
|
||||
// compressed
|
||||
logic ZCA_SUPPORTED;
|
||||
logic ZCB_SUPPORTED;
|
||||
logic ZCD_SUPPORTED;
|
||||
logic ZCF_SUPPORTED;
|
||||
|
||||
// Memory synthesis configuration
|
||||
logic USE_SRAM;
|
||||
|
||||
|
|
|
|||
|
|
@ -27,8 +27,7 @@
|
|||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RASPredictor import cvw::*; #(parameter cvw_t P,
|
||||
parameter StackSize = 16 )(
|
||||
module RASPredictor import cvw::*; #(parameter cvw_t P)(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
||||
|
|
@ -41,10 +40,10 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
|
|||
);
|
||||
|
||||
logic CounterEn;
|
||||
localparam Depth = $clog2(StackSize);
|
||||
localparam Depth = $clog2(P.RAS_SIZE);
|
||||
|
||||
logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr;
|
||||
logic [StackSize-1:0] [P.XLEN-1:0] memory;
|
||||
logic [P.RAS_SIZE-1:0] [P.XLEN-1:0] memory;
|
||||
integer index;
|
||||
|
||||
logic PopF;
|
||||
|
|
@ -76,14 +75,20 @@ module RASPredictor import cvw::*; #(parameter cvw_t P,
|
|||
assign P1 = 1;
|
||||
assign M1 = '1; // -1
|
||||
mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
|
||||
assign NextPtr = Ptr + IncDecPtr;
|
||||
logic [Depth-1:0] Sum;
|
||||
assign Sum = Ptr + IncDecPtr;
|
||||
if(|P.RAS_SIZE[Depth-1:0])
|
||||
assign NextPtr = Sum >= P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
|
||||
else
|
||||
assign NextPtr = Sum;
|
||||
//assign NextPtr = Ptr + IncDecPtr;
|
||||
|
||||
flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
|
||||
|
||||
// RAS must be reset.
|
||||
always_ff @ (posedge clk) begin
|
||||
if(reset) begin
|
||||
for(index=0; index<StackSize; index++)
|
||||
for(index=0; index<P.RAS_SIZE; index++)
|
||||
memory[index] <= {P.XLEN{1'b0}};
|
||||
end else if(PushE) begin
|
||||
memory[NextPtr] <= #1 PCLinkE;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module decompress #(parameter XLEN)(
|
||||
module decompress import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half
|
||||
output logic [31:0] InstrD, // Decompressed instruction
|
||||
output logic IllegalCompInstrD // Invalid decompressed instruction
|
||||
|
|
@ -88,20 +88,60 @@ module decompress #(parameter XLEN)(
|
|||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
|
||||
5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
||||
InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
|
||||
5'b00011: if (XLEN==32)
|
||||
InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
|
||||
5'b00011: if (P.XLEN==32)
|
||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
||||
InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
|
||||
5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
|
||||
5'b00100: if (P.ZCB_SUPPORTED)
|
||||
if (instr16[12:10] == 3'b000)
|
||||
InstrD = {10'b0, instr16[6:5], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
|
||||
else if (instr16[12:10] == 3'b001) begin
|
||||
if (instr16[6])
|
||||
InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
|
||||
else
|
||||
InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
|
||||
end else if (instr16[12:10] == 3'b010)
|
||||
InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[6:5], 7'b0000011}; // c.sb
|
||||
else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
|
||||
InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0000011}; // c.sh
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
||||
InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
|
||||
5'b00111: if (XLEN==32)
|
||||
InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
|
||||
5'b00111: if (P.XLEN==32)
|
||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
||||
InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
|
||||
5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
|
||||
5'b01001: if (XLEN==32)
|
||||
5'b01001: if (P.XLEN==32)
|
||||
InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
|
||||
else
|
||||
InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
|
||||
|
|
@ -125,33 +165,51 @@ module decompress #(parameter XLEN)(
|
|||
InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
|
||||
else // if (instr16[6:5] == 2'b11)
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
|
||||
else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
|
||||
if (instr16[6:5] == 2'b00)
|
||||
else if (instr16[12:10] == 3'b111) begin
|
||||
if (instr16[6:5] == 2'b00 & P.XLEN > 32)
|
||||
InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
|
||||
else if (instr16[6:5] == 2'b01)
|
||||
else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
|
||||
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
|
||||
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
|
||||
else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
|
||||
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
|
||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
|
||||
else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
|
||||
else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
|
||||
InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
|
||||
else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32)
|
||||
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
|
||||
else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED)
|
||||
InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
|
||||
else begin // reserved
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
// coverage off
|
||||
// are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
|
||||
// This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other
|
||||
// possible values for instr16[12:10] are covered by branches above. XLEN !> 32
|
||||
// will never occur in rv64gc so this branch can not be covered
|
||||
else begin // illegal instruction
|
||||
end else begin // illegal instruction
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
// coverage on
|
||||
5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
|
||||
5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
|
||||
5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
|
||||
5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
|
||||
5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
|
||||
5'b10011: if (XLEN == 32)
|
||||
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||
5'b10011: if (P.XLEN == 32)
|
||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
||||
InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
|
||||
5'b10100: if (instr16[12] == 0)
|
||||
|
|
@ -167,10 +225,20 @@ module decompress #(parameter XLEN)(
|
|||
InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
|
||||
else
|
||||
InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
|
||||
5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||
5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
|
||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
||||
else begin // unsupported instruction
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
||||
5'b10111: if (XLEN==32)
|
||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||
5'b10111: if (P.XLEN==32)
|
||||
if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED)
|
||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
||||
else begin
|
||||
IllegalCompInstrD = 1;
|
||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||
end
|
||||
else
|
||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
||||
default: begin // illegal instruction
|
||||
|
|
|
|||
|
|
@ -70,23 +70,24 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||
output logic IClassWrongM, // Class prediction is wrong
|
||||
output logic ICacheStallF, // I$ busy with multicycle operation
|
||||
// Faults
|
||||
input logic IllegalBaseInstrD, // Illegal non-compressed instruction
|
||||
input logic IllegalFPUInstrD, // Illegal FP instruction
|
||||
input logic IllegalBaseInstrD, // Illegal non-compressed instruction
|
||||
input logic IllegalFPUInstrD, // Illegal FP instruction
|
||||
output logic InstrPageFaultF, // Instruction page fault
|
||||
output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
|
||||
output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||
// mmu management
|
||||
input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
|
||||
input logic [P.XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
|
||||
input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
|
||||
input logic ITLBWriteF, // Writes PTE and PageType to ITLB
|
||||
input logic [P.XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
|
||||
input logic STATUS_MXR, // Status CSR: make executable page readable
|
||||
input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
|
||||
input logic STATUS_MPRV, // Status CSR: modify machine privilege
|
||||
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
|
||||
input logic [1:0] PrivilegeModeW, // Priviledge mode in Writeback stage
|
||||
input logic [P.XLEN-1:0] PTE, // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
|
||||
input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
|
||||
input logic ITLBWriteF, // Writes PTE and PageType to ITLB
|
||||
input logic [P.XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
|
||||
input logic STATUS_MXR, // Status CSR: make executable page readable
|
||||
input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
|
||||
input logic STATUS_MPRV, // Status CSR: modify machine privilege
|
||||
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
|
||||
input logic ENVCFG_PBMTE, // Page-based memory types enabled
|
||||
input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
|
||||
output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
|
||||
output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
|
||||
input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
|
||||
|
|
@ -171,7 +172,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||
assign TLBFlush = sfencevmaM & ~StallMQ;
|
||||
|
||||
mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1))
|
||||
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
|
||||
immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
|
||||
.PrivilegeModeW, .DisableTranslation(1'b0),
|
||||
.VAdr(PCFExt),
|
||||
.Size(2'b10),
|
||||
|
|
@ -352,9 +353,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
||||
|
||||
// expand 16-bit compressed instructions to 32 bits
|
||||
if (P.C_SUPPORTED) begin
|
||||
if (P.C_SUPPORTED | P.ZCA_SUPPORTED) begin
|
||||
logic IllegalCompInstrD;
|
||||
decompress #(P.XLEN) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||
decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||
end else begin
|
||||
assign InstrD = InstrRawD;
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ module spill import cvw::*; #(parameter cvw_t P) (
|
|||
assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
|
||||
end else
|
||||
assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed
|
||||
// Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
|
||||
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
|
||||
|
||||
always_ff @(posedge clk)
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
|
||||
input logic [1:0] STATUS_MPP, // Machine previous privilege mode
|
||||
input logic ENVCFG_PBMTE, // Page-based memory types enabled
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
|
||||
input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
|
||||
input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
|
||||
|
|
@ -153,7 +154,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
|
||||
.FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_HADE, .PrivilegeModeW,
|
||||
.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
|
||||
.WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
|
||||
.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
|
||||
|
|
@ -190,7 +191,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
|
|||
assign DisableTranslation = SelHPTW | FlushDCacheM;
|
||||
assign WriteAccessM = PreLSURWM[0] | (|CMOpM);
|
||||
mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
|
||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
|
||||
.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
|
||||
.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
|
||||
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
|
|||
// system status
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic [P.XLEN-1:0] ReadDataM, // page table entry from LSU
|
||||
input logic [P.XLEN-1:0] WriteDataM,
|
||||
|
|
@ -153,7 +154,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
|
|||
logic [P.XLEN-1:0] AccessedPTE;
|
||||
|
||||
assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
|
||||
mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
|
||||
mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when HADE = 0 because UpdatePTE = 0
|
||||
flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
|
||||
|
||||
assign SaveHPTWAdr = WalkerState == L0_ADR;
|
||||
|
|
@ -182,11 +183,12 @@ module hptw import cvw::*; #(parameter cvw_t P) (
|
|||
// hptw needs to know if there is a Dirty or Access fault occuring on this
|
||||
// memory access. If there is the PTE needs to be updated seting Access
|
||||
// and possibly also Dirty. Dirty is set if the operation is a store/amo.
|
||||
// However any other fault should not cause the update.
|
||||
assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
|
||||
// However any other fault should not cause the update, and updates are in software when ENVCFG_HADE = 0
|
||||
assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_HADE & ~OtherPageFault;
|
||||
|
||||
assign HPTWRW[0] = (WalkerState == UPDATE_PTE); // HPTWRW[0] will always be 0 if HADE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE
|
||||
assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if HADE = 0 because HPTWUpdateDA will be 0
|
||||
|
||||
assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
|
||||
assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;
|
||||
end else begin // block: hptwwrites
|
||||
assign NextPTE = ReadDataM;
|
||||
assign HPTWAdr = HPTWReadAdr;
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
|
|||
input logic STATUS_MPRV, // Status CSR: modify machine privilege
|
||||
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
|
||||
input logic ENVCFG_PBMTE, // Page-based memory types enabled
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
|
||||
input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
|
||||
input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW
|
||||
|
|
@ -82,7 +83,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
|
|||
.clk, .reset,
|
||||
.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
|
||||
.SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
|
||||
.VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
|
||||
.VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
|
||||
.PrivilegeModeW, .ReadAccess, .WriteAccess,
|
||||
.DisableTranslation, .PTE, .PageTypeWriteVal,
|
||||
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
|
|||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ENVCFG_PBMTE, // Page-based memory types enabled
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
|
||||
input logic ReadAccess,
|
||||
input logic WriteAccess,
|
||||
|
|
@ -104,7 +105,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
|
|||
|
||||
assign VPN = VAdr[P.VPN_BITS+11:12];
|
||||
|
||||
tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE,
|
||||
tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE,
|
||||
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
|
||||
.PTEAccessBits, .CAMHit, .Misaligned,
|
||||
.TLBMiss, .TLBHit, .TLBPageFault,
|
||||
|
|
|
|||
|
|
@ -32,10 +32,11 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
|
|||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
input logic [1:0] STATUS_MPP,
|
||||
input logic ENVCFG_PBMTE, // Page-based memory types enabled
|
||||
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
|
||||
input logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
|
||||
input logic ReadAccess, WriteAccess,
|
||||
input logic DisableTranslation,
|
||||
input logic TLBFlush, // Invalidate all TLB entries
|
||||
input logic TLBFlush, // Invalidate all TLB entries
|
||||
input logic [11:0] PTEAccessBits,
|
||||
input logic CAMHit,
|
||||
input logic Misaligned,
|
||||
|
|
@ -114,50 +115,12 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
|
|||
end
|
||||
|
||||
// Determine wheter to update DA bits. With SVADU, it is done in hardware
|
||||
if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault;
|
||||
else assign UpdateDA = PreUpdateDA;
|
||||
assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
|
||||
|
||||
// Determine whether page fault occurs
|
||||
assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & ~P.SVADU_SUPPORTED);
|
||||
assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE));
|
||||
assign TLBPageFault = Translate & TLBHit & (PrePageFault | InvalidAccess);
|
||||
|
||||
/*
|
||||
// Check whether the access is allowed, page faulting if not.
|
||||
if (ITLB == 1) begin:itlb // Instruction TLB fault checking
|
||||
// User mode may only execute user mode pages, and supervisor mode may
|
||||
// only execute non-user mode pages.
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
|
||||
((EffectivePrivilegeMode == P.S_MODE) & PTE_U);
|
||||
assign CausePageFault = ImproperPrivilege | ~PTE_X | UpperBitsUnequal | BadPTE | BadPBMT | Misaligned | ~PTE_V | (~PTE_A & P.SVADU_SUPPORTED);
|
||||
assign TLBPageFault = Translate & TLBHit & CausePageFault;
|
||||
// Determine wheter to update DA bits
|
||||
if(P.SVADU_SUPPORTED) assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
|
||||
else assign UpdateDA = ~PTE_A;
|
||||
end else begin:dtlb // Data TLB fault checking
|
||||
logic InvalidRead, InvalidWrite;
|
||||
|
||||
// User mode may only load/store from user mode pages, and supervisor mode
|
||||
// may only access user mode pages when STATUS_SUM is low.
|
||||
assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
|
||||
((EffectivePrivilegeMode == P.S_MODE) & PTE_U & ~STATUS_SUM);
|
||||
// Check for read error. Reads are invalid when the page is not readable
|
||||
// (and executable pages are not readable) or when the page is neither
|
||||
// readable nor executable (and executable pages are readable).
|
||||
assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
|
||||
// Check for write error. Writes are invalid when the page's write bit is
|
||||
// low.
|
||||
assign InvalidWrite = WriteAccess & ~PTE_W;
|
||||
if(P.SVADU_SUPPORTED) begin : hptwwrites
|
||||
assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault;
|
||||
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); // *** update to match
|
||||
end else begin
|
||||
// Fault for software handling if access bit is off or writing a page with dirty bit off
|
||||
assign UpdateDA = ~PTE_A | WriteAccess & ~PTE_D;
|
||||
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpdateDA | UpperBitsUnequal | Misaligned | ~PTE_V));
|
||||
end
|
||||
end
|
||||
*/
|
||||
|
||||
assign TLBHit = CAMHit & TLBAccess;
|
||||
assign TLBMiss = ~CAMHit & TLBAccess & Translate ;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||
output logic [2:0] FRM_REGW,
|
||||
output logic [3:0] ENVCFG_CBE,
|
||||
output logic ENVCFG_PBMTE, // Page-based memory type enable
|
||||
output logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
//
|
||||
output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
|
||||
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
|
||||
|
|
@ -292,6 +293,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
|||
// Broadcast appropriate environment configuration based on privilege mode
|
||||
assign ENVCFG_STCE = MENVCFG_REGW[63]; // supervisor timer counter enable
|
||||
assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
|
||||
assign ENVCFG_HADE = MENVCFG_REGW[61]; // Hardware A/D Update enable
|
||||
assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 :
|
||||
(PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] :
|
||||
(MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);
|
||||
|
|
|
|||
|
|
@ -172,7 +172,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
assign MENVCFG_WriteValM = {
|
||||
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
|
||||
MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED,
|
||||
54'b0,
|
||||
MENVCFG_PreWriteValM[61] & P.SVADU_SUPPORTED,
|
||||
53'b0,
|
||||
MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED,
|
||||
MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
|
||||
3'b0,
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
|||
output logic [2:0] FRM_REGW, // FPU rounding mode
|
||||
output logic [3:0] ENVCFG_CBE, // Cache block operation enables
|
||||
output logic ENVCFG_PBMTE, // Page-based memory type enable
|
||||
output logic ENVCFG_HADE, // HPTW A/D Update enable
|
||||
// PC logic output in privileged unit
|
||||
output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
|
||||
// control outputs
|
||||
|
|
@ -138,7 +139,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
|||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
|
||||
.MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
|
||||
.SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE,
|
||||
.SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE,
|
||||
.CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
|
||||
|
||||
// pipeline early-arriving trap sources
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
|||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic SquashSCW;
|
||||
logic MDUActiveE; // Mul/Div instruction being executed
|
||||
logic ENVCFG_HADE; // HPTW A/D Update enable
|
||||
logic ENVCFG_PBMTE; // Page-based memory type enable
|
||||
logic [3:0] ENVCFG_CBE; // Cache Block operation enables
|
||||
logic [3:0] CMOpM; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
|
||||
|
|
@ -185,7 +186,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
|||
.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
|
||||
// mmu management
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
||||
.STATUS_MPP, .ENVCFG_PBMTE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
|
||||
.STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_HADE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
|
||||
// pmp/pma (inside mmu) signals.
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF);
|
||||
|
||||
|
|
@ -234,6 +235,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
|||
.STATUS_MPRV, // from csr
|
||||
.STATUS_MPP, // from csr
|
||||
.ENVCFG_PBMTE, // from csr
|
||||
.ENVCFG_HADE, // from csr
|
||||
.sfencevmaM, // connects to privilege
|
||||
.DCacheStallM, // connects to privilege
|
||||
.LoadPageFaultM, // connects to privilege
|
||||
|
|
@ -296,7 +298,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
|||
.PrivilegeModeW, .SATP_REGW,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
|
||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
|
||||
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
|
||||
end else begin
|
||||
assign CSRReadValW = 0;
|
||||
assign UnalignedPCNextF = PC2NextF;
|
||||
|
|
|
|||
|
|
@ -63,6 +63,11 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
|
|||
assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP requires DCACHE_SUPPORTED");
|
||||
assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVPBMT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $error("SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
|
||||
assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $error("ZCB requires M and ZBB (and also ZBA for RV64)");
|
||||
assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $error("C and ZCA/ZCD/ZCF cannot simultaneously be supported");
|
||||
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $error("ZCF or ZCD requires ZCA");
|
||||
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $error("ZCF requires F");
|
||||
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $error("ZCD requires D");
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
|||
logic StallF, StallD;
|
||||
logic STATUS_SXL, STATUS_UXL;
|
||||
logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
|
||||
logic [P.XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
|
||||
logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
|
||||
logic InstrValidM, InstrValidW;
|
||||
logic StallE, StallM, StallW;
|
||||
logic FlushD, FlushE, FlushM, FlushW;
|
||||
|
|
@ -259,10 +259,10 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
|
|||
assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
|
||||
|
||||
// pipeline to writeback stage
|
||||
flopenrc #(P.XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
|
||||
flopenrc #(P.XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
||||
flopenrc #(P.XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
|
||||
flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
|
||||
flopenrc #(32) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
|
||||
flopenrc #(32) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
||||
flopenrc #(32) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
|
||||
flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
|
||||
flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
|
||||
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
|
||||
flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
|
||||
|
|
|
|||
|
|
@ -1000,7 +1000,7 @@ module testbenchfp;
|
|||
endmodule
|
||||
|
||||
|
||||
module readvectors (
|
||||
module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk,
|
||||
input logic [P.FLEN*4+7:0] TestVector,
|
||||
input logic [P.FMTBITS-1:0] ModFmt,
|
||||
|
|
@ -1026,7 +1026,7 @@ module readvectors (
|
|||
);
|
||||
|
||||
localparam Q_LEN = 32'd128;
|
||||
`include "parameter-defs.vh"
|
||||
//`include "parameter-defs.vh"
|
||||
|
||||
logic XEn;
|
||||
logic YEn;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,8 @@
|
|||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
`include "config.vh"
|
||||
`include "BranchPredictorType.vh"
|
||||
|
||||
// This is set from the command line script
|
||||
// `define USE_IMPERAS_DV
|
||||
|
|
@ -33,6 +34,8 @@
|
|||
`include "idv/idv.svh"
|
||||
`endif
|
||||
|
||||
import cvw::*;
|
||||
|
||||
`define DEBUG_TRACE 0
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
|
|
@ -61,8 +64,7 @@ module testbench;
|
|||
`endif
|
||||
|
||||
|
||||
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
|
||||
|
||||
|
|
@ -96,40 +98,40 @@ module testbench;
|
|||
integer TokenIndex``STAGE; \
|
||||
integer MarkerIndex``STAGE; \
|
||||
integer NumCSR``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedPC``STAGE; \
|
||||
logic [P.XLEN-1:0] ExpectedPC``STAGE; \
|
||||
logic [31:0] ExpectedInstr``STAGE; \
|
||||
string text``STAGE; \
|
||||
string MemOp``STAGE; \
|
||||
string RegWrite``STAGE; \
|
||||
integer ExpectedRegAdr``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
|
||||
logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
||||
logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \
|
||||
logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
|
||||
string ExpectedCSRArray``STAGE[10:0]; \
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
|
||||
logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(E)
|
||||
`DECLARE_TRACE_SCANNER_SIGNALS(M)
|
||||
// M-stage expected values
|
||||
logic checkInstrM;
|
||||
integer MIPexpected, SIPexpected;
|
||||
string name;
|
||||
logic [`AHBW-1:0] readDataExpected;
|
||||
logic [P.AHBW-1:0] readDataExpected;
|
||||
// W-stage expected values
|
||||
logic checkInstrW;
|
||||
logic [`XLEN-1:0] ExpectedPCW;
|
||||
logic [P.XLEN-1:0] ExpectedPCW;
|
||||
logic [31:0] ExpectedInstrW;
|
||||
string textW;
|
||||
string RegWriteW;
|
||||
integer ExpectedRegAdrW;
|
||||
logic [`XLEN-1:0] ExpectedRegValueW;
|
||||
logic [P.XLEN-1:0] ExpectedRegValueW;
|
||||
string MemOpW;
|
||||
logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
|
||||
logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
|
||||
integer NumCSRW;
|
||||
string ExpectedCSRArrayW[10:0];
|
||||
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
||||
logic [`XLEN-1:0] ExpectedIntType;
|
||||
logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0];
|
||||
logic [P.XLEN-1:0] ExpectedIntType;
|
||||
integer NumCSRWIndex;
|
||||
integer NumCSRPostWIndex;
|
||||
logic [`XLEN-1:0] InstrCountW;
|
||||
logic [P.XLEN-1:0] InstrCountW;
|
||||
// ========== Interrupt parsing & spoofing ==========
|
||||
string interrupt;
|
||||
string interruptLine;
|
||||
|
|
@ -143,7 +145,7 @@ module testbench;
|
|||
string interruptDesc;
|
||||
integer NextMIPexpected, NextSIPexpected;
|
||||
integer NextMepcExpected;
|
||||
logic [`XLEN-1:0] AttemptedInstructionCount;
|
||||
logic [P.XLEN-1:0] AttemptedInstructionCount;
|
||||
// ========== Misc Aliases ==========
|
||||
`define RF dut.core.ieu.dp.regf.rf
|
||||
`define PC dut.core.ifu.pcreg.q
|
||||
|
|
@ -168,7 +170,7 @@ module testbench;
|
|||
`define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q
|
||||
`define MTVEC `CSR_BASE.csrm.MTVECreg.q
|
||||
`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
|
||||
`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
|
||||
`define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q
|
||||
`define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2]
|
||||
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
|
||||
`define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW
|
||||
|
|
@ -249,14 +251,14 @@ module testbench;
|
|||
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
|
||||
always begin clk <= 1; # 5; clk <= 0; # 5; end
|
||||
// Wally Interface
|
||||
logic [`AHBW-1:0] HRDATAEXT;
|
||||
logic [P.AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic HCLK, HRESETn;
|
||||
logic HREADY;
|
||||
logic HSELEXT;
|
||||
logic [`PA_BITS-1:0] HADDR;
|
||||
logic [`AHBW-1:0] HWDATA;
|
||||
logic [`XLEN/8-1:0] HWSTRB;
|
||||
logic [P.PA_BITS-1:0] HADDR;
|
||||
logic [P.AHBW-1:0] HWDATA;
|
||||
logic [P.XLEN/8-1:0] HWSTRB;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
|
|
@ -273,10 +275,13 @@ module testbench;
|
|||
logic SDCCmdOut;
|
||||
logic SDCCmdOE;
|
||||
logic [3:0] SDCDatIn;
|
||||
logic SDCIntr;
|
||||
|
||||
|
||||
// Hardwire UART, GPIO pins
|
||||
assign GPIOPinsIn = 0;
|
||||
assign GPIOIN = 0;
|
||||
assign UARTSin = 1;
|
||||
assign SDCIntr = 0;
|
||||
|
||||
|
||||
|
||||
|
|
@ -284,8 +289,8 @@ module testbench;
|
|||
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
|
||||
rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
|
||||
wallyTracer wallyTracer(rvvi);
|
||||
rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
|
||||
wallyTracer #(P) wallyTracer(rvvi);
|
||||
|
||||
trace2log idv_trace2log(rvvi);
|
||||
// trace2cov idv_trace2cov(rvvi);
|
||||
|
|
@ -346,23 +351,23 @@ module testbench;
|
|||
// Privileges for PMA are set in the imperas.ic
|
||||
// volatile (IO) regions are defined here
|
||||
// only real ROM/RAM areas are BOOTROM and UNCORE_RAM
|
||||
if (`CLINT_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
|
||||
if (P.CLINT_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
|
||||
end
|
||||
if (`GPIO_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
|
||||
if (P.GPIO_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
|
||||
end
|
||||
if (`UART_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
|
||||
if (P.UART_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
|
||||
end
|
||||
if (`PLIC_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));
|
||||
if (P.PLIC_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
|
||||
end
|
||||
if (`SDC_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
|
||||
if (P.SDC_SUPPORTED) begin
|
||||
void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
|
||||
end
|
||||
|
||||
if(`XLEN==32) begin
|
||||
if(P.XLEN==32) begin
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
|
||||
void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
|
||||
|
|
@ -429,28 +434,28 @@ module testbench;
|
|||
|
||||
|
||||
// Wally
|
||||
wallypipelinedsoc dut(.clk, .reset, .reset_ext,
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
|
||||
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
|
||||
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK,
|
||||
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout,
|
||||
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
|
||||
.SDCIntr);
|
||||
|
||||
// W-stage hardware not needed by Wally itself
|
||||
parameter nop = 'h13;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
logic [P.XLEN-1:0] PCW;
|
||||
logic [31:0] InstrW;
|
||||
logic InstrValidW;
|
||||
logic [`XLEN-1:0] IEUAdrW, WriteDataW;
|
||||
logic [P.XLEN-1:0] IEUAdrW, WriteDataW;
|
||||
logic TrapW;
|
||||
`define FLUSHW dut.core.FlushW
|
||||
`define STALLW dut.core.StallW
|
||||
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
|
||||
flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
|
||||
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
|
||||
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
|
||||
flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
|
||||
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
|
||||
flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
|
||||
flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
|
||||
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
|
||||
|
||||
|
||||
|
|
@ -526,29 +531,29 @@ module testbench;
|
|||
end
|
||||
|
||||
genvar i;
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
|
||||
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [P.XLEN-1:0],31,1);
|
||||
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0);
|
||||
`INIT_CHECKPOINT_VAL(PC, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEDELEG, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIDELEG, [P.XLEN-1:0]);
|
||||
if(!NO_SPOOFING) begin
|
||||
`INIT_CHECKPOINT_VAL(MIE, [11:0]);
|
||||
`INIT_CHECKPOINT_VAL(MIP, [11:0]);
|
||||
end
|
||||
`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SEPC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MCAUSE, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SCAUSE, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MEPC, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SEPC, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
|
||||
`INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
|
||||
`INIT_CHECKPOINT_VAL(MSCRATCH, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SSCRATCH, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MTVEC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MSCRATCH, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SSCRATCH, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(MTVEC, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(STVEC, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(SATP, [P.XLEN-1:0]);
|
||||
`INIT_CHECKPOINT_VAL(PRIV, [1:0]);
|
||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0);
|
||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1);
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0);
|
||||
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
|
||||
// UART checkpointing does not cover entire UART state
|
||||
// Many UART registers are difficult to initialize because under the hood
|
||||
|
|
@ -563,8 +568,8 @@ module testbench;
|
|||
`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
|
||||
// xSTATUS need to be handled manually because the most upstream signals
|
||||
// are made of individual bits, not registers
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0);
|
||||
`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0);
|
||||
|
||||
// ========== INITIALIZATION ==========
|
||||
initial begin
|
||||
|
|
@ -620,7 +625,7 @@ module testbench;
|
|||
force {`STATUS_SPIE} = initMSTATUS[0][5];
|
||||
force {`STATUS_MIE} = initMSTATUS[0][3];
|
||||
force {`STATUS_SIE} = initMSTATUS[0][1];
|
||||
force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
|
||||
force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
|
||||
force `INSTRET = CHECKPOINT;
|
||||
while (reset!==1) #1;
|
||||
while (reset!==0) #1;
|
||||
|
|
@ -873,7 +878,7 @@ module testbench;
|
|||
"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
|
||||
"stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
|
||||
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
|
||||
"senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
|
||||
// "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // *** fix me
|
||||
"mip": begin
|
||||
`checkCSR(`CSR_BASE.csrm.MIP_REGW)
|
||||
if(!NO_SPOOFING) begin
|
||||
|
|
@ -953,7 +958,7 @@ module testbench;
|
|||
//////////////////////////////// Extra Features ///////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Function Tracking
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
FunctionName #(P) FunctionName(.reset(reset),
|
||||
.clk(clk),
|
||||
.ProgramAddrMapFile(ProgramAddrMapFile),
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
|
|
@ -978,12 +983,12 @@ module testbench;
|
|||
* explanation of the below algorithm.
|
||||
*/
|
||||
logic SvMode, PTE_R, PTE_X;
|
||||
logic [`XLEN-1:0] SATP, PTE;
|
||||
logic [P.XLEN-1:0] SATP, PTE;
|
||||
logic [55:0] BaseAdr, PAdr;
|
||||
logic [8:0] VPN [2:0];
|
||||
logic [11:0] Offset;
|
||||
function logic [`XLEN-1:0] adrTranslator(
|
||||
input logic [`XLEN-1:0] adrIn);
|
||||
function logic [P.XLEN-1:0] adrTranslator(
|
||||
input logic [P.XLEN-1:0] adrIn);
|
||||
begin
|
||||
int i;
|
||||
// Grab the SATP register from privileged unit
|
||||
|
|
@ -997,7 +1002,7 @@ module testbench;
|
|||
SvMode = SATP[63];
|
||||
// Only perform translation if translation is on and the processor is not
|
||||
// in machine mode
|
||||
if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin
|
||||
if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin
|
||||
BaseAdr = SATP[43:0] << 12;
|
||||
for (i = 2; i >= 0; i--) begin
|
||||
PAdr = BaseAdr + (VPN[i] << 3);
|
||||
|
|
|
|||
|
|
@ -35,8 +35,15 @@ beef0110
|
|||
0000000f
|
||||
0000000c
|
||||
00000bad
|
||||
beef0770 # Test 11.3.1.3.5: check successful read/write when A=0 and SVADU=1
|
||||
beef0aa0 # Test 11.3.1.3.6: check successful read/write when D=0 and SVADU=1
|
||||
0000000f # Test 11.3.1.3.6(a) page fault on write when A = 0
|
||||
0000000d # Test 11.3.1.3.6(a) page fault on read when A = 0
|
||||
00000bad
|
||||
0000000f # Test 11.3.1.3.7(a) page fault on write when D = 0
|
||||
deadbeef # Test 11.3.1.3.7(a) successful read when D = 0
|
||||
00000009 # call from going to m mode from s mode
|
||||
0000000b # ecall from going to S mode from m mode
|
||||
beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.HADE=1
|
||||
beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and MENVCFG.HADE=1
|
||||
beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping
|
||||
00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
|
||||
00000000 # previous value of mprv before being set
|
||||
|
|
|
|||
|
|
@ -1324,6 +1324,18 @@ write_mideleg:
|
|||
csrw mideleg, t4
|
||||
j test_loop
|
||||
|
||||
write_menvcfg:
|
||||
// writes the value in t4 to the menvcfg register
|
||||
// Doesn't log anything
|
||||
csrw menvcfg, t4
|
||||
j test_loop
|
||||
|
||||
write_menvcfgh:
|
||||
// writes the value in t4 to the menvcfgh register
|
||||
// Doesn't log anything
|
||||
csrw menvcfgh, t4
|
||||
j test_loop
|
||||
|
||||
executable_test:
|
||||
// Execute the code at the address in t3, returning the value in t2.
|
||||
// Assumes the code modifies t2, to become the value stored in t4 for this test.
|
||||
|
|
|
|||
|
|
@ -157,13 +157,28 @@ test_cases:
|
|||
.4byte 0xBFFDE0, 0xbad, executable_test # instr page fault when X=0
|
||||
|
||||
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
|
||||
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
|
||||
|
||||
# test 11.3.1.3.6(a) Accessed flag == 0
|
||||
.4byte 0x3020, 0xBEEF0770, write32_test # store page fault when A=0
|
||||
.4byte 0x3020, 0xBEEF0770, read32_test # load page fault when A=0
|
||||
|
||||
# test 11.3.1.3.7(a) Dirty flag == 0
|
||||
.4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0
|
||||
.4byte 0x4658, 0xDEADBEEF, read32_test # read success when D=0; default DEADBEEF value wasn't changed
|
||||
|
||||
# Now set HADE bit
|
||||
.4byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
|
||||
.4byte 0x0, 0x20000000, write_menvcfgh # set menvcfg.HADE = 1
|
||||
.4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
|
||||
|
||||
# Since SVADU is 1, there are no faults when A/D=0
|
||||
|
||||
# test 11.3.1.3.6 Accessed flag == 0
|
||||
# test 11.3.1.3.6(b) Accessed flag == 0
|
||||
.4byte 0x3020, 0xBEEF0770, write32_test # Write success when A=0 and SVADU is enabled
|
||||
.4byte 0x3020, 0xBEEF0770, read32_test # Read success when A=0 and SVADU is enabled
|
||||
|
||||
# test 11.3.1.3.7 Dirty flag == 0
|
||||
# test 11.3.1.3.7(b) Dirty flag == 0
|
||||
.4byte 0x4658, 0xBEEF0AA0, write32_test # write successs when D=0 and SVADU is enabled
|
||||
.4byte 0x4658, 0xBEEF0AA0, read32_test # read success when D=0
|
||||
|
||||
|
|
|
|||
|
|
@ -436,6 +436,14 @@ ffffffff
|
|||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
0bad0bad # controls
|
||||
0bad0bad
|
||||
0bad0bad
|
||||
|
|
|
|||
|
|
@ -84,9 +84,23 @@ beef0110 # Test 11.3.1.3.4: read test success
|
|||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and SVADU=1
|
||||
0000000f # Test 11.3.1.3.6(a): write test with page fault
|
||||
00000000
|
||||
0000000d # read test with page fault
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
0000000f # Test 11.3.1.3.7(a): write test with page fault
|
||||
00000000
|
||||
deadbeef # read test success but nothing was written so read back default
|
||||
deadbeef
|
||||
00000009 # ecall from going to M mode from S mode
|
||||
00000000
|
||||
0000000B # ecall from going to S mode from M mode
|
||||
00000000
|
||||
beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1
|
||||
0990dead
|
||||
beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and SVADU=1
|
||||
beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
|
||||
0440dead
|
||||
0000000d # Test 11.3.1.3.8: read test with page fault for nonzero reserved bit
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -92,9 +92,23 @@ beef0110 # Test 11.3.1.3.4: read test success
|
|||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
beef0770 # Test 11.3.1.3.5: check successful read/write when A=0 and SVADU=1
|
||||
0000000f # Test 11.3.1.3.6(a): write test with page fault
|
||||
00000000
|
||||
0000000d # read test with page fault
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
0000000f # Test 11.3.1.3.7(a): write test with page fault
|
||||
00000000
|
||||
deadbeef # read test success but get deadbeef because nothing was written
|
||||
deadbeef
|
||||
00000009 # ecall from going to M mode from S mode
|
||||
00000000
|
||||
0000000B # ecall from going to S mode from M mode
|
||||
00000000
|
||||
beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1
|
||||
0990dead
|
||||
beef0aa0 # Test 11.3.1.3.6: check successful read/write when D=0 and SVADU=1
|
||||
beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
|
||||
0440dead
|
||||
beef0000 # Test 11.3.1.4.1: read test success on new page table mapping
|
||||
0000dead
|
||||
|
|
|
|||
|
|
@ -125,6 +125,164 @@ CBOMTest_inval_step4_all:
|
|||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
################################################################################
|
||||
# INVALIDATE all ways D$
|
||||
################################################################################
|
||||
|
||||
# theory of operation
|
||||
# 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
|
||||
# 2. Then verify the second region has the same data
|
||||
# 3. Invalidate the second region
|
||||
# 4. Verify the second region has the original invalid data
|
||||
# DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated
|
||||
# but the next should have the copied data.
|
||||
|
||||
# step 0 copy deadbeef to remote regions spaced 4KiB apart
|
||||
CBOMTest_way_inval_4096_step0:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+4096
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_8192_step0:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+8192
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_12288_step0:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+12288
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_16384_step0:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+16384
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
# one of the following will force an eviction of each of the previous
|
||||
CBOMTest_way_inval_20480_step0: # this one should force eviction of _4096
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+20480
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_24576_step0: # this one should force eviction of _4096
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+24576
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_28672_step0: # this one should force eviction of _4096
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+28672
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
CBOMTest_way_inval_32768_step0: # this one should force eviction of _4096
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+32768
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
|
||||
# step 1
|
||||
CBOMTest_way_inval_4096_step1:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+4096
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
|
||||
CBOMTest_way_inval_8192_step1:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+8192
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
|
||||
CBOMTest_way_inval_12288_step1:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+12288
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
|
||||
CBOMTest_way_inval_16384_step1:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+16384
|
||||
li a2, 8
|
||||
jal ra, memcpy8
|
||||
|
||||
# don't want to ca use a write back for the previous writes since we want to invalidate them
|
||||
|
||||
# step 2
|
||||
CBOMTest_way_inval_4096_step2:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+4096
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_8192_step2:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+8192
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_12288_step2:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+12288
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_16384_step2:
|
||||
la a0, SourceData
|
||||
la a1, Destination1+16384
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_step3_all_again:
|
||||
la a1, Destination1+4096
|
||||
la a2, Destination1+8192
|
||||
la a3, Destination1+12288
|
||||
la a4, Destination1+16384
|
||||
cbo.inval (a1)
|
||||
cbo.inval (a2)
|
||||
cbo.inval (a3)
|
||||
cbo.inval (a4)
|
||||
|
||||
# step 4 All should be invalid
|
||||
CBOMTest_way_inval_4096_step4_all:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+4096
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_8192_step4_all:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+8192
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_12288_step4_all:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+12288
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
CBOMTest_way_inval_16384_step4_all:
|
||||
la a0, DeadBeafData1
|
||||
la a1, Destination1+16384
|
||||
li a2, 8
|
||||
jal ra, memcmp8
|
||||
sd a0, 0(s0) # should be -1
|
||||
addi s0, s0, 8
|
||||
|
||||
################################################################################
|
||||
# Clean D$
|
||||
################################################################################
|
||||
|
|
@ -151,7 +309,7 @@ CBOMTest_clean_step1:
|
|||
|
||||
# step 2
|
||||
CBOMTest_clean_step2:
|
||||
la a0, SourceData
|
||||
la a0, SourceData
|
||||
la a1, Destination2
|
||||
li a2, 64
|
||||
jal ra, memcmp8
|
||||
|
|
@ -466,7 +624,7 @@ Destination2:
|
|||
Destination3:
|
||||
.fill 128, 4, 0xdeadbeef
|
||||
signature:
|
||||
.fill 32, 4, 0x0bad0bad
|
||||
.fill 40, 4, 0x0bad0bad
|
||||
|
||||
RVMODEL_DATA_END
|
||||
|
||||
|
|
|
|||
|
|
@ -194,13 +194,29 @@ test_cases:
|
|||
# *** fetches on pages with X = 1 already tested in 11.3.1.3.1
|
||||
.8byte 0x5AA0, 0x1, executable_test # instr page fault when X=0
|
||||
|
||||
|
||||
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
|
||||
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
|
||||
|
||||
# test 11.3.1.3.6(a) Accessed flag == 0
|
||||
.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0
|
||||
.8byte 0x3AB8, 0x0990DEADBEEF0990, read64_test# load page fault when A=0
|
||||
|
||||
# test 11.3.1.3.7(a) Dirty flag == 0
|
||||
.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0
|
||||
.8byte 0x4AA0, 0xDEADBEEFDEADBEEF, read64_test# read success when D=0
|
||||
|
||||
# Now set HADE bit
|
||||
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
|
||||
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1
|
||||
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
|
||||
|
||||
# Since SVADU is 1, there are no faults when A/D=0
|
||||
# test 11.3.1.3.6 Accessed flag == 0
|
||||
# test 11.3.1.3.6(b) Accessed flag == 0
|
||||
.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test # Write success when A=0 and SVADU is enabled
|
||||
.8byte 0x36D0, 0x0990DEADBEEF0770, read64_test # Read success when A=0 and SVADU is enabled
|
||||
|
||||
# test 11.3.1.3.7 Dirty flag == 0
|
||||
# test 11.3.1.3.7(b) Dirty flag == 0
|
||||
.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test # Write success when D=0 and SVADU is enabled
|
||||
.8byte 0x4658, 0x0440DEADBEEF0AA0, read64_test # read success when D=0
|
||||
|
||||
|
|
|
|||
|
|
@ -187,7 +187,23 @@ test_cases:
|
|||
# executes on pages with X = 1 already tested in 11.3.1.3.1
|
||||
.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0
|
||||
|
||||
|
||||
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
|
||||
# Initially test with HADE = 0, so needing to set A/D bits triggers page fault
|
||||
|
||||
# test 11.3.1.3.6(a) Accessed flag == 0
|
||||
.8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # store page fault when A=0
|
||||
.8byte 0x802036D0, 0x0990DEADBEEF0990, read64_test # load page fault when A=0
|
||||
|
||||
# test 11.3.1.3.7(a) Dirty flag == 0
|
||||
.8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # store page fault when D=0
|
||||
.8byte 0x80204658, 0xDEADBEEFDEADBEEF, read64_test # read success when D=0
|
||||
|
||||
# Now set HADE bit
|
||||
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
|
||||
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1
|
||||
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
|
||||
|
||||
# Since SVADU is 1, there are no faults when A/D=0
|
||||
|
||||
# test 11.3.1.3.6 Accessed flag == 0
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue