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Merge pull request #1427 from georgiatai/devcvw

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Changes in wally, sail, and spike config to support vector verification
This commit is contained in:
David Harris 2025-05-27 08:40:43 -07:00 • committed by GitHub
commit 1c0fb856e7
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8 changed files with 21 additions and 8 deletions
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2
tests/riscof/sail_cSim/riscof_sail_cSim.py
View file

@ -63,6 +63,8 @@ class sail_cSim(pluginTemplate):
self.isa += 'd'
if "Q" in ispec["ISA"]:
self.isa += 'q'
if "V" in ispec["ISA"]:
self.isa += 'v'
objdump = "riscv64-unknown-elf-objdump"
if shutil.which(objdump) is None:
logger.error(objdump+": executable not found. Please check environment setup.")

2
tests/riscof/sail_cSim/rv32gc.json
View file

@ -56,7 +56,7 @@
"supported": true
},
"V": {
"supported": false,
"supported": true,
"vlen_exp": 9,
"elen_exp": 6,
"vl_use_ceil": false

2
tests/riscof/sail_cSim/rv64gc.json
View file

@ -56,7 +56,7 @@
"supported": true
},
"V": {
"supported": false,
"supported": true,
"vlen_exp": 9,
"elen_exp": 6,
"vl_use_ceil": false

2
tests/riscof/spike/riscof_spike.py
View file

@ -103,6 +103,8 @@ class spike(pluginTemplate):
self.isa += 'q'
if "C" in ispec["ISA"]:
self.isa += 'c'
if "V" in ispec["ISA"]:
self.isa += 'v'
if "Zicsr" in ispec["ISA"]:
self.isa += '_Zicsr'
if "Zicond" in ispec["ISA"]:

7
tests/riscof/spike/spike_rv32gc_isa.yaml
View file

@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x4014112D
reset-val: 0x4034112D
rv32:
accessible: true
mxl:
@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x014112D, 0x0000000]
- extensions[25:0] bitmask [0x034112D, 0x0000000]
wr_illegal:
- Unchanged
PMP:
@ -31,3 +31,4 @@ hart0:
pmp-grain: 0
pmp-count: 16
pmp-writable: 12

6
tests/riscof/spike/spike_rv64gc_isa.yaml
View file

@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV64IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x800000000014112D
reset-val: 0x800000000034112D
rv32:
accessible: false
rv64:
@ -25,7 +25,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x015112D, 0x0000000]
- extensions[25:0] bitmask [0x035112D, 0x0000000]
wr_illegal:
- Unchanged
PMP: