mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-06-27 17:01:20 -04:00
WIP: Fetch buffer PCF logic
Increment PCF one final time when fetch buffer goes high. Currently breaks sims because it increments twice for some reason right now. Co-authored-by: Jordan Carlin <jcarlin@hmc.edu> Co-authered-by: Corey Hickson <chickson@hmc.edu>
This commit is contained in:
Vikram Krishna
parent
fea1f6ad86
commit
1e3d39ba3c
6 changed files with 66 additions and 29 deletions
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@ -212,7 +212,7 @@ localparam PLIC_SPI_ID = 32'd6;
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localparam PLIC_SDC_ID = 32'd9;
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// Branch prediction
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localparam logic BPRED_SUPPORTED = 1;
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localparam logic BPRED_SUPPORTED = 0;
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localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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localparam BPRED_SIZE = 32'd10;
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localparam BPRED_NUM_LHR = 32'd6;
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@ -18,6 +18,7 @@ add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FetchBufferStallF
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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@ -42,29 +43,57 @@ add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbe
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -expand -group HDU -expand -group Stall /testbench/dut/core/ifu/StallFBF
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add wave -noupdate -expand -group HDU -expand -group Stall /testbench/dut/core/ifu/NoStallPCF
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
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add wave -noupdate /testbench/dut/core/StallW
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add wave -noupdate -expand -label {Contributors: StallW} -group {Contributors: sim:/testbench/dut/core/StallW} /testbench/dut/core/hzu/StallWCause
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add wave -noupdate /testbench/dut/core/hzu/StallWCause
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add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/ExternalStall
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add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/FlushDCause
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add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/FlushWCause
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add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/IFUStallF
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add wave -noupdate -expand -label {Contributors: StallWCause} -group {Contributors: sim:/testbench/dut/core/hzu/StallWCause} /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate /testbench/dut/core/hzu/IFUStallF
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add wave -noupdate -expand -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/IFUCacheBusStallF
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add wave -noupdate -expand -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/SelSpillNextF
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add wave -noupdate -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/IFUCacheBusStallF
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add wave -noupdate -label {Contributors: IFUStallF} -group {Contributors: sim:/testbench/dut/core/hzu/IFUStallF} /testbench/dut/core/ifu/SelSpillNextF
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add wave -noupdate /testbench/dut/core/ifu/IFUCacheBusStallF
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add wave -noupdate -expand -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/BusStall
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add wave -noupdate -expand -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/BusStall
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add wave -noupdate -label {Contributors: IFUCacheBusStallF} -group {Contributors: sim:/testbench/dut/core/ifu/IFUCacheBusStallF} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ce}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/addr}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/addrd}
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add wave -noupdate -group {instruction pipeline} -radix decimal {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheSetTag}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/PAdr}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ReadTag}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/InvalidateCacheDelay}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidWay}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/HitWay}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/FlushCache}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelVictim}
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add wave -noupdate -group {instruction pipeline} {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWay}
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add wave -noupdate -group {instruction pipeline} -expand /testbench/dut/core/ifu/bus/icache/icache/ReadDataLineWay
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/ReadDataLineCache
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/SelFetchBuffer
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/WordOffsetAddr
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/icache/ReadDataLine
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/ICacheInstrF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/SelIROM
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/CacheableF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/Spill/spill/InstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/Spill/spill/SelSpillF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/CompressedF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCPlus2or4F
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/BPWrongE
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PC1NextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/CSRWriteFenceM
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PC2NextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/RetM
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/TrapM
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/UnalignedPCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
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@ -394,8 +423,8 @@ add wave -noupdate -expand -group FetchBuffer -label {PCFB[2]} {/testbench/dut/c
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add wave -noupdate -expand -group FetchBuffer -label {PCFB[1]} {/testbench/dut/core/ifu/fetchbuffer/PCFetchBuffer/fbEntries[1]/q}
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add wave -noupdate -expand -group FetchBuffer -label {PCFB[0]} {/testbench/dut/core/ifu/fetchbuffer/PCFetchBuffer/fbEntries[0]/q}
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{potential optimization} {2680 ns} 1} {{WHY IFU STALL?} {7010 ns} 1}
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quietly wave cursor active 1
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WaveRestoreCursors {{potential optimization} {2680 ns} 1} {{WHY IFU STALL?} {7010 ns} 1} {{Cursor 3} {7010 ns} 1} {{Cursor 4} {2518 ns} 0}
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quietly wave cursor active 4
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 194
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configure wave -justifyvalue left
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@ -410,4 +439,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {2630 ns} {2730 ns}
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WaveRestoreZoom {2468 ns} {2577 ns}
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@ -43,7 +43,7 @@ module hazard (
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input logic wfiM,
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IntPendingM,
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// Stall & flush outputs
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output logic StallF,
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output logic StallF, StallFBF,
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StallD,
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StallE,
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StallM,
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@ -97,14 +97,17 @@ module hazard (
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// The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.
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// The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
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// A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
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assign StallFCause = FetchBufferStallF | (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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assign StallFBF = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
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assign StallFCause = StallFBF | FetchBufferStallF;
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assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause; // TODO: add stall if empty fetch buffer
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assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
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assign StallMCause = WFIStallM & ~FlushMCause;
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// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
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// assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
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// Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
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assign StallWCause = (IFUStallF & ~FlushDCause) |(LSUStallM & ~FlushWCause) | ExternalStall;
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | ExternalStall;
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// Stall each stage for cause or if the next stage is stalled
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// coverage off: StallFCause is always 0
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@ -28,7 +28,7 @@
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module ifu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic StallF, StallD, StallE, StallM, StallW, StallFBF,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
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// Command from CPU
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@ -303,9 +303,12 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
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assign GatedStallD = StallD & ~SelSpillNextF;
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logic NoStallPCF;
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if (P.FETCHBUFFER_ENTRIES != 0) begin : fetchbuffer
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fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .nop, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF);
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logic PCFetchBufferStallD;
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logic PCFetchBufferStallD, FetchBufferStallFDelay;
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flop #(1) flop1 (clk, FetchBufferStallF, FetchBufferStallFDelay);
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assign NoStallPCF = ~FetchBufferStallFDelay & FetchBufferStallF;
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fetchbuffer #(P, P.XLEN) PCFetchBuffer(.clk, .reset, .StallF, .StallD, .FlushD, .nop({{1'b1},{(P.XLEN-1){1'b0}}}), .WriteData(PCF), .ReadData(PCD), .FetchBufferStallF(PCFetchBufferStallD));
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end else begin
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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@ -323,7 +326,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
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mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
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flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
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logic PCEnable;
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assign PCEnable = NoStallPCF | ~StallF | reset;
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flopen #(P.XLEN) pcreg(clk, PCEnable, PCNextF, PCF); //* make this NoStallPCF
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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@ -48,7 +48,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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input logic ExternalStall
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);
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logic StallF, StallD, StallE, StallM, StallW;
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logic StallF, StallD, StallE, StallM, StallW, StallFBF;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, RetM;
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@ -175,7 +175,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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// instruction fetch unit: PC, branch prediction, instruction cache
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ifu #(P) ifu(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.StallF, .StallD, .StallE, .StallM, .StallW, .StallFBF, .FlushD, .FlushE, .FlushM, .FlushW,
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.InstrValidE, .InstrValidD,
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.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
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// Fetch
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@ -282,7 +282,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.DivBusyE, .FDivBusyE,
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.wfiM, .IntPendingM,
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// Stall & flush outputs
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.StallF, .StallD, .StallE, .StallM, .StallW, .StallFBF,
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.FlushD, .FlushE, .FlushM, .FlushW);
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// privileged unit
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@ -751,7 +751,7 @@ end
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.CMP_CSR (1)
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) idv_trace2api(rvvi);
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`include "RV_Assertions.sv"
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// `include "RV_Assertions.sv"
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string filename;
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initial begin
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