github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-24 13:57:07 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Added additional fsm to ILA.

Browse source
This commit is contained in:
Ross Thompson 2022-01-09 17:10:57 -06:00
parent 6eb2f37ce4
commit 26fb09c868
2 changed files with 5 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

14
fpga/constraints/debug2.xdc
View file

@ -574,26 +574,20 @@ connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe123]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]}
{wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]}
{wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]]
connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe124]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/CurrState ]]
connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/SpillSupport.CurrState[0] ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe125]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]}
{wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]}
{wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]]
connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe126]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]}
{wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]}
{wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]

2
pipelined/src/lsu/interlockfsm.sv
View file

@ -55,7 +55,7 @@ module interlockfsm
STATE_T5_ITLB_MISS,
STATE_T7_DITLB_MISS} statetype;
statetype InterlockCurrState, InterlockNextState;
(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState;
always_ff @(posedge clk)