Added extra core signal to mark_debug.txt. Modified wally.tcl

fpga/constraints/marked_debug.txt

@@ -30,6 +30,7 @@ wally/wallypipelinedcore.sv: logic           MemRWM
 wally/wallypipelinedcore.sv: logic                InstrValidM
 wally/wallypipelinedcore.sv: logic     WriteDataM
 wally/wallypipelinedcore.sv: logic     IEUAdrM
+wally/wallypipelinedcore.sv: logic   HRDATA
 ifu/spill.sv:    statetype CurrState
 ifu/ifu.sv: logic    				IFUStallF
 ifu/ifu.sv: logic     IFUHADDR

fpga/generator/wally.tcl

@@ -19,7 +19,7 @@ read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossb
 read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
 read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
 
-read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
+# read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
 read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
 read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v]
 read_verilog  {../src/fpgaTop.v}
@@ -47,6 +47,9 @@ synth_design -rtl -name rtl_1
 
 report_clocks -file reports/clocks.rpt
 
+# Temp
+set_param messaging.defaultLimit 100000
+
 # this does synthesis? wtf?
 launch_runs synth_1 -jobs 4