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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2025-05-28 06:01:43 -07:00
commit 34f8b8f3e7
12 changed files with 76 additions and 19 deletions
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6
tests/coverage/tlbmisc.S
View file

@ -64,10 +64,10 @@ main:
li t0, 0x80200000
jalr ra, t0 # jump to misaligned megapage
li t0, 0x7FFFFFFF80000000
jalr ra, t0 # jump to page with UpperBitsUnequal
li t0, 0x0000000080C00000
li t0, 0x8000000080C00000
jalr ra, t0
li t0, 0x000000080C00000
jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
# test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,

9
tests/riscof/Makefile
View file

@ -18,7 +18,13 @@ current_dir := $(shell pwd)
.PHONY: all riscv-arch-test wally-riscv-arch-test clean
all: riscv-arch-test wally-riscv-arch-test
riscv-arch-test: arch32e arch32 arch64
cvw-riscv-arch-test: cvw-arch32 cvw-arch64 # cvw-arch32e
cvw-riscv-arch-test: # cvw-arch32e
rm -rf $(cvw_arch_workdir)
rm -rf $(WALLY)/addins/cvw-arch-verif/work/*
$(MAKE) cvw-arch32
$(MAKE) cvw-arch64
wally-riscv-arch-test: wally32 wally64
# Generate config.ini files
@ -51,6 +57,7 @@ clean:
rm -rf $(wally_workdir)
rm -rf $(arch_workdir)
rm -rf $(cvw_arch_workdir)
rm -rf $(WALLY)/addins/cvw-arch-verif/work/*
$(work_dir) $(arch_workdir) $(wally_workdir) $(cvw_arch_workdir):
mkdir -p $@

2
tests/riscof/sail_cSim/riscof_sail_cSim.py
View file

@ -63,6 +63,8 @@ class sail_cSim(pluginTemplate):
self.isa += 'd'
if "Q" in ispec["ISA"]:
self.isa += 'q'
if "V" in ispec["ISA"]:
self.isa += 'v'
objdump = "riscv64-unknown-elf-objdump"
if shutil.which(objdump) is None:
logger.error(objdump+": executable not found. Please check environment setup.")

20
tests/riscof/sail_cSim/rv32gc.json
View file

@ -56,7 +56,7 @@
"supported": true
},
"V": {
"supported": false,
"supported": true,
"vlen_exp": 9,
"elen_exp": 6,
"vl_use_ceil": false
@ -82,6 +82,9 @@
"Zicntr": {
"supported": true
},
"Zicsr": {
"supported": true
},
"Zifencei": {
"supported": true
},
@ -103,6 +106,15 @@
"Zalrsc": {
"supported": false
},
"Zawrs": {
"supported": false,
"nto": {
"is_nop": false
},
"sto": {
"is_nop": false
}
},
"Zfa": {
"supported": true
},
@ -181,6 +193,9 @@
"Zvbc": {
"supported": false
},
"Zvkned": {
"supported": false
},
"Zvknha": {
"supported": false
},
@ -203,7 +218,8 @@
"supported": true
},
"Svbare": {
"supported": true
"supported": true,
"sfence_vma_illegal_if_svbare_only": true
},
"Sv32": {
"supported": true

20
tests/riscof/sail_cSim/rv64gc.json
View file

@ -56,7 +56,7 @@
"supported": true
},
"V": {
"supported": false,
"supported": true,
"vlen_exp": 9,
"elen_exp": 6,
"vl_use_ceil": false
@ -82,6 +82,9 @@
"Zicntr": {
"supported": true
},
"Zicsr": {
"supported": true
},
"Zifencei": {
"supported": true
},
@ -103,6 +106,15 @@
"Zalrsc": {
"supported": false
},
"Zawrs": {
"supported": false,
"nto": {
"is_nop": false
},
"sto": {
"is_nop": false
}
},
"Zfa": {
"supported": true
},
@ -181,6 +193,9 @@
"Zvbc": {
"supported": false
},
"Zvkned": {
"supported": false
},
"Zvknha": {
"supported": false
},
@ -203,7 +218,8 @@
"supported": true
},
"Svbare": {
"supported": true
"supported": true,
"sfence_vma_illegal_if_svbare_only": true
},
"Sv32": {
"supported": false

2
tests/riscof/spike/riscof_spike.py
View file

@ -103,6 +103,8 @@ class spike(pluginTemplate):
self.isa += 'q'
if "C" in ispec["ISA"]:
self.isa += 'c'
if "V" in ispec["ISA"]:
self.isa += 'v'
if "Zicsr" in ispec["ISA"]:
self.isa += '_Zicsr'
if "Zicond" in ispec["ISA"]:

7
tests/riscof/spike/spike_rv32gc_isa.yaml
View file

@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x4014112D
reset-val: 0x4034112D
rv32:
accessible: true
mxl:
@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x014112D, 0x0000000]
- extensions[25:0] bitmask [0x034112D, 0x0000000]
wr_illegal:
- Unchanged
PMP:
@ -31,3 +31,4 @@ hart0:
pmp-grain: 4
pmp-count: 16
pmp-writable: 12

6
tests/riscof/spike/spike_rv64gc_isa.yaml
View file

@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV64IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x800000000014112D
reset-val: 0x800000000034112D
rv32:
accessible: false
rv64:
@ -25,7 +25,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x015112D, 0x0000000]
- extensions[25:0] bitmask [0x035112D, 0x0000000]
wr_illegal:
- Unchanged
PMP: