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Added testing for every bit field in MIE, rather than just one

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Kip Macsai-Goren 2022-04-22 23:05:54 +00:00
parent 2cc6d3ddb4
commit 3e62a8f974
2 changed files with 19 additions and 1 deletions
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11
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S
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@ -33,10 +33,19 @@ li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// test 5.3.1.6 Interrupt enabling and priority tests
// testing with MIE bits set already tested in WALLY-trap
// note that none of these interrupts should be caught or handled.
jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
END_TESTS

9
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S
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@ -34,9 +34,18 @@ csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// testing with MIE bits set already tested in WALLY-trap
// note that none of these interrupts should be caught or handled.
jal cause_s_soft_interrupt
jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
END_TESTS