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Added comments to some files, added a+b = 0 detector to comparator.sv
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6 changed files with 18 additions and 3 deletions
2
.gitignore
vendored
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.gitignore
vendored
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@ -104,3 +104,5 @@ pipelined/config/rv64ic_noPriv
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pipelined/config/rv64ic_orig
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synthDC/Summary.csv
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pipelined/srt/exptestgen
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pipelined/srt/testgen
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pipelined/srt/qst2
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@ -237,6 +237,7 @@ module fpu (
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// select the result that may be written to the integer register - to IEU
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mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0],
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CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
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// *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok
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// E/M pipe registers
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@ -65,7 +65,7 @@ module hazard(
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assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
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// stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
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assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
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assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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assign StallMCause = wfiM & (~TrapM & ~IntPendingM);
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assign StallWCause = LSUStallM | IFUStallF;
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@ -30,6 +30,15 @@
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`include "wally-config.vh"
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module donedet #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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output logic eq);
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//assign eq = (a+b == 0); // gives good speed but 3x necessary area
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// See CMOS VLSI Design 4th Ed. p. 463 K = A+B for K = 0
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assign eq = ((a ^ b) == {a[WIDTH-2:0], 1'b0} | {b[WIDTH-2:0], 1'b0});
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endmodule
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module comparator_sub #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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output logic [2:0] flags);
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@ -1,7 +1,10 @@
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all: sqrttestgen testgen
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all: sqrttestgen testgen qst2
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sqrttestgen: sqrttestgen.c
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gcc sqrttestgen.c -lm -o sqrttestgen
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testgen: testgen.c
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gcc testgen.c -lm -o testgen
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qst2: qst2.c
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gcc qst2.c -lm -o qst2
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