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https://github.com/openhwgroup/cvw.git
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Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
This commit is contained in:
David Harris
parent
89ee6c778e
commit
467aac8463
10 changed files with 449 additions and 2193 deletions
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@ -12,8 +12,11 @@ work/coremark.bare.riscv.memfile: work/coremark.bare.riscv work/coremark.bare.ri
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work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
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riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump
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work/coremark.bare.riscv: $(sources)
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make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd"
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work/coremark.bare.riscv: $(sources) Makefile
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# make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta"
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# These flags were used by WD on CoreMark
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make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta "
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# -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error
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mkdir -p work/
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mv $(cmbase)/coremark.bare.riscv work/
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@ -1,3 +0,0 @@
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If you need to compile for different abi, below is an example of how to configure the gnu riscv toolchain.
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./configure --prefix=/import/eager1/ross/riscv-multilib-bin --enable-multilib --multilib-generate="rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv64ic-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--"
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33
examples/verilog/riscvsingle/riscvsingle.S
Normal file
33
examples/verilog/riscvsingle/riscvsingle.S
Normal file
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@ -0,0 +1,33 @@
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# riscvtest.s
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# Sarah.Harris@unlv.edu
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# David_Harris@hmc.edu
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# 27 Oct 2020
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#
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# Test the RISC-V processor.
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# add, sub, and, or, slt, addi, lw, sw, beq, jal
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# If successful, it should write the value 25 to address 100
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# RISC-V Assembly Description Address Machine Code
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main: addi x2, x0, 5 # x2 = 5 0 00500113
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addi x3, x0, 12 # x3 = 12 4 00C00193
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addi x7, x3, -9 # x7 = (12 - 9) = 3 8 FF718393
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or x4, x7, x2 # x4 = (3 OR 5) = 7 C 0023E233
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and x5, x3, x4 # x5 = (12 AND 7) = 4 10 0041F2B3
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add x5, x5, x4 # x5 = (4 + 7) = 11 14 004282B3
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beq x5, x7, end # shouldn't be taken 18 02728863
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slt x4, x3, x4 # x4 = (12 < 7) = 0 1C 0041A233
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beq x4, x0, around # should be taken 20 00020463
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addi x5, x0, 0 # shouldn't happen 24 00000293
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around: slt x4, x7, x2 # x4 = (3 < 5) = 1 28 0023A233
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add x7, x4, x5 # x7 = (1 + 11) = 12 2C 005203B3
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sub x7, x7, x2 # x7 = (12 - 5) = 7 30 402383B3
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sw x7, 84(x3) # [96] = 7 34 0471AA23
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lw x2, 96(x0) # x2 = [96] = 7 38 06002103
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add x9, x2, x5 # x9 = (7 + 11) = 18 3C 005104B3
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jal x3, end # jump to end, x3 = 0x44 40 008001EF
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addi x2, x0, 1 # shouldn't happen 44 00100113
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end: add x2, x2, x9 # x2 = (7 + 18) = 25 48 00910133
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sw x2, 0x20(x3) # mem[100] = 25 4C 0221A023
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done: beq x2, x2, done # infinite loop 50 00210063
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21
examples/verilog/riscvsingle/riscvsingle.memfile
Normal file
21
examples/verilog/riscvsingle/riscvsingle.memfile
Normal file
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@ -0,0 +1,21 @@
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00500113
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00C00193
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FF718393
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0023E233
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0041F2B3
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004282B3
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02728863
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0041A233
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00020463
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00000293
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0023A233
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005203B3
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402383B3
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0471AA23
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06002103
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005104B3
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008001EF
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00100113
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00910133
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0221A023
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00210063
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384
examples/verilog/riscvsingle/riscvsingle.sv
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384
examples/verilog/riscvsingle/riscvsingle.sv
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@ -0,0 +1,384 @@
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// riscvsingle.sv
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// RISC-V single-cycle processor
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// From Section 7.6 of Digital Design & Computer Architecture
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// 27 April 2020
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// David_Harris@hmc.edu
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// Sarah.Harris@unlv.edu
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// run 210
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// Expect simulator to print "Simulation succeeded"
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// when the value 25 (0x19) is written to address 100 (0x64)
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// Single-cycle implementation of RISC-V (RV32I)
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// User-level Instruction Set Architecture V2.2 (May 7, 2017)
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// Implements a subset of the base integer instructions:
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// lw, sw
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// add, sub, and, or, slt,
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// addi, andi, ori, slti
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// beq
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// jal
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// Exceptions, traps, and interrupts not implemented
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// little-endian memory
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// 31 32-bit registers x1-x31, x0 hardwired to 0
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// R-Type instructions
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// add, sub, and, or, slt
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// INSTR rd, rs1, rs2
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// Instr[31:25] = funct7 (funct7b5 & opb5 = 1 for sub, 0 for others)
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// I-Type Instructions
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// lw, I-type ALU (addi, andi, ori, slti)
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// lw: INSTR rd, imm(rs1)
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// I-type ALU: INSTR rd, rs1, imm (12-bit signed)
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// Instr[31:20] = imm[11:0]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// S-Type Instruction
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// sw rs2, imm(rs1) (store rs2 into address specified by rs1 + immm)
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// Instr[31:25] = imm[11:5] (offset[11:5])
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// Instr[24:20] = rs2 (src)
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// Instr[19:15] = rs1 (base)
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:0] (offset[4:0])
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// Instr[6:0] = opcode
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// B-Type Instruction
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// beq rs1, rs2, imm (PCTarget = PC + (signed imm x 2))
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// Instr[31:25] = imm[12], imm[10:5]
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// Instr[24:20] = rs2
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// Instr[19:15] = rs1
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// Instr[14:12] = funct3
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// Instr[11:7] = imm[4:1], imm[11]
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// Instr[6:0] = opcode
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// J-Type Instruction
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// jal rd, imm (signed imm is multiplied by 2 and added to PC, rd = PC+4)
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// Instr[31:12] = imm[20], imm[10:1], imm[11], imm[19:12]
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// Instr[11:7] = rd
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// Instr[6:0] = opcode
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// Instruction opcode funct3 funct7
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// add 0110011 000 0000000
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// sub 0110011 000 0100000
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// and 0110011 111 0000000
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// or 0110011 110 0000000
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// slt 0110011 010 0000000
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// addi 0010011 000 immediate
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// andi 0010011 111 immediate
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// ori 0010011 110 immediate
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// slti 0010011 010 immediate
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// beq 1100011 000 immediate
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// lw 0000011 010 immediate
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// sw 0100011 010 immediate
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// jal 1101111 immediate immediate
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module testbench();
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logic clk;
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logic reset;
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logic [31:0] WriteData, DataAdr;
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logic MemWrite;
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// instantiate device to be tested
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top dut(clk, reset, WriteData, DataAdr, MemWrite);
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// initialize test
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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if(MemWrite) begin
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if(DataAdr === 100 & WriteData === 25) begin
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$display("Simulation succeeded");
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$stop;
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end else if (DataAdr !== 96) begin
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$display("Simulation failed");
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$stop;
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end
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end
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end
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endmodule
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module top(input logic clk, reset,
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output logic [31:0] WriteData, DataAdr,
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output logic MemWrite);
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logic [31:0] PC, Instr, ReadData;
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// instantiate processor and memories
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riscvsingle rvsingle(clk, reset, PC, Instr, MemWrite, DataAdr,
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WriteData, ReadData);
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imem imem(PC, Instr);
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dmem dmem(clk, MemWrite, DataAdr, WriteData, ReadData);
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endmodule
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module riscvsingle(input logic clk, reset,
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output logic [31:0] PC,
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input logic [31:0] Instr,
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output logic MemWrite,
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output logic [31:0] ALUResult, WriteData,
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input logic [31:0] ReadData);
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logic ALUSrc, RegWrite, Jump, Zero;
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logic [1:0] ResultSrc, ImmSrc;
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logic [2:0] ALUControl;
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controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
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ResultSrc, MemWrite, PCSrc,
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ALUSrc, RegWrite, Jump,
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ImmSrc, ALUControl);
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datapath dp(clk, reset, ResultSrc, PCSrc,
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ALUSrc, RegWrite,
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ImmSrc, ALUControl,
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Zero, PC, Instr,
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ALUResult, WriteData, ReadData);
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endmodule
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module controller(input logic [6:0] op,
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input logic [2:0] funct3,
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input logic funct7b5,
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input logic Zero,
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output logic [1:0] ResultSrc,
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output logic MemWrite,
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output logic PCSrc, ALUSrc,
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output logic RegWrite, Jump,
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output logic [1:0] ImmSrc,
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output logic [2:0] ALUControl);
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logic [1:0] ALUOp;
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logic Branch;
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maindec md(op, ResultSrc, MemWrite, Branch,
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ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
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aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
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assign PCSrc = Branch & Zero | Jump;
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endmodule
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module maindec(input logic [6:0] op,
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output logic [1:0] ResultSrc,
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output logic MemWrite,
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output logic Branch, ALUSrc,
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output logic RegWrite, Jump,
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output logic [1:0] ImmSrc,
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output logic [1:0] ALUOp);
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logic [10:0] controls;
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assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
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ResultSrc, Branch, ALUOp, Jump} = controls;
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always_comb
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case(op)
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// RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
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7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
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7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
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7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type
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7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
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7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
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7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
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default: controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
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endcase
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endmodule
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module aludec(input logic opb5,
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input logic [2:0] funct3,
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input logic funct7b5,
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input logic [1:0] ALUOp,
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output logic [2:0] ALUControl);
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logic RtypeSub;
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assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
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always_comb
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case(ALUOp)
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2'b00: ALUControl = 3'b000; // addition
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2'b01: ALUControl = 3'b001; // subtraction
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default: case(funct3) // R-type or I-type ALU
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3'b000: if (RtypeSub)
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ALUControl = 3'b001; // sub
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else
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ALUControl = 3'b000; // add, addi
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3'b010: ALUControl = 3'b101; // slt, slti
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3'b110: ALUControl = 3'b011; // or, ori
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3'b111: ALUControl = 3'b010; // and, andi
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default: ALUControl = 3'bxxx; // ???
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endcase
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endcase
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endmodule
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module datapath(input logic clk, reset,
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input logic [1:0] ResultSrc,
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input logic PCSrc, ALUSrc,
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input logic RegWrite,
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input logic [1:0] ImmSrc,
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input logic [2:0] ALUControl,
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output logic Zero,
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output logic [31:0] PC,
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input logic [31:0] Instr,
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output logic [31:0] ALUResult, WriteData,
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input logic [31:0] ReadData);
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logic [31:0] PCNext, PCPlus4, PCTarget;
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logic [31:0] ImmExt;
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logic [31:0] SrcA, SrcB;
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logic [31:0] Result;
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// next PC logic
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flopr #(32) pcreg(clk, reset, PCNext, PC);
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adder pcadd4(PC, 32'd4, PCPlus4);
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adder pcaddbranch(PC, ImmExt, PCTarget);
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mux2 #(32) pcmux(PCPlus4, PCTarget, PCSrc, PCNext);
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// register file logic
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regfile rf(clk, RegWrite, Instr[19:15], Instr[24:20],
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Instr[11:7], Result, SrcA, WriteData);
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extend ext(Instr[31:7], ImmSrc, ImmExt);
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// ALU logic
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mux2 #(32) srcbmux(WriteData, ImmExt, ALUSrc, SrcB);
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alu alu(SrcA, SrcB, ALUControl, ALUResult, Zero);
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mux3 #(32) resultmux(ALUResult, ReadData, PCPlus4, ResultSrc, Result);
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endmodule
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module regfile(input logic clk,
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input logic we3,
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input logic [ 4:0] a1, a2, a3,
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input logic [31:0] wd3,
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output logic [31:0] rd1, rd2);
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logic [31:0] rf[31:0];
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// three ported register file
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// read two ports combinationally (A1/RD1, A2/RD2)
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// write third port on rising edge of clock (A3/WD3/WE3)
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// register 0 hardwired to 0
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always_ff @(posedge clk)
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if (we3) rf[a3] <= wd3;
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assign rd1 = (a1 != 0) ? rf[a1] : 0;
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assign rd2 = (a2 != 0) ? rf[a2] : 0;
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endmodule
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module adder(input [31:0] a, b,
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output [31:0] y);
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assign y = a + b;
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endmodule
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module extend(input logic [31:7] instr,
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input logic [1:0] immsrc,
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output logic [31:0] immext);
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always_comb
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case(immsrc)
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// I-type
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2'b00: immext = {{20{instr[31]}}, instr[31:20]};
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// S-type (stores)
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2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
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// B-type (branches)
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2'b10: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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// J-type (jal)
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2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
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default: immext = 32'bx; // undefined
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endcase
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endmodule
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module flopr #(parameter WIDTH = 8)
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(input logic clk, reset,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q);
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always_ff @(posedge clk, posedge reset)
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if (reset) q <= 0;
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else q <= d;
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endmodule
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module mux2 #(parameter WIDTH = 8)
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(input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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|
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module mux3 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1, d2,
|
||||
input logic [1:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
|
||||
endmodule
|
||||
|
||||
module imem(input logic [31:0] a,
|
||||
output logic [31:0] rd);
|
||||
|
||||
logic [31:0] RAM[63:0];
|
||||
|
||||
initial
|
||||
$readmemh("riscvtest.txt",RAM);
|
||||
|
||||
assign rd = RAM[a[31:2]]; // word aligned
|
||||
endmodule
|
||||
|
||||
module dmem(input logic clk, we,
|
||||
input logic [31:0] a, wd,
|
||||
output logic [31:0] rd);
|
||||
|
||||
logic [31:0] RAM[63:0];
|
||||
|
||||
assign rd = RAM[a[31:2]]; // word aligned
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (we) RAM[a[31:2]] <= wd;
|
||||
endmodule
|
||||
|
||||
module alu(input logic [31:0] a, b,
|
||||
input logic [2:0] alucontrol,
|
||||
output logic [31:0] result,
|
||||
output logic zero);
|
||||
|
||||
logic [31:0] condinvb, sum;
|
||||
logic v; // overflow
|
||||
logic isAddSub; // true when is add or subtract operation
|
||||
|
||||
assign condinvb = alucontrol[0] ? ~b : b;
|
||||
assign sum = a + condinvb + alucontrol[0];
|
||||
assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
|
||||
~alucontrol[1] & alucontrol[0];
|
||||
|
||||
always_comb
|
||||
case (alucontrol)
|
||||
3'b000: result = sum; // add
|
||||
3'b001: result = sum; // subtract
|
||||
3'b010: result = a & b; // and
|
||||
3'b011: result = a | b; // or
|
||||
3'b100: result = a ^ b; // xor
|
||||
3'b101: result = sum[31] ^ v; // slt
|
||||
3'b110: result = a << b[4:0]; // sll
|
||||
3'b111: result = a >> b[4:0]; // srl
|
||||
default: result = 32'bx;
|
||||
endcase
|
||||
|
||||
assign zero = (result == 32'b0);
|
||||
assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,135 +0,0 @@
|
|||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define BUILDROOT 0
|
||||
`define BUSYBEAR 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
//`define MISA (32'h00000104)
|
||||
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define MEM_DTIM 1
|
||||
`define MEM_DCACHE 1
|
||||
`define MEM_IROM 1
|
||||
`define MEM_ICACHE 1
|
||||
`define MEM_VIRTMEM 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 2048
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define DCACHE_REPLBITS 3
|
||||
`define ICACHE_NUMWAYS 1
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h00000000000100b0
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 34'h80000000
|
||||
`define RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10012000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 0
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_UART_ID 4
|
||||
|
||||
// Can add PLIC Config here
|
||||
// Num interrupt sources
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/coremark/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/coremark/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
|
@ -28,7 +28,8 @@ vlib work
|
|||
# because vsim will run vopt
|
||||
|
||||
# default to config/coremark, but allow this to be overridden at the command line. For example:
|
||||
vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
#vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
|
|
|
|||
|
|
@ -77,9 +77,9 @@ module testbench();
|
|||
assign HREADYEXT = 1;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
wallypipelinedsoc dut(.clk, .reset_ext, .reset(), .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
|
||||
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
|
||||
|
||||
logic [31:0] InstrW;
|
||||
|
|
@ -87,7 +87,7 @@ module testbench();
|
|||
|
||||
// Track names of instructions
|
||||
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
||||
dut.hart.ifu.icache.FinalInstrRawF,
|
||||
dut.hart.ifu.icache.icache.readdata.FinalInstrRawF, // *** is there a better name
|
||||
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
||||
dut.hart.ifu.InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
|
@ -123,7 +123,7 @@ module testbench();
|
|||
end
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (dut.hart.priv.ecallM) begin
|
||||
if (dut.hart.priv.priv.ecallM) begin
|
||||
#20;
|
||||
$display("Code ended with ebreakM");
|
||||
$stop;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue