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rv32imc lockstep config fixes

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Jordan Carlin 2025-03-13 01:01:50 -07:00
parent 8cf1e84fd4
commit 48f2b7eac1
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1 changed files with 8 additions and 24 deletions
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32
config/rv32imc/imperas.ic
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@ -17,13 +17,10 @@
--override cpu/mvendorid=0x602
--override cpu/marchid=0x24
--override refRoot/cpu/tvec_align=64
# --override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
# No virtual memory
--override cpu/Sv_modes=1
--override cpu/tval_ii_code=T
# mstatus.FS read-only 0
--override cpu/mstatus_FS_zero=T
@ -38,26 +35,20 @@
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
--override cpu/ecode_mask=0x8000000F # for RV32
# --override cpu/ecode_mask=0x800000000000000F # for RV64
# Debug mode not yet supported
--override cpu/debug_mode=none
--override cpu/Smepmp_version=none
--override cpu/Smmpm=none
#--override cpu/Zicfilp=F
--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
# disable CSRs 7a0-7a8
--override cpu/trigger_num=0
# Reset address
--override cpu/reset_address=0x80000000
--override cpu/unaligned=F # Zicclsm (should be true)
# Wally implementats WFI as NOP
--override cpu/wfi_is_nop=T
--override cpu/misa_Extensions_mask=0x0 # MISA not writable
# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
#--override cpu/updatePTEA=F
#--override cpu/updatePTED=F
# MISA not writable
--override cpu/misa_Extensions_mask=0x0
# No PMP
--override cpu/PMP_registers=0
--override cpu/PMP_undefined=T
@ -78,19 +69,12 @@
#
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
# Enable the Imperas instruction coverage
#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
#-override refRoot/cpu/cv/cover=basic
#-override refRoot/cpu/cv/extensions=RV32I
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x00807FFFFF -attributes " rwx--- 1248 " # DTIM/IROM
# Store simulator output to logfile
--output imperas.log