mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 22:07:12 -04:00
Merge branch 'main' of github.com:ross144/cvw into main
This commit is contained in:
Ross Thompson
commit
625192d9a4
6 changed files with 107 additions and 114 deletions
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@ -93,7 +93,7 @@ localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2);
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localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
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// division constants
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localparam DIVN = (((NF<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
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localparam DIVN = (((NF+2<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
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localparam LOGR = ($clog2(RADIX)); // r = log(R)
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localparam RK = (LOGR*DIVCOPIES); // r*k used for intdiv preproc
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localparam LOGRK = ($clog2(RK)); // log2(r*k)
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140
sim/wave.do
140
sim/wave.do
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@ -11,37 +11,37 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
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add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
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add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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@ -74,26 +74,27 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
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add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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@ -520,8 +521,8 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
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add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
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add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
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add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
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add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
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add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
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add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
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add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
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add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
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add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
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add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
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@ -594,26 +595,19 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
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add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
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add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
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add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
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add wave -noupdate /testbench/LoadMem
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add wave -noupdate /testbench/CurrState
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add wave -noupdate /testbench/DCacheFlushStart
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3
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add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM
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||||
add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf
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add wave -noupdate /testbench/ecf
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||||
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce
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||||
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we
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||||
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr
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add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout
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||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW
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||||
add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE
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||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
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||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
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||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
|
||||
add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW
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||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW
|
||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW
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||||
add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1}
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||||
WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1}
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||||
quietly wave cursor active 1
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||||
configure wave -namecolwidth 250
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||||
configure wave -valuecolwidth 194
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||||
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@ -629,4 +623,4 @@ configure wave -griddelta 40
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|||
configure wave -timeline 0
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||||
configure wave -timelineunits ns
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||||
update
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||||
WaveRestoreZoom {319935 ns} {320329 ns}
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||||
WaveRestoreZoom {6124 ns} {6284 ns}
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||||
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|||
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@ -200,7 +200,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
|
|||
((P.XLEN == 64) & (Funct3D == 3'b011));
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||||
assign BFunctD = Funct3D[2:1] != 2'b01; // legal branches
|
||||
assign JRFunctD = Funct3D == 3'b000;
|
||||
assign PFunctD = Funct3D == 3'b000 & Rs1D == 5'b0 & RdD == 5'b0;
|
||||
assign PFunctD = Funct3D == 3'b000 & RdD == 5'b0;
|
||||
assign CSRFunctD = Funct3D[1:0] != 2'b00;
|
||||
assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101;
|
||||
end else begin:legalcheck2
|
||||
|
|
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|||
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@ -54,11 +54,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
||||
logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
|
||||
logic [P.XLEN-1:0] MENVCFGH_REGW;
|
||||
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
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logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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logic WriteMENVCFGM;
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// Machine CSRs
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localparam MVENDORID = 12'hF11;
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@ -82,7 +80,6 @@ module csrm import cvw::*; #(parameter cvw_t P) (
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localparam MCAUSE = 12'h342;
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localparam MTVAL = 12'h343;
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localparam MIP = 12'h344;
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localparam MTINST = 12'h34A;
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localparam PMPCFG0 = 12'h3A0;
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// .. up to 15 more at consecutive addresses
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localparam PMPADDR0 = 12'h3B0;
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@ -146,7 +143,6 @@ module csrm import cvw::*; #(parameter cvw_t P) (
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assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
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assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
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assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
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assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
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assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
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assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
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@ -168,6 +164,11 @@ module csrm import cvw::*; #(parameter cvw_t P) (
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flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
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end else assign MCOUNTEREN_REGW = '0;
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||||
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// MENVCFG register
|
||||
if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
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logic WriteMENVCFGM;
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||||
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
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||||
assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
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// MENVCFG is always 64 bits even for RV32
|
||||
assign MENVCFG_WriteValM = {
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||||
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
|
||||
|
|
@ -178,12 +179,11 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
3'b0,
|
||||
MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
|
||||
};
|
||||
|
||||
if (P.XLEN == 64) begin
|
||||
assign MENVCFG_PreWriteValM = CSRWriteValM;
|
||||
flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
|
||||
assign MENVCFGH_REGW = 0;
|
||||
end else begin
|
||||
end else begin // RV32 has high and low halves
|
||||
logic WriteMENVCFGHM;
|
||||
assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
|
||||
assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
|
||||
|
|
@ -191,12 +191,14 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
|
||||
assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
|
||||
end
|
||||
end
|
||||
|
||||
// Read machine mode CSRs
|
||||
// verilator lint_off WIDTH
|
||||
logic [5:0] entry;
|
||||
always_comb begin
|
||||
entry = '0;
|
||||
CSRMReadValM = 0;
|
||||
IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
|
||||
if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry
|
||||
CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
|
||||
|
|
@ -219,7 +221,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
|
||||
MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0
|
||||
MSTATUS: CSRMReadValM = MSTATUS_REGW;
|
||||
MSTATUSH: CSRMReadValM = MSTATUSH_REGW;
|
||||
MSTATUSH: if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW;
|
||||
else IllegalCSRMAccessM = 1;
|
||||
MTVEC: CSRMReadValM = MTVEC_REGW;
|
||||
MEDELEG: CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW};
|
||||
MIDELEG: CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW};
|
||||
|
|
@ -229,16 +232,13 @@ module csrm import cvw::*; #(parameter cvw_t P) (
|
|||
MEPC: CSRMReadValM = MEPC_REGW;
|
||||
MCAUSE: CSRMReadValM = MCAUSE_REGW;
|
||||
MTVAL: CSRMReadValM = MTVAL_REGW;
|
||||
MTINST: CSRMReadValM = 0; // implemented as trivial zero
|
||||
MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
|
||||
MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
|
||||
MENVCFGH: CSRMReadValM = MENVCFGH_REGW;
|
||||
MENVCFG: if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
|
||||
else IllegalCSRMAccessM = 1;
|
||||
MENVCFGH: if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
|
||||
else IllegalCSRMAccessM = 1;
|
||||
MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
|
||||
|
||||
default: begin
|
||||
CSRMReadValM = 0;
|
||||
IllegalCSRMAccessM = 1;
|
||||
end
|
||||
default: IllegalCSRMAccessM = 1;
|
||||
endcase
|
||||
end
|
||||
// verilator lint_on WIDTH
|
||||
|
|
|
|||
|
|
@ -54,7 +54,6 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
|
|||
// STATUS REGISTER FIELD
|
||||
// See Privileged Spec Section 3.1.6
|
||||
// Lower privilege status registers are a subset of the full status register
|
||||
// *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable
|
||||
if (P.XLEN==64) begin: csrsr64 // RV64
|
||||
assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
|
||||
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue