mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 12:57:23 -04:00
Merge branch 'localhistory'
Repair to wave file. Created implementations of local history. Part of my Ph.D. research.
This commit is contained in:
Ross Thompson
commit
664231c0da
19 changed files with 494 additions and 215 deletions
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@ -279,12 +279,13 @@ if(sys.argv[1] == '-b'):
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dct[PredType] = (currSize, currPercent)
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print(dct)
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fig, axes = plt.subplots()
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marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*'}
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colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue'}
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marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
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colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
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for cat in dct:
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(x, y) = dct[cat]
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x=[int(2**int(v)) for v in x]
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print(x, y)
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#print(x, y)
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print(cat)
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axes.plot(x,y, color=colors[cat])
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axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
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#plt.scatter(x, y, label=cat)
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@ -132,6 +132,7 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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@ -141,6 +141,7 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 12
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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@ -136,6 +136,7 @@
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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@ -133,8 +133,9 @@
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`define PLIC_UART_ID 10
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_TYPE "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 16
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`define BPRED_NUM_LHR 8
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 1
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@ -136,6 +136,7 @@
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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@ -135,6 +135,7 @@
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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@ -138,6 +138,7 @@
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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@ -136,8 +136,10 @@
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`define PLIC_UART_ID 10
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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//`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_TYPE "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 6
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`define BPRED_NUM_LHR 4
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 1
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@ -138,6 +138,7 @@
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BPRED_NUM_LHR 6
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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@ -46,18 +46,33 @@ configs = [
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)
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]
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# bpdSize = [6, 8, 10, 12, 14, 16]
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# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
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# for CurrBPType in bpdType:
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# for CurrBPSize in bpdSize:
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# name = CurrBPType+str(CurrBPSize)
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# configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
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# tc = TestCase(
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# name=name,
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# variant="rv32gc",
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# cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
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# grepstr="")
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# configs.append(tc)
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bpdSize = [6, 8, 10, 12, 14, 16]
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bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic']
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LHRSize = [4, 8, 10]
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bpdType = ['local_repair']
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for CurrBPType in bpdType:
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for CurrBPSize in bpdSize:
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name = CurrBPType+str(CurrBPSize)
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configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
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tc = TestCase(
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name=name,
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variant="rv32gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
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grepstr="")
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configs.append(tc)
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for CurrLHRSize in LHRSize:
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name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
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configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
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tc = TestCase(
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name=name,
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variant="rv32gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc configOptions " + name + " embench " + configOptions,
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grepstr="")
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configs.append(tc)
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import os
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from multiprocessing import Pool, TimeoutError
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112
sim/wave.do
112
sim/wave.do
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@ -6,12 +6,6 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/FunctionName/FunctionName/PCD
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add wave -noupdate /testbench/FunctionName/FunctionName/PCE
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add wave -noupdate /testbench/FunctionName/FunctionName/PCF
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add wave -noupdate /testbench/FunctionName/FunctionName/PCM
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add wave -noupdate /testbench/FunctionName/FunctionName/PCM_temp
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add wave -noupdate /testbench/FunctionName/FunctionName/PCMOld
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
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add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
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@ -38,15 +32,16 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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@ -66,10 +61,10 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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@ -99,9 +94,9 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
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add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -expand -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -expand -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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|
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@ -152,23 +147,24 @@ add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
|
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/ebufsmarb/CurrState
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
|
||||
add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
||||
add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
|
||||
add wave -noupdate -group AHB -group IFU /testbench/dut/core/HRDATA
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
|
||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
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||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/HRDATA
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||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
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||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
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||||
add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
||||
add wave -noupdate -group AHB -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
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||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
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||||
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@ -323,13 +319,6 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3
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add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
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||||
add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
|
|
@ -361,6 +350,8 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMASt
|
|||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
|
|
@ -372,10 +363,14 @@ add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /test
|
|||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
|
||||
|
|
@ -538,10 +533,10 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
|
|||
add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
|
|
@ -591,21 +586,31 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
|
|||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
|
||||
add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
|
||||
add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
|
||||
add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRM
|
||||
add wave -noupdate -label BHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BHT/mem
|
||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPDirPredD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRNextW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewBPDirPredM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRCommittedF
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1868041 ns} 0} {{Cursor 5} {394987 ns} 1}
|
||||
quietly wave cursor active 4
|
||||
WaveRestoreCursors {{Cursor 4} {12208 ns} 1} {{Cursor 4} {30 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
configure wave -justifyvalue left
|
||||
|
|
@ -620,4 +625,3 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {7738932 ns}
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define INSTR_CLASS_PRED 1
|
||||
`define INSTR_CLASS_PRED 0
|
||||
|
||||
module bpred (
|
||||
input logic clk, reset,
|
||||
|
|
@ -127,19 +127,21 @@ module bpred (
|
|||
.PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
|
||||
.BranchE, .BranchM, .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
|
||||
// *** Fix me
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
localHistoryPredictor DirPredictor(.clk,
|
||||
.reset, .StallF, .StallE,
|
||||
.LookUpPC(PCNextF),
|
||||
.Prediction(BPDirPredF),
|
||||
// update
|
||||
.UpdatePC(PCE),
|
||||
.UpdateEN(InstrClassE[0] & ~StallE),
|
||||
.PCSrcE,
|
||||
.UpdatePrediction(InstrClassE[0]));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end else if (`BPRED_TYPE == "BP_LOCAL_BASIC") begin:Predictor
|
||||
localbpbasic #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
|
||||
.BranchE, .BranchM, .PCSrcE);
|
||||
end else if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin:Predictor
|
||||
localaheadbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
|
||||
.BranchE, .BranchM, .PCSrcE);
|
||||
end else if (`BPRED_TYPE == "BP_LOCAL_REPAIR") begin:Predictor
|
||||
localreapirbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
|
||||
.BranchD, .BranchE, .BranchM, .PCSrcE);
|
||||
end
|
||||
|
||||
// Part 2 Branch target address prediction
|
||||
|
|
|
|||
|
|
@ -1,130 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// locallHistoryPredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
|
||||
k = 10) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] Prediction,
|
||||
// update
|
||||
input logic [`XLEN-1:0] UpdatePC,
|
||||
input logic UpdateEN, PCSrcE,
|
||||
input logic [1:0] UpdatePrediction
|
||||
);
|
||||
|
||||
logic [2**m-1:0][k-1:0] LHRNextF;
|
||||
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
|
||||
logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
|
||||
logic [1:0] PredictionMemory;
|
||||
logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
|
||||
logic [1:0] UpdatePredictionF;
|
||||
|
||||
assign LHRFNext = {PCSrcE, LHRF[k-1:1]};
|
||||
assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
|
||||
assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};
|
||||
|
||||
// INCASE we do ahead pipelining
|
||||
// ram2p1r1wb #(m,k) LHR(.clk(clk)),
|
||||
// .reset(reset),
|
||||
// .RA1(LookUpPCIndex), // need hashing function to get correct PC address
|
||||
// .RD1(LHRF),
|
||||
// .REN1(~StallF),
|
||||
// .WA1(UpdatePCIndex),
|
||||
// .WD1(LHRENExt),
|
||||
// .WEN1(UpdateEN),
|
||||
// .BitWEN1(2'b11));
|
||||
|
||||
genvar index;
|
||||
for (index = 0; index < 2**m; index = index +1) begin:localhist
|
||||
flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
|
||||
.d(LHRFNext), .q(LHRNextF[index]));
|
||||
end
|
||||
|
||||
// need to forward when updating to the same address as reading.
|
||||
// first we compare to see if the update and lookup addreses are the same
|
||||
assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
|
||||
assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex];
|
||||
|
||||
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
|
||||
// LHR referes to the address that the past k branches points to in the prediction stage
|
||||
// LHRE refers to the address that the past k branches points to in the exectution stage
|
||||
ram2p1r1wb #(k, 2) PHT(.clk(clk),
|
||||
.reset(reset),
|
||||
.ra1(ForwardLHRNext),
|
||||
.rd1(PredictionMemory),
|
||||
.ren1(~StallF),
|
||||
.wa2(LHRFNext),
|
||||
.wd2(UpdatePrediction),
|
||||
.wen2(UpdateEN),
|
||||
.bwe2(2'b11));
|
||||
|
||||
|
||||
|
||||
assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
|
||||
|
||||
// register the update value and the forwarding signal into the Fetch stage
|
||||
// TODO: add stall logic ***
|
||||
flopr #(1) DoForwardingReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.d(DoForwardingPHT),
|
||||
.q(DoForwardingPHTF));
|
||||
|
||||
flopr #(2) UpdatePredictionReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.d(UpdatePrediction),
|
||||
.q(UpdatePredictionF));
|
||||
|
||||
assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
|
||||
|
||||
//pipeline for LHR
|
||||
flopenrc #(k) LHRFReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallF),
|
||||
.clear(1'b0),
|
||||
.d(ForwardLHRNext),
|
||||
.q(LHRF));
|
||||
/*
|
||||
flopenrc #(k) LHRDReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallD),
|
||||
.clear(FlushD),
|
||||
.d(LHRF),
|
||||
.q(LHRD));
|
||||
|
||||
flopenrc #(k) LHREReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallE),
|
||||
.clear(FlushE),
|
||||
.d(LHRD),
|
||||
.q(LHRE));
|
||||
*/
|
||||
endmodule
|
||||
117
src/ifu/bpred/localaheadbp.sv
Normal file
117
src/ifu/bpred/localaheadbp.sv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
///////////////////////////////////////////
|
||||
// gsharebasic.sv
|
||||
//
|
||||
// Written: Ross Thompson
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: 16 March 2021
|
||||
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
|
||||
// Modified: 20 February 2023
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] BPDirPredD,
|
||||
output logic BPDirPredWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchE, BranchM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexM;
|
||||
//logic [1:0] BPDirPredD, BPDirPredE;
|
||||
logic [1:0] BPDirPredE;
|
||||
logic [1:0] BPDirPredM;
|
||||
logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
|
||||
|
||||
logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
|
||||
logic [k-1:0] LHRNextW;
|
||||
logic PCSrcM;
|
||||
logic [2**m-1:0][k-1:0] LHRArray;
|
||||
logic [m-1:0] IndexLHRNextF, IndexLHRM;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
|
||||
logic UpdateM;
|
||||
|
||||
//assign IndexNextF = LHR;
|
||||
assign IndexM = LHRW;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallD), .ce2(~StallW & ~FlushW),
|
||||
.ra1(LHRF),
|
||||
.rd1(BPDirPredD),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewBPDirPredW),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
//flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
|
||||
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
|
||||
flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM);
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
|
||||
//flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
|
||||
flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
|
||||
|
||||
assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
|
||||
|
||||
// This is the main difference between global and local history basic implementations. In global,
|
||||
// the ghr wraps back into itself directly without
|
||||
// being pipelined. I.E. GHR is not read in F and then pipelined to M where it is updated. Instead
|
||||
// GHR is both read and update in M. GHR is still pipelined so that the PHT is updated with the correct
|
||||
// GHR. Local history in contrast must pipeline the specific history register read during F and then update
|
||||
// that same one in M. This implementation does not forward if a branch matches in the D, E, or M stages.
|
||||
assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
|
||||
|
||||
// this is local history
|
||||
//genvar index;
|
||||
//assign UpdateM = BranchM & ~StallW & ~FlushW;
|
||||
assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
|
||||
assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
|
||||
|
||||
ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexLHRNextF),
|
||||
.rd1(LHRF),
|
||||
.wa2(IndexLHRM),
|
||||
.wd2(LHRNextW),
|
||||
.we2(BranchM),
|
||||
.bwe2('1));
|
||||
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
//flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
|
||||
//assign LHRF = LHRNextF;
|
||||
flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
|
||||
flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
|
||||
flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
|
||||
flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
107
src/ifu/bpred/localbpbasic.sv
Normal file
107
src/ifu/bpred/localbpbasic.sv
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
///////////////////////////////////////////
|
||||
// gsharebasic.sv
|
||||
//
|
||||
// Written: Ross Thompson
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: 16 March 2021
|
||||
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
|
||||
// Modified: 20 February 2023
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module localbpbasic #(parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] BPDirPredF,
|
||||
output logic BPDirPredWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchE, BranchM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexM;
|
||||
logic [1:0] BPDirPredD, BPDirPredE;
|
||||
logic [1:0] NewBPDirPredE, NewBPDirPredM;
|
||||
|
||||
logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHR;
|
||||
logic [k-1:0] LHRNextW;
|
||||
logic PCSrcM;
|
||||
logic [2**m-1:0][k-1:0] LHRArray;
|
||||
logic [m-1:0] IndexLHRNextF, IndexLHRM;
|
||||
|
||||
logic UpdateM;
|
||||
|
||||
assign IndexNextF = LHR;
|
||||
assign IndexM = LHRM;
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(BPDirPredF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewBPDirPredM),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
|
||||
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
|
||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
|
||||
|
||||
assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
|
||||
|
||||
// This is the main difference between global and local history basic implementations. In global,
|
||||
// the ghr wraps back into itself directly without
|
||||
// being pipelined. I.E. GHR is not read in F and then pipelined to M where it is updated. Instead
|
||||
// GHR is both read and update in M. GHR is still pipelined so that the PHT is updated with the correct
|
||||
// GHR. Local history in contrast must pipeline the specific history register read during F and then update
|
||||
// that same one in M. This implementation does not forward if a branch matches in the D, E, or M stages.
|
||||
assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
|
||||
|
||||
// this is local history
|
||||
genvar index;
|
||||
assign UpdateM = BranchM & ~StallW & ~FlushW;
|
||||
assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
|
||||
for (index = 0; index < 2**m; index = index +1) begin:localhist
|
||||
flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
|
||||
.d(LHRNextW), .q(LHRArray[index]));
|
||||
end
|
||||
assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
|
||||
assign LHR = LHRArray[IndexLHRNextF];
|
||||
|
||||
// this is global history
|
||||
//flopenr #(k) LHRReg(clk, reset, ~StallM & ~FlushM & BranchM, LHRNextW, LHR);
|
||||
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHR, LHRF);
|
||||
flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
|
||||
flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
|
||||
flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
|
||||
|
||||
|
||||
endmodule
|
||||
138
src/ifu/bpred/localrepairbp.sv
Normal file
138
src/ifu/bpred/localrepairbp.sv
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
///////////////////////////////////////////
|
||||
// gsharebasic.sv
|
||||
//
|
||||
// Written: Ross Thompson
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: 16 March 2021
|
||||
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
|
||||
// Modified: 20 February 2023
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module localreapirbp #(parameter m = 6, // 2^m = number of local history branches
|
||||
parameter k = 10) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] BPDirPredD,
|
||||
output logic BPDirPredWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCE, PCM,
|
||||
input logic BranchD, BranchE, BranchM, PCSrcE
|
||||
);
|
||||
|
||||
//logic [1:0] BPDirPredD, BPDirPredE;
|
||||
logic [1:0] BPDirPredE;
|
||||
logic [1:0] BPDirPredM;
|
||||
logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
|
||||
|
||||
logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
|
||||
logic [k-1:0] LHRNextW;
|
||||
logic PCSrcM;
|
||||
logic [2**m-1:0][k-1:0] LHRArray;
|
||||
logic [m-1:0] IndexLHRNextF, IndexLHRM;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [k-1:0] LHRCommittedF, LHRSpeculativeF;
|
||||
logic [m-1:0] IndexLHRD;
|
||||
logic [k-1:0] LHRNextE;
|
||||
logic SpeculativeFlushedF;
|
||||
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallD), .ce2(~StallW & ~FlushW),
|
||||
.ra1(LHRF),
|
||||
.rd1(BPDirPredD),
|
||||
.wa2(LHRW),
|
||||
.wd2(NewBPDirPredW),
|
||||
.we2(BranchM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
//flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
|
||||
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
|
||||
flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM);
|
||||
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
|
||||
//flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
|
||||
flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
|
||||
|
||||
assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
|
||||
|
||||
// This is the main difference between global and local history basic implementations. In global,
|
||||
// the ghr wraps back into itself directly without
|
||||
// being pipelined. I.E. GHR is not read in F and then pipelined to M where it is updated. Instead
|
||||
// GHR is both read and update in M. GHR is still pipelined so that the PHT is updated with the correct
|
||||
// GHR. Local history in contrast must pipeline the specific history register read during F and then update
|
||||
// that same one in M. This implementation does not forward if a branch matches in the D, E, or M stages.
|
||||
assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
|
||||
|
||||
// this is local history
|
||||
assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
|
||||
assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
|
||||
|
||||
ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexLHRNextF),
|
||||
.rd1(LHRCommittedF),
|
||||
.wa2(IndexLHRM),
|
||||
.wd2(LHRNextW),
|
||||
.we2(BranchM),
|
||||
.bwe2('1));
|
||||
|
||||
assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
|
||||
assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE;
|
||||
// *** replace with a small CAM
|
||||
ram2p1r1wbe #(2**m, k) SHB(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallE & ~FlushE),
|
||||
.ra1(IndexLHRNextF),
|
||||
.rd1(LHRSpeculativeF),
|
||||
.wa2(IndexLHRD),
|
||||
.wd2(LHRNextE),
|
||||
.we2(BranchD),
|
||||
.bwe2('1));
|
||||
// **** replace with small CAM
|
||||
logic [2**m-1:0] FlushedBits;
|
||||
always_ff @(posedge clk) begin // Valid bit array,
|
||||
SpeculativeFlushedF <= #1 FlushedBits[IndexLHRNextF];
|
||||
if (reset | FlushD) FlushedBits <= #1 '1;
|
||||
if(BranchD & ~StallE & ~FlushE) begin
|
||||
FlushedBits[IndexLHRD] <= #1 '0;
|
||||
end
|
||||
end
|
||||
|
||||
//assign SpeculativeFlushedF = '1;
|
||||
mux2 #(k) LHRMux(LHRSpeculativeF, LHRCommittedF, SpeculativeFlushedF, LHRF);
|
||||
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
|
||||
//flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
|
||||
//assign LHRF = LHRNextF;
|
||||
flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
|
||||
flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
|
||||
flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
|
||||
flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
`include "wally-config.vh"
|
||||
`include "tests.vh"
|
||||
|
||||
`define PrintHPMCounters 0
|
||||
`define PrintHPMCounters 1
|
||||
`define BPRED_LOGGER 0
|
||||
`define I_CACHE_ADDR_LOGGER 0
|
||||
`define D_CACHE_ADDR_LOGGER 0
|
||||
|
|
@ -540,6 +540,21 @@ module testbench;
|
|||
if (`BPRED_SUPPORTED) begin
|
||||
integer adrindex;
|
||||
|
||||
// local history only
|
||||
if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
|
||||
always @(*) begin
|
||||
if(reset) begin
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
|
||||
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
|
||||
end
|
||||
#1;
|
||||
for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
|
||||
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if(reset) begin
|
||||
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
|
||||
|
|
|
|||
|
|
@ -2077,8 +2077,8 @@ string arch64zbs[] = '{
|
|||
|
||||
string custom[] = '{
|
||||
`CUSTOM,
|
||||
"debug",
|
||||
"simple",
|
||||
"debug",
|
||||
"cacheTest"
|
||||
};
|
||||
string testsBP64[] = '{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue