mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 21:38:55 -04:00
Merge branch 'main' of github.com:openhwgroup/cvw
This commit is contained in:
Jacob Pease
commit
669ae65c4f
6 changed files with 2 additions and 265 deletions
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Subproject commit bbcba78647080dee82e96bc1b8ff9cd9a3cf7fa1
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Subproject commit 189974e497d7b8d2c08bb1d151b1ccdeaf3a64c9
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Subproject commit ce04b4930545ae4c81e2f3b6f6935e2aac08679e
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Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874
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@ -238,46 +238,6 @@
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0000001F
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00000062 # hardware interlock
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00000026
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000000D2
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0000002D
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00000048
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00000037
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00000026
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00000015
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00000084
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00000073
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00000062
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00000051
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00000046
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00000035
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00000024
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00000013
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00000064
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00000053
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00000042
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00000031
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00000001 #watermark interrupts
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00000000 #read mip
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@ -547,101 +547,6 @@ test_cases:
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#.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
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#.4byte rx_data, 0x000000F0, read32_test # read rx_data
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#=========== Test Hardware Interlock ================
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# interlock in base case
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.4byte fmt, 0x00080000, write32_test # reset fmt register
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.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x00000062, write32_test # initiate transmission
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.4byte sck_mode, 0x00000002, write32_test # flip polarity during transmission
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.4byte tx_data, 0x00000026, write32_test # transmit second frame w/ control register updated
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.4byte 0x0, 0x00000001, spi_data_wait
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.4byte rx_data, 0x00000062, read32_test
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.4byte rx_data, 0x00000026, read32_test # clear rx fifo
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.4byte sck_mode, 0x00000000, write32_test # reset polarity
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# interlock in case where cs_mode is auto, but there is minimal intercs delay
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.4byte delay0, 0x00000001, write32_test # set sck-cs delay to 0, with sck.pha 0 there is 0 delay
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.4byte tx_data, 0x000000D2, write32_test # initiate transmission
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.4byte sck_mode, 0x00000002, write32_test # flip sck polarity
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.4byte tx_data, 0x0000002D, write32_test # transmit second frame
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.4byte 0x0, 0x00000001, spi_data_wait
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.4byte rx_data, 0x000000D2, read32_test
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.4byte rx_data, 0x0000002D, read32_test # clear rx fifo
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.4byte sck_mode, 0x00000000, write32_test # reset polarity
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# interlock in case where cs_mode = hold, 0 intercs delay
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.4byte delay0, 0x00010001, write32_test # reset delay0
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.4byte sck_mode, 0x00000000, write32_test # reset polarity
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.4byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
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.4byte tx_data, 0x15263748, spi_burst_send # place 4 frames into tx fifo
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.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte sck_mode, 0x00000000, write32_test # flip polarity again
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.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.4byte rx_data, 0x00000048, read32_test
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.4byte rx_data, 0x00000037, read32_test
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.4byte rx_data, 0x00000026, read32_test
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.4byte rx_data, 0x00000015, read32_test #clear rx fifo
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# interlock in case where cs_mode = hold, intercs delay
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.4byte sck_mode, 0x00000000, write32_test # reset polarity
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.4byte delay1, 0x00010001, write32_test # set intercs delay to 1
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.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x51627384, spi_burst_send # place 4 frames into tx fifo
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.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte sck_mode, 0x00000000, write32_test # flip polarity again
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.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.4byte rx_data, 0x00000084, read32_test
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.4byte rx_data, 0x00000073, read32_test
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.4byte rx_data, 0x00000062, read32_test
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.4byte rx_data, 0x00000051, read32_test #clear rx fifo
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# repeat previous set of tests with cs_mode = off
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.4byte cs_mode, 0x00000003, write32_test # set cs_mode to hold
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.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x13243546, spi_burst_send # place 4 frames into tx fifo
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.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte sck_mode, 0x00000000, write32_test # flip polarity again
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.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.4byte rx_data, 0x00000046, read32_test
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.4byte rx_data, 0x00000035, read32_test
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.4byte rx_data, 0x00000024, read32_test
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.4byte rx_data, 0x00000013, read32_test #clear rx fifo
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# interlock in case where cs_mode = hold, intercs delay
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.4byte sck_mode, 0x00000000, write32_test # reset polarity
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.4byte delay1, 0x00000000, write32_test # set intercs delay to 0
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.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.4byte tx_data, 0x31425364, spi_burst_send # place 4 frames into tx fifo
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.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.4byte sck_mode, 0x00000000, write32_test # flip polarity again
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.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.4byte rx_data, 0x00000064, read32_test
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.4byte rx_data, 0x00000053, read32_test
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.4byte rx_data, 0x00000042, read32_test
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.4byte rx_data, 0x00000031, read32_test #clear rx fifo
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# =========== Test watermark interrupts ===========
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@ -238,46 +238,6 @@
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00000000
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0000001F
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00000000
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00000062 # hardware interlock
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00000000
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00000026
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00000000
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000000D2
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00000000
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0000002D
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00000000
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00000048
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00000000
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00000037
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00000000
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00000026
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00000000
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00000015
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00000000
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00000084
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00000000
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00000073
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00000000
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00000062
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00000000
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00000051
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00000000
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00000046
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00000000
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00000035
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00000000
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00000024
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00000000
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00000013
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00000000
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00000064
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00000000
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00000053
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00000000
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00000042
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00000000
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00000031
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00000000
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00000001 #watermark interrupts
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00000000
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00000000 #read mip
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@ -551,94 +551,6 @@ test_cases:
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#.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
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#.8byte rx_data, 0x000000F0, read32_test # read rx_data
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#=========== Test Hardware Interlock ================
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# interlock in base case
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.8byte fmt, 0x00080000, write32_test # reset fmt register
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.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.8byte tx_data, 0x00000062, write32_test # initiate transmission
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.8byte sck_mode, 0x00000002, write32_test # flip polarity during transmission
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.8byte tx_data, 0x00000026, write32_test # transmit second frame w/ control register updated
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.8byte 0x0, 0x00000001, spi_data_wait
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.8byte rx_data, 0x00000062, read32_test
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.8byte rx_data, 0x00000026, read32_test # clear rx fifo
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.8byte sck_mode, 0x00000000, write32_test # reset polarity
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# interlock in case where cs_mode is auto, but there is minimal intercs delay
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.8byte delay0, 0x00000001, write32_test # set sck-cs delay to 0, with sck.pha 0 there is 0 delay
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.8byte tx_data, 0x000000D2, write32_test # initiate transmission
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.8byte sck_mode, 0x00000002, write32_test # flip sck polarity
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.8byte tx_data, 0x0000002D, write32_test # transmit second frame
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.8byte 0x0, 0x00000001, spi_data_wait
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.8byte rx_data, 0x000000D2, read32_test
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.8byte rx_data, 0x0000002D, read32_test # clear rx fifo
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.8byte sck_mode, 0x00000000, write32_test # reset polarity
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# interlock in case where cs_mode = hold, 0 intercs delay
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.8byte delay0, 0x00010001, write32_test # reset delay0
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.8byte sck_mode, 0x00000000, write32_test # reset polarity
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.8byte cs_mode, 0x00000002, write32_test # set cs_mode to hold
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.8byte tx_data, 0x15263748, spi_burst_send # place 4 frames into tx fifo
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.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.8byte sck_mode, 0x00000000, write32_test # flip polarity again
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.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.8byte rx_data, 0x00000048, read32_test
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.8byte rx_data, 0x00000037, read32_test
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.8byte rx_data, 0x00000026, read32_test
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.8byte rx_data, 0x00000015, read32_test #clear rx fifo
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# interlock in case where cs_mode = hold, intercs delay
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.8byte sck_mode, 0x00000000, write32_test # reset polarity
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.8byte delay1, 0x00010001, write32_test # set intercs delay to 1
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.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.8byte tx_data, 0x51627384, spi_burst_send # place 4 frames into tx fifo
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.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.8byte sck_mode, 0x00000000, write32_test # flip polarity again
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.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.8byte rx_data, 0x00000084, read32_test
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.8byte rx_data, 0x00000073, read32_test
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.8byte rx_data, 0x00000062, read32_test
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.8byte rx_data, 0x00000051, read32_test #clear rx fifo
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# repeat previous set of tests with cs_mode = off
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.8byte cs_mode, 0x00000003, write32_test # set cs_mode to hold
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.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.8byte tx_data, 0x13243546, spi_burst_send # place 4 frames into tx fifo
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.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.8byte sck_mode, 0x00000000, write32_test # flip polarity again
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.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.8byte rx_data, 0x00000046, read32_test
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.8byte rx_data, 0x00000035, read32_test
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.8byte rx_data, 0x00000024, read32_test
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.8byte rx_data, 0x00000013, read32_test #clear rx fifo
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# interlock in case where cs_mode = hold, intercs delay
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.8byte sck_mode, 0x00000000, write32_test # reset polarity
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.8byte delay1, 0x00000000, write32_test # set intercs delay to 0
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.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock
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.8byte tx_data, 0x31425364, spi_burst_send # place 4 frames into tx fifo
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.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame)
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.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end
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.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock
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.8byte sck_mode, 0x00000000, write32_test # flip polarity again
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.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame
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.8byte rx_data, 0x00000064, read32_test
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.8byte rx_data, 0x00000053, read32_test
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.8byte rx_data, 0x00000042, read32_test
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.8byte rx_data, 0x00000031, read32_test #clear rx fifo
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