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# Ignore editor backup files
*~
# Ignore transients generated by the tests
/.cproject
/.project
/work/
/setup.env
#ignore Mac file system artifacts
*.DS_Store
riscv-target/

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# CHANGELOG
## [2.5.3] - 2021-10-15
- fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests.
## [2.5.2] - 2021-10-14
- update format for aes32 and sm4 instructions
- update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified
- delete zip and unzip tests in rv64i_m/K_unratified
- update tests for aes64ks1i, sm4ed and sm4ks to use byte_count with overlap = "Y" to improve the coverage of S-boxes
## [2.5.1] - 2021-10-07
- added styles files to the F coverage report directories.
## [2.5.0] - 2021-10-01
- Added rv32f tests, references, coverage files and data propagation reports
- fixed broken links in READMEs across the repo.
- corrected string "EBREAK" in io string macro to "ECALL" for ecall.S tests. #207
- fixed typo `.alive` --> `.align` in `riscv-target/example_target/model_test.h`.
## [2.4.7] - 2021-10-01
- Fix for the issue #206
## [2.4.6] - 2021-08-02
- Added rv32e tests in riscv-test-suite
## [2.4.5] - 2021-07-29
- fix for issue #195
## [2.4.4] - 2021-07-19
- Annotating tags during releases
## [2.4.3] - 2021-05-20
- added new 64-bit K crypto tests as per the test-plan presented by the scalar crypto task group
[here](https://github.com/riscv/riscv-crypto/blob/d89dfee25780f79c162da4eb69cd9076dd701c88/tests/compliance/test-plan-scalar.adoc)
- added new 32-bit K crypto tests as per the above mentioned test-plan.
- added coverage and data propagation reports for the above tests.
- updated README in riscv-test-suite
- added missing semi-colon in example target Makefile.include files
## [2.4.2] - 2021-04-20
- changed all occurances of SPTBR to the new name SATP
## [2.4.1] - 2021-04-01
- updated issue number in TestFormatSpec to be consistent with doc history
- adding a contribution guideline
- updated comment on usage of RISCV_DEVICE in Makefile.include
- updated licenses that are currently used by tests
- renamed K tests to K_unratified
- updated ci to build and upload pdf for testformatspec
## [2.4.0] - 2021-03-26
2021-03-26 Duncan Graham <info@imperas.com>
- Added new K Crypto (scalar) (0.8.1) tests from Imperas
## [2.3.1] - 2021-03-20
### Changed
- Compliance Task Group changed to Architecture Test SIG in all docs and comments
- replacing old riscv-compliance link with new riscv-arch-test links
- fixed ci for release
### Removed
- spec/TestFormatSpec.pdf is removed since its old. Keeping only adoc file
- removing obsolete and commented out portions from doc/README
## [2.3] - 2021-03-11
### Added
- updated maintainers list in root-level readme
- updated the links to riscof, isac and ctg repos and docs in root-level readme
- adding CI to update versions automatically
### Removed
- replaced spike target with a REAMDE pointing to riscv-isa-sim/arch_test_target/README.md
## [2.2] - 2021-01-28
2021-01-22 Tobias Wölfel <tobias.woelfel@mailbox.org>
* Add missing base ISA check in riscv-test-suite
2021-01-20 Xiretza <xiretza@xiretza.xyz>
* Deduplicate makefiles in riscv-test-suite
* Makefile: Fix ordering of simulate and verify targets to allow multi-job runs (make -j)
* Makefile.include: Document RISCV_TEST
* Makefile: use $(TARGETDIR) variable for postverify target instead of hard-coded path
2021-01-16 S Pawan Kumar <spawan1999@gmail.com>
* Fixed NARGS macro defintion to work correctly.
2021-01-15 Xiretza <xiretza@xiretza.xyz>
* style: Add a missing space to the "OK" message in verify.sh
2020-12-17 Neel Gala <neelgala@incoresemi.com>
* remove env folder symlinks from all riscv-test-suite src folders
* fixed assertion macros for ovpsim
* renamed RVTEST_ASSERT to RVMODEL_ASSERT in the Makefile and ovpsim macros
* tests updated with right set of "correctvals"
2020-11-24 Neel Gala <neelgala@incoresemi.com>
* added MIGRATION.adoc in doc directory to indicate how old framework targets can work with
changes made as part of this PR
* updated doc/README.adoc to avoid the word "compliance" and updated the section on porting a new
target to the framework.
* Added an example_target directory to host dummy files which can be used as a starting point for
porting targets. This was provided by MarcKarasek.
* migrated/ported existing targets (except codasip and sifive-formal) to the new framework
changes.
* in riscv-test-env/p/riscv_test.h changed names of RVTEST_[CODE/DATA]_[BEGIN/END] to
RVTEST_[CODE/DATA]_[BEGIN/END]_OLD respectively to avoid conflicts with the new framework macros.
* in riscv-test-env/p/riscv_test.h re-strutucture RVTEST_DATA_BEGIN_OLD/END to ensure that all
target specific data contents are introduced in RVTEST_DATA_END after the signature.
* added new file riscv-test-suite/env/arch_test.h which contains the macros used by the new set of
tests. A symlink to this in the riscv-test-env directory is also created. The arch_test also
includes aliases for the old macros.
* encoding.h moved to riscv-test-suite/env and a symlink to this file exists in riscv-test-env.
This was done to ensure that the arch_test.h and encoding.h are not to be modified by the
targets
* Added riscv-test-stats which includes coverage and data propagation reports for the tests
available in the riscv-test-suite directory.
* upddted the directory structure of the riscv-test-suite as per definition found in the
TestFormatSpec document.
* new set of tests with better coverage for rv[32/64][I,M,C, Zifencei] added. Almost all tests
were generated using the open source riscv_ctg tool. A few tests like fence, fencei, ebreak,
ecall, etc were handwritten/modified to follow the new macro conventions.
* Updated TestFormatSpec to avoid the word compliance and also updated the definitions of macros
and signatures
* created a root-level Makefile.include to decouple the Makefile and target specific settings.
* Added riscv-target and Makefile.include to the .gitignore file to stop tracking target specific
changes.
* Added special targets for compile(build), simulate(run) and verify in the Makefiles of each
test-suite.
* the existing riscv-targets have been either updated for the new framework or migrated to the
framework.
2020-10-15 Simon Davidmann <simond@imperas.com>
* riscvOVPsim enhanced and moved to its own respository: github.com/riscv-ovpsim
2020-04-24 Allen Baum <allen.baum@esperantotech.com>
* fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account
of tests with negative offsets (which causes stores outside the signature area)
2020-03-19 Neel Gala <neelgala@gmail.com>
* restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable
tests.
* based on the above fixed the directory structure for riscv-targets where-ever applicable. Only
tested riscvOVPsim and spike.
* fixed script bugs for spike as well
* renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files
and Makefrag
* renamed mbadaddr csr to mtval as raised in issue #31
* C.SWSP-01.S test updated to fix issue #37
2020-03-18 Neel Gala <neelgala@gmail.com>
* fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile
2020-02-07 Prashanth Mundkur <prashanth.mundkur@gmail.com>
* Support F extension on RV32 sail-riscv-c.
2019-12-01 Allen Baum <allen.baum@esperantotech.com>
* modified macro names to conformn to riscof naming convention of model specific vs. pre-defined
* add more complete list of macros, their uses, parameters, and whether they are required or optional
* minor structural changes (moving sentences, renumbering) and typo fixes
* clarified impact of debug macros
* clarified how SIGUPD and BASEUPD must be used
* remove section about test taxonomy, binary tests, emulated ops
* clarify/fix boundary between test target and framework responsibilities
(split test target into test target and test shell)
* remove To Be discussed items that have been discussed
* remove default case condition; if conditions are unchanged, part of same case
* minor grammatical changes related to the above
2019-10-16 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range.
* more gramatical fixes, clarifications added
* added To Be Discussed items regarding emulated instruction and binary tests
2019-09-11 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: more grammar and typo corrections and changes
clarified and added To Be Discussed issues
2019-09-11 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: many grammar and typo corrections and changes
removed many "to Be Discussed items and made them official
Added wording to clarify spec intent (work in progress/goal rather than final)
Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE
Added detail on proposals for connection to framework (how framework selects tests).
Expanded definition of signature format
Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure
Added many "future work" items related to the above
Added examples and comments to code examples to indicate how proposed macros would be used
* .gitignore: added condition to ignore Mac file system artifacts
2019-11-05 Lee Moore <moore@imperas.com>
* Restructured RV32I to move Zicsr and Zifencei into their own suites
2019-10-14 Lee Moore <moore@imperas.com>
* Added Ability to run a single test by using the Make Variable RISCV_TEST
for example, to only run the test I-ADD-01 from the rv32i suite
make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01
* Added Top Level Variable to Makefile RISCV_TARGET_FLAGS,
in the case of the RISCV_TARGET this can be passed and appended to the invocation
commandline configuration, for example to pass a command line flag to the RISCV_TARGET
to perform tracing. The value of this flag will be target specific
make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace"
This is has also been added to all other targets to allow target configuration from
the commandline
2019-10-07 Philipp Wagner <phw@lowrisc.org>
* When executing the test suite, Ibex always writes an instruction
log. Update the Makefile to write it to a test-specific location
(next to all other log files).
* On Ibex, provide an additional .objdump-noalias disassembly file
with no aliases and numeric register names (instead of ABI names).
This file matches the Ibex trace and can be used to debug the test
runs.
2019-08-29 Robert Balas <balasr@iis.ee.ethz.ch>
* Added support for using RI5CY as a target.
* Added subdirectory riscv-target/ri5cy
2019-08-08 Lee Moore <moore@imperas.com>
* Added support for lowRISC/ibex RTL as a target using Verilator.
In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org
2019-07-18 Paul Donahue <pdonahue@ventanamicro.com>
* Fix typos/grammar and use correct architectural terms.
2019-06-21 Ben Selfridge <benselfridge@galois.com>
* Added support for using the the GRIFT simulator as a target.
* Added subdirectory riscv-target/grift
* updated README.md and doc/README.adoc
2019-05-23 Prashanth Mundkur <prashanth.mundkur@gmail.com>
* Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
* added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml
* updated README.md and doc/README.adoc
2019-04-05 Allen Baum <allen.baum@esperantotech.com>
* spec/TestFormatSpec.adoc: Adding details, minor corrections, ToBeDiscussed
items and clarifications to the specification of the future compliance test
suite. Also removing restrictions on having absolate addresses in signature
2019-02-21 Lee Moore <moore@imperas.com>
* Fixed bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0
* Corrected commit I-LUI-01.S, register target changed but missed assertion
2019-02-21 Deborah Soung <debs@sifive.com>
* added RiscvFormalSpec as a target with its own unique environment
2019-02-15 Radek Hajek <radek.hajek@codasip.com>
* updated rv32i tests to support all registers (x31) with assertions
* updated spec/TestFormatSpec.adoc example ISA test with new assertions
2019-02-05 Deborah Soung <debs@sifive.com>
* [Issue #33] fixing rv32si/ma_fetch.S test
* [Issue #32] fixing breakpoint test
2019-02-01 Lee Moore <moore@imperas.com>
* updated Infrastructure macros to support non-volatile registers
* updated riscvOVPsim
2019-01-29 Deborah Soung <debs@sifive.com>
* Added Rocket Chip generated cores as a target
* riscv-target/rocket/compliance_io.h created
* riscv-target/rocket/compliance_test.h created
* riscv-target/rocket/*/Makefile.include created for existing test suites
* README.adoc updated with instructions for using Rocket cores as targets
2019-01-22 Premysl Vaclavik <pvaclavik@codasip.com>
* feature: initial version of Compliance Test Format Specification
* This new document outlines how we should like the compliance
system to work going forward. By contrast the doc/README.adoc file
describes the current system as it is.
* Approved at Compliance TG meeting of 9 Jan 2019.
2019-01-02 Radek Hajek <radek.hajek@codasip.com>
* unified macros in all compliance tests
2018-12-20 Lee Moore <moore@imperas.com>
* fixed riscvOVPsim
2018-11-22 Simon Davidmann <simond@imperas.com>
* added information on test suite status
2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
* Added support for using external target directories with $TARGETDIR
2018-11-21 Neel Gala <neelgala@incoresemi.com>
* riscv-test-suite/rv_/references/_.reference_output: changed signature
format for all tests to include only 4-bytes per line starting with the
most significant byte on the left.
* riscv-target/spike/device/rv_/Makefile.include: Added a patch for
spike-device Makefiles where the old-signature format is post-processed
to generate a signature in the new format at the end of each test.
* riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above.
* Makefile: default target for Makefile is now to run all tests supported by
the target mentioned defined by RISCV_TARGET variable.
2018-10-11 Simon Davidmann <simond@imperas.com>
* Ported github riscv/riscv-tests for RV32 processors to this compliance env
* rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui
2018-09-10 Lee Moore <moore@imperas.com>
* Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to
identify untested usage cases
* Macro renames to support GPR, (S)FPR, (D)FPR
* Added test suite RV32IM to test 32 bit Multiply and Divide instructions
* Added test suite RV32IMC to test 32 bit Compressed instructions
* Added test suite RV64I to test 64 bit Integer instructions
* Added test suite RV64IM to test 64 bit Multiply and Divide instructions
2018-06-15 Radek Hajek <hajek@codasip.com>
Modifications to support Codasip simulator.
The simulator is renamed as Codasip-simulator (was
Codasip-IA-simulator), compliance_test.h has been moved to target
directories and a COMPILE_TARGET has been added to Makefile to
allow use of LLVM.
* Makefile: Include Codasip simulator target.
* riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as
riscv-target/Codasip-simulator/compliance_io.h.
* riscv-target/Codasip-simulator/compliance_io.h: Renamed from
riscv-target/codasip-IA-simulator/compliance_io.
* riscv-target/Codasip-simulator/compliance_test.h: Created.
* riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include:
Renamed as
riscv-target/Codasip-simulator/device/rv32i/Makefile.include
* riscv-target/Codasip-simulator/device/rv32i/Makefile.include:
Renamed from
riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include.
* riscv-test-env/compliance_test.h: Renamed as
riscv-target/riscvOVPsim/compliance_test.h.
* riscv-target/riscvOVPsim/compliance_test.h: Renamed from
riscv-test-env/compliance_test.h.
* riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated
for new environment.
* riscv-target/spike/compliance_test.h: Created.
* riscv-target/spike/device/rv32i/Makefile.include: Updated for
new environment.
* riscv-test-suite/rv32i/Makefile: Likewise.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
Put placeholders in empty directories to make sure they show in
the GitHub hierarchy.
* riscv-test-suite/rv32i/.gitignore: Created.
* riscv-test-suite/rv32m/.gitignore: Created.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Make references to files in the repo into links.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Ignore editor backup files.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Add better link to documentation README.md.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Move AsciiDoc details into new README.md in the doc
directory.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Fix typo in link to AsciiDoc cheat sheet
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* COPYING.BSD: Created.
* COPYING.CC: Created.
* README.md: Add git process, licensing and engineering process.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Correct details for running the compliance tests and
directory for OVPsim.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
Clean restructuring to just the work of interest.
* thought-experiments: Directory removed.
* .gitignore: Merged with TestStructure/.gitignore
* Makefile: Renamed from TestStructure/Makefile.
* TestStructure/Makefile: Renamed as Makefile.
* README.md: Merged with TestStructure/README.md.
* TestStructure/.gitignore: Deleted and contents moved into
.gitignore.
* TestStructure/README.md: Deleted and contents moved into
README.md.
* TestStructure/doc: Directory deleted.
* TestStructure/riscv-target: Directory moved to riscv-target.
* riscv-target: Directory moved from TestStructure/riscv-target
* TestStructure/riscv-test-env: Directory moved to riscv-test-env.
* riscv-test-env: Directory moved from
TestStructure/riscv-test-env.
* TestStructure/riscv-test-suite: Directory moved to
riscv-test-suite.
* riscv-test-suite: Directory moved from
TestStructure/riscv-test-suite.
* thought-experiments: Directory deleted.
2018-05-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Initial commit to populate the repository.
* ChangeLog: Created.
* README.md: Created.

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# Contributing to RISC-V Architecture Tests
Your inputs are welcome and greatly appreciated! We want to make contributing to this project as easy and transparent as possible, whether it's:
- Reporting a bug
- Discussing the current state of the code
- Submitting a fix
- Proposing new features
- Becoming a maintainer
## We develop with Github
We use github to host code, to track issues and feature requests, as well as accept pull requests.
## We use a simple git flow where all code changes happen through Pull Requests
Pull requests are the best way to propose changes to the codebase. We actively welcome your pull requests:
1. Fork the repo and create your branch from `master`.
2. If you have added new tests, please ensure they adhere to the latest TestFormatSpec and that you have run them on the RVI approved reference
models (if support in those models is available).
3. If you have updated any test-macros make sure to update the documentation as well.
4. If you have updated the docs, ensure that they render correctly in the respective format.
5. Make sure to create an entry in the CHANGELOG.md. Please refer to the section on versioning below
to choose an appropriate version number.
6. Ensure the existing tests are not broken and still pass on the the RVI approved reference models.
7. Please include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
8. Issue that pull request!
## Versioning
When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to
the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must
be followed while assigning a new version number :
- Patch-updates: all doc updates (like typos, more clarification,etc) and updates to unratified extensions.
- Minor-updates: Updates to ratified extensions OR migration of extensions to ratified OR changes in docs regarding policies or spec.
- Major-updates: Changes to the framework flow (backward compatible or incompatible).
Note: You can have either a patch or minor or major update.
Note: In case of a conflict, the maintainers will decide the final version to be assigned.
## Any contributions you make will be under the permissive open-source License
In short, when you submit code changes, your submissions are understood to be under a permissive open source license like BSD-3, Apache-2.0 and CC, etc that covers the project. Feel free to contact the maintainers if that's a concern.
## Report bugs using Github's [issues](https://github.com/riscv/riscv-arch-test/issues)
We use GitHub issues to track public bugs. Report a bug by [opening a new issue](https://github.com/riscv/riscv-arch-test/issues/new); it's that easy!
## Write bug reports with detail, background, and sample code
**Great Bug Reports** tend to have:
- A quick summary and/or background
- Steps to reproduce
- Be specific!
- Give sample code if you can.
- What you expected would happen
- What actually happens
- Notes (possibly including why you think this might be happening, or stuff you tried that didn't work)
## License
By contributing, you agree that your contributions will be licensed under its permissive open source
licenses.

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#
# Ensure the compiler and necessary executables are on the search PATH
#
#
# Ensure you have set the following Variables
#
#
export ROOTDIR = $(shell pwd)
export WORK ?= $(ROOTDIR)/work
include Makefile.include
pipe:= |
empty:=
comma:= ,
space:= $(empty) $(empty)
RISCV_ISA_ALL = $(shell ls $(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m)
RISCV_ISA_OPT = $(subst $(space),$(pipe),$(RISCV_ISA_ALL))
RISCV_ISA_ALL := $(filter-out Makefile.include,$(RISCV_ISA_ALL))
ifeq ($(RISCV_DEVICE),)
RISCV_DEVICE = I
DEFAULT_TARGET=all_variant
else
DEFAULT_TARGET=variant
endif
export SUITEDIR = $(ROOTDIR)/riscv-test-suite/rv$(XLEN)i_m/$(RISCV_DEVICE)
$(info )
$(info ============================ VARIABLE INFO ==================================)
$(info ROOTDIR: ${ROOTDIR} [origin: $(origin ROOTDIR)])
$(info WORK: ${WORK} [origin: $(origin WORK)])
$(info TARGETDIR: ${TARGETDIR} [origin: $(origin TARGETDIR)])
$(info RISCV_TARGET: ${RISCV_TARGET} [origin: $(origin RISCV_TARGET)])
$(info XLEN: ${XLEN} [origin: $(origin XLEN)])
$(info RISCV_DEVICE: ${RISCV_DEVICE} [origin: $(origin RISCV_DEVICE)])
$(info =============================================================================)
$(info )
RVTEST_DEFINES =
ifeq ($(RISCV_ASSERT),1)
RVTEST_DEFINES += -DRVMODEL_ASSERT
endif
export RVTEST_DEFINES
VERBOSE ?= 0
ifeq ($(VERBOSE),1)
export V=
export REDIR1 =
export REDIR2 =
else
export V=@
export REDIR1 = 1>/dev/null
export REDIR2 = 2>/dev/null
endif
default: $(DEFAULT_TARGET)
variant: simulate verify
all_variant:
@for isa in $(RISCV_ISA_ALL); do \
$(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa variant; \
rc=$$?; \
if [ $$rc -ne 0 ]; then \
exit $$rc; \
fi \
done
build: compile
run: simulate
clean_all: clean
compile:
$(MAKE) $(JOBS) \
RISCV_TARGET=$(RISCV_TARGET) \
RISCV_DEVICE=$(RISCV_DEVICE) \
compile -C $(SUITEDIR)
simulate:
$(MAKE) $(JOBS) \
RISCV_TARGET=$(RISCV_TARGET) \
RISCV_DEVICE=$(RISCV_DEVICE) \
run -C $(SUITEDIR)
verify: simulate
riscv-test-env/verify.sh
postverify:
ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
$(info No post verify script found $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh)
else
$(TARGETDIR)/$(RISCV_TARGET)/postverify.sh
endif
clean:
$(MAKE) $(JOBS) \
RISCV_TARGET=$(RISCV_TARGET) \
RISCV_DEVICE=$(RISCV_DEVICE) \
clean -C $(SUITEDIR)
help:
@echo "RISC-V Architectural Tests"
@echo ""
@echo " Makefile Environment Variables to be set per Target"
@echo " -- TARGETDIR='<directory containing the target folder>'"
@echo " -- XLEN='<make supported xlen>'"
@echo " -- RISCV_TARGET='<name of target>'"
@echo " -- RISCV_TARGET_FLAGS='<any flags to be passed to target>'"
@echo " -- RISCV_DEVICE='$(RISCV_ISA_OPT)' [ leave empty to run all devices ]"
@echo " -- RISCV_TEST='<name of the test. eg. I-ADD-01'"
@echo " "
@echo " Makefile targets available"
@echo " -- build: To compile all the tests within the RISCV_DEVICE suite and generate the elfs. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
@echo " -- run: To run compiled tests on the target model and generate signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
@echo " -- verify: To verify if the generated signatures match the corresponding reference signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
@echo " -- postverify: To run post verification processing for a target, for example with this, riscvOVPsim runs instructional functional coverage on the tests"
@echo " -- clean : removes the working directory from the root folder and also from the respective device folders of the target"
@echo " -- default: build, run, and verify on all devices enabled"

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# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target
#export TARGETDIR ?= ~/riscv-wally/addins/riscv-isa-sim/arch_test_target
export RISCV_PREFIX = riscv64-unknown-elf-
# set XLEN to max supported XLEN. Allowed values are 32 and 64
export XLEN ?= 64
# name of the target. Note a folder of the same name must exist in the TARGETDIR directory
export RISCV_TARGET ?= spike
# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify.
# Leave this blank if you want to iterate through all the supported extensions available in the target
export RISCV_DEVICE ?=
# set this to a string which needs to be passed to your target Makefile.include files
export RISCV_TARGET_FLAGS ?=
# set this if you want to enable assertions on the test-suites. Currently no tests support
# assertions.
export RISCV_ASSERT ?= 0
# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure
# that no common files across jobs are created/overwritten leading to unknown behavior
JOBS= -j1

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# RISC-V Architecture Test SIG
This is a repository for the work of the RISC-V Foundation Architecture Test SIG. The repository owners are:
- Neel Gala (InCore Semiconductors)
- Marc Karasek (Inspire Semiconductors)
Details of the RISC-V Foundation, the work of its task groups, and how to become a member can be found at [riscv.org](https://riscv.org/).
For more details and documentation on the current testing framework see: [doc/README.adoc](doc/README.adoc)
For more details on the test format spec see: [spec/TestFormatSpec.adoc](spec/TestFormatSpec.adoc)
For contributions and reporting issues please refer to [CONTRIBUTION.md](CONTRIBUTION.md)
## Test Disclaimers
The following are the exhaustive list of disclaimers that can be used as waivers by target owners
when reporting the status of pass/fail on the execution of the architectural suite on their respective targets.
1. The references uploaded for the following misaligned load/store tests will match targets which do
not support misaligned load/stores in hardware. Targets with hardware misaligned support for
load/stores will fail these tests.
1. rv32i_m/privilege/src/misalign-[lb[u],lh[u],lw,sh,sb,sw]-01.S
2. rv64i_m/privilege/src/misalign-[lb[u],lh[u],lw[u],ld,sb,sh,sw,sd]-01.S
2. The references uploaded for the following misaligned instruction tests will match targets which
have compressed extension support enabled by default. Targets without the compressed extension
support will fail the following tests:
1. rv[32/64]i_m/privilege/src/misalign-b[ge[u],lt[u],eq,ne]-01.S
2. rv[32/64]i_m/privilege/src/misalign[1,2]-jalr-01.S
3. The machine mode trap handler used in the privilege tests assumes one of the following conditions.
Targets not satisfying any of the following conditions are bound to fail the entire
rv32i_m/privilege and rv64i_m/privilege tests:
1. The target must have implemented mtvec which is completely writable by the test in machine mode.
2. The target has initialized mtvec, before entering the test (via RVMODEL_BOOT), to point to a memory location which has both read and write permissions.
## Contribution process
Please refer to to [CONTRIBUTION.md](CONTRIBUTION.md) for guidelines on contributions.
## Licensing
In general:
- code is licensed under one of the following:
- the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`);
- the Apache License (SPDX license identifier `Apache-2.0`); while
- documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`).
The files [`COPYING.BSD`](./COPYING.BSD), [`COPYING.APACHE`](./COPYING.APACHE) and [`COPYING.CC`](./COPYING.CC) in the top level directory contain the complete text of these licenses.
## Engineering practice
- Documentation uses the structured text format _AsciiDoc_. See [`doc/README.adoc`](doc/README.adoc) for more details.
- Some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message.
- Please include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
## Quick Links:
- RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\] \[[REPO](https://github.com/riscv-software-src/riscof)\]: This is the next version of the architectural test framework currently under development
- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\] \[[REPO](https://github.com/riscv-software-src/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
- [Videos](https://youtu.be/VIW1or1Oubo): This Global Forum 2020 video provides an introduction to the above mentioned tools
- [riscvOVPsim](https://github.com/riscv-ovpsim/imperas-riscv-tests): Imperas freeware RISC-V reference simulator for compliance testing
- [riscvOVPsimPlus](https://www.ovpworld.org/riscvOVPsimPlus/): Imperas enhanced freeware RISC-V reference simulator for test development and verification

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# Ignore editor backups
*~
# Generated files
custom.dict
README.pdf
README.html

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@ -0,0 +1,147 @@
2019-02-21 Deborah Soung <debs@sifive.com>
* README.adoc: Documentation for rocket chip as target.
2019-02-05 Deborah Soung <debs@sifive.com>
* README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S).
* README.adoc: Update documentation for rocket chip as target (fixed breakpoint.S).
2019-01-29 Deborah Soung <debs@sifive.com>
* README.adoc: Documentation for rocket chip as target.
2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
* README.adoc (Repository structure) Added documentation for the $TARGETDIR environmental variable
2018-11-21 Neel Gala <neelgala@incoresemi.com>
* README.adoc: Added new signature format spec.
2018-06-18 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.adoc (Future work): Reflect changes made to support
Codasip simulator.
(Repository structure): Diagrammatic representation of the file
structure deleted.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Add custom.dict.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
Document issue 1.8 Draft.
* README.adoc (Introduction): Add Future work section and bump
version.
* custom.wordlist: Add words needed for Future work section.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.adoc: Remove special apostrophe from "licensor's".
* custom.wordlist: Updated with more words to be ignored.
2018-06-12 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README-old.md: Deleted.
* README.adoc: Include details of how to contribute and installing
the tools from the old README and reference the licence as an
appendix.
2018-06-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
This makes the document appear directly as the README of the doc
directory, so there is now no longer a need to publish to GitHub
pages.
* .gitignore: Change name of files ignored.
* Makefile: Remove publish target.
* README.adoc: Symbolic link removed and replaced by design.adoc,
to which the CC license text has been added.
* design.adoc: Renamed as README.adoc.
* publish.sh: Deleted.
2018-06-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Previous version moved to README-old.md for the time
being.
* README.adoc: Created as symbolic link to design.adoc.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Note about make publish.
* design.adoc (Overall structure): Make list or instruction sets
and extensions compact representation.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Only publish from clean and committed master branch
to avoid difficult use of git stash.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Don't rely on doc directory being available on
gh-pages branch.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* publish.sh: Make executable and correctly set top level
repository directory.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
Add a mechanism to make the latest documentation available via
GitHub pages. This means that design.html is no longer part of
the master branch, but is published by copying to index.html on
the gh-pages branch.
* .gitignore: Ignore design.html.
* Makefile: Add publish target and delete design.html when cleaning.
* README.md: Link to GitHub pages for latest documentation.
* design.adoc: Deal with AsciiDoc apparent bug with consecutive
comment blogs.
* design.html: Deleted.
* publish.sh: Created.
2018-06-10 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Fix link to generated documentation.
* design.html: Regenerated.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* Makefile: Add sanity check for version number and spell target.
* design.adoc: Fix trivial typo.
* design.html: Regenerated.
2018-06-09 Jeremy Bennett <jeremy.bennett@embecosm.com>
* .gitignore: Don't ignore .html or .xml
* README.md: Note location of old documentation, give link to HTML
and explain how to contribute.
* custom.wordlist: Created.
* design.adoc: Cleaned up from top to bottom and spell checked.
* design.html: Generated.
2018-06-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* Makefile: Clean up and add license header.
* README.md: Created.
* design.adoc: Add licensing and SPDX license identifier.
* legacy.adoc: Deleted.
2018-06-04 Jeremy Bennett <jeremy.bennett@embecosm.com>
This is the first version of the document taken from Simon
Davidmann's MS Word document. The main document is design.adoc,
legacy material, currently just appendices C and D has been moved
to legacy.adoc.
design.adoc is correct AsciiDoc. legacy.adoc is just a raw dump,
which needs cleaning up.
The next step will be restructuring design.adoc as agreed.
* .gitignore: Created.
* ChangeLog: Created.
* Makefile: Created.
* design.adoc: Created.
* legacy.adoc: Created.

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= Migration guide
:toc:
:icons: font
:numbered:
:source-highlighter: rouge
This document serves as a guide to users of the architectural suite to migrate their targets from an
older version to a newer version with minimal changes. This guide thus provides a patch scheme to get
the previous versions of the targets up and running with the new versions of the framework.
However, users are strongly encouraged to completely migrate to the newer versions, as and when
available, and avoid using these patches.
== Migration from v0.1 to v0.2
This section will describe the changes required to transition your targets ported on v0.1 to v0.2
framework. For examples please see: `riscv-target/riscvOVPsim_0p1` and `riscv-target/spike_0p1`.
=== Change header filename
In version v0.1 the target specific assembly macros were split across two files: `compliance_test.h`
and `compliance_io.h`. In version v0.2 these macros are to merged into a single file named
`model_test.h`. The following commands can the achieve the above:
----
mv compliance_test.h model_test.h
cat compliance_io.h >> model_test.h
rm compliance_io.h
----
=== Change device directory structure
In version v0.1 a target would have one or multiple of the directories defined to indicate supported
extensions: `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei`. In version v0.2 the
directories of the extensions have changed in order to provide more consistency and less ambiguity.
For version v0.2, the `device` directory first needs to have either a `rv32i_m` directory to indicate
that the target is a 32-bit machine. The extension directories, as supported by the target, are
now to be created in each of these directories using the following mapping scheme:
. device/rv32i -> device/rv32i_m/I
. device/rv32im -> device/rv32i_m/M
. device/rv32imc -> device/rv32i_m/C
. device/rv32Zicsr -> device/rv32i_m/privilege
. device/rv32Zifencei -> device/rv32i_m/Zifencei
The contents of the extension directories need not change, unless there are dependencies on the path
of the directory itself. The following commands will achieve the above:
----
cd device
mkdir rv32i_m
mv rv32i rv32i_m/I
mv rv32im rv32i_m/M
mv rv32imc rv32i_m/C
mv rv32Zicsr rv32i_m/privilege
mv rv32Zifencei rv32i_m/Zifencei
----
=== Changes in target macro names.
Since some of the macros from the old framework have been re-purposed in the new v0.2 framework,
there will be name conflicts rendering the old ones useless. In order to retain the old macros, they
have been renamed with a post-fix `_OLD`. The macros that have been renamed are given below:
. `RVTEST_CODE_BEGIN` -> `RVTEST_CODE_BEGIN_OLD`
. `RVTEST_CODE_END` -> `RVTEST_CODE_END_OLD`
. `RVTEST_DATA_BEGIN` -> `RVTEST_DATA_BEGIN_OLD`
. `RVTEST_DATA_END` -> `RVTEST_DATA_END_OLD`
The user is thus required to make the above changes in the new `model_test.h` that was created
as part of this migration. The following commands will help achieve the above:
----
sed -i 's/RVTEST_CODE_BEGIN/RVTEST_CODE_BEGIN_OLD/g' model_test.h
sed -i 's/RVTEST_CODE_END/RVTEST_CODE_END_OLD/g' model_test.h
sed -i 's/RVTEST_DATA_BEGIN/RVTEST_DATA_BEGIN_OLD/g' model_test.h
sed -i 's/RVTEST_DATA_END/RVTEST_DATA_END_OLD/g' model_test.h
----
note:: the RVTEST_DATA_END in v0.1 enforced a 16-byte alignment before the signature end. This
constraint has been removed.
=== Changes in device Makefile.include files
No changes required.

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# Makefile for RISC-V Architectural Test SIG documentation
# This file is part of the RISC-V Foundation Architectural Test SIG
# tool set and documentation.
# Copyright (C) 2017 CodaSip Limited <www.codasip.com>
# Copyright (C) 2018 Embecosm Limited <www.embecosm.com>.
# Copyright (C) 2018 Imperas Limited <www.imperas.com>
# All rights reserved.
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of mosquitto nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
# SPDX-License-Identifier: BSD-3-Clause
ROOT = README
SRC = $(ROOT).adoc
SRC_STRIPPED = $(ROOT)-stripped.adoc
.PHONY: all
all: pdf html
.PHONY: pdf
pdf: $(ROOT).pdf
$(ROOT).pdf: sanity-check $(SRC)
asciidoctor-pdf -d article $(SRC)
.PHONY: html
html: $(ROOT).html
$(ROOT).html: sanity-check $(SRC)
asciidoctor -d article -b html $(SRC)
# It is all too easy for the document history and title page to have diverging
# version numbers. This target checks first.
.PHONY: sanity-check
sanity-check:
@s=$$(sed -n < $(SRC) -e '3s/Issue //p') ; \
t=$$(sed -n < $(SRC) -e "/== Document history/,/^$$/p" | \
grep -c "$${s}") ; \
if [ $${t} -ne 1 ] ; \
then \
echo "Version number of title and document history do not match" ; \
exit 1 ; \
fi
custom.dict: custom.wordlist
aspell --lang=en create master ./$@ < $<
.PHONY: spell
spell: custom.dict $(SRC)
sed < $(SRC) > $(SRC_STRIPPED) -e 's/`[^`]\+`//gp' -e '/^----$$/,/^----$$/d'
aspell --master=en_US --mode=none --add-extra-dicts=./custom.dict \
-c $(SRC_STRIPPED)
$(RM) $(SRC_STRIPPED)
clean:
rm -f $(ROOT)-stripped.adoc $(ROOT).pdf $(ROOT).html custom.dict

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= RISC-V Architectural Testing Framework =
RISC-V Foundation Architecture Test SIG
Issue 1.16 Draft
:toc:
:icons: font
:numbered:
:source-highlighter: rouge
////
SPDX-License-Identifier: CC-BY-4.0
Document conventions:
- one line per paragraph (don't fill lines - this makes changes clearer)
- Wikipedia heading conventions (First word only capitalized)
- US spelling throughout.
- Run "make spell" before committing changes.
- Build the HTML and commit it with any changed source.
- Do not commit the PDF!
////
== Introduction
=== About
This document describes the RISC-V Architectural Testing framework which is used to test if a RISC-V device's has understood and implemented the specifications correctly
* It explains the framework around the tests, the running of individual tests, and the suites of tests.
* It explains how to set up targets to run the tests.
This document is made freely available under a <<app_cc_by_4.0>>.
=== Intent of the architectural test suite
The RISC-V Architectural Tests are an evolving set of tests that are created to help ensure that software written for a given RISC-V Profile/Specification will run on all implementations that comply with that profile.
These tests also help ensure that the implementer has both understood and implemented the specification correctly.
The RISC-V Architectural Test suite is a minimal filter. Passing the tests and having the results approved by RISC-V International is a prerequisite to licensing the RISC-V trademarks in connection with the design. Passing the RISC-V Architectural Tests does not mean that the design complies with the RISC-V Architecture. These are only a basic set of tests checking important aspects of the specification without focusing on details.
The RISC-V Architectural Tests are not a substitute for rigorous design verification.
The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant.
=== Intended audience
This document is intended for design and verification engineers who wish to check if their RISC-V implementation (simulation models, HDL models, etc.) is compliant to the RISC-V specification.
For those who wish to develop new architectural tests and/or to write or adapt their own test framework are suggested to read the link:../spec/TestFormatSpec.adoc[`Test Format Spec`].
=== Contribute
You are encouraged to contribute to this repository (including changes to this document) by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory.
While submitting a pull request note that some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message.
Make sure to also include a comment with the SPDX license identifier in all source files, for example:
```
// SPDX-License-Identifier: BSD-3-Clause
```
NOTE: Don't forget to add your own name to the list of contributors in the document.
== Licensing
In general:
* code is licensed under the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`);
* documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`).
The files link:../COPYING.BSD[`COPYING.BSD`] and link:../COPYING.CC[`COPYING.CC`] in the top level directory contain the complete text of these licenses.
NOTE: The riscv-ovpsim simulator is licensed under an Imperas license. There is no dependency on this and it is included as a convenience to users.
==== AsciiDoc
This is a structured text format used by this document. Simple usage should be fairly self evident.
* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website].
* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website].
* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful.
==== Installing tools
To generate the documentation as HTML you need _asciidoctor_ and to generate as
PDF you need _asciidoctor-pdf_.
* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor].
* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf].
To spell check you need _aspell_ installed.
==== Building the documentation
To build HTML:
[source,make]
----
make html
----
To build PDF:
[source,make]
----
make pdf
----
To build both:
[source,make]
----
make
----
To check the spelling (excludes any listing or code phrases):
[source,make]
----
make spell
----
Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`].
=== Contributors
This document has been created by the following people (in alphabetical order of surname).
* Jeremy Bennett
* Mary Bennett
* Simon Davidmann
* Neel Gala
* Radek Hajek
* Lee Moore
* Milan Nostersky
* Marcela Zachariasova
=== Document history
[cols="<1,<2,<3,<4",options="header,pagewidth",]
|================================================================================
| _Revision_ | _Date_ | _Author_ | _Modification_
| 1.16 Draft | 23 September 2020 | Neel Gala| Changed Compliance to Architecture/Architectural. Refined the steps to port a new target. Removed simulator and target specific docs. Added vocabulary from the Test Format Specification
| 1.15 Draft | 14 March 2019 |
Prashanth Mundkur |
Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
| 1.14 Draft | 21 February 2019 |
Deborah Soung |
Documented how to use SiFive's RISC-V ISA Formal Specification model as a target.
| 1.13 Draft | 29 January 2019 |
Deborah Soung |
Added documentation on how to use Rocket Chip generated cores as targets.
| 1.12 Draft | 22 November 2018 |
Simon Davidmann |
Updated notes on Test Suites.
| 1.11 Draft | 21 November 2018 |
Neel Gala |
Added new signature format specs .
| 1.10 Draft | 20 June 2018 |
Simon Davidmann, Lee Moore |
Cleaned up description of updated framework and inclusion of riscvOVPsim.
| 1.9 Draft | 12 June 2018 |
Jeremy Bennett |
Update Future work section to take account of Codasip changes. Remove diagrammatic directory structure.
| 1.8 Draft | 12 June 2018 |
Jeremy Bennett |
Add Future work section.
| 1.7 Draft | 12 June 2018 |
Jeremy Bennett |
Add CC license as an appendix.
| 1.6 Draft | 10 June 2018 |
Jeremy Bennett |
Tidy up areas that are flawed in HTML version.
| 1.5 Draft | 8 June 2018 |
Jeremy Bennett |
General tidy up.
| 1.4 Draft | 8 June 2018 |
Jeremy Bennett |
Added license preamble.
| 1.3 Draft | 5 June 2018 |
Simon Davidmann |
Updated to reflect directory structure and trace macros.
| 1.2 Draft | 3 June 2018 |
Jeremy Bennett |
Converted to AsciiDoc, cleaned up and restructured.
| 1.1 Draft | 1 June 2018 |
Simon Davidmann
Lee Moore |
Revised format and expand to describe framework, usage of many tests groups,
and different Targets
|1.0 | 24 December 2017 |
Radek Hajek
Milan Nostersky
Marcela Zachariasova |
First version of the document.
|================================================================================
== Repository structure
The top level directory contains :
- a `README.md` file providing high-level details about the RISC-V Architecture Testing Framework.
- top level `Makefile` for running the tests on a RISC-V implementation.
- `ChangeLog` for logging changes with respect to code.
- complete license files for the Creative Commons and BSD licenses used by the task group.
There are then five top level directories.
`doc`:: All the documentation for the project, written using _AsciiDoc_.
`coverage`:: This directory contains a sub-directory structure similar to the `riscv-test-suite` directory. The coverage reports of each test-suite are available in the corresponding directories. The reports are available in the html and yaml formats. The directory also contains multiple coverpoint YAMLs which capture all the coverpoints of interest which are covered by all the tests in the `riscv-test-suite` directory.
`riscv-target`:: Contains a further subdirectory for each target, within which are placed the `model_test.h` header for that target and a `device` directory for all the devices of that target. If the `$TARGETDIR` environment variable is set to another directory, the scripts will search this directory for targets instead.
`riscv-test-env`:: This contains the `verify.sh` script which checks if the signatures generated the riscv-target device match the statically hosted reference signatures at the end of simulation. The directory also contains symbolic-links to the `arch_test.h` and `encoding.h` files present in the `riscv-test-suite/env` directory.
`riscv-test-suite`:: This contains a further `env` subdirectory which contains the `arch_test.h` and the `encoding.h` file which includes common assembly macros and routines which is used across the tests in the suite. Further directories are present which contain the actual architectural tests. The names and structure of these directories is based on the link:../test-pool structure guideline highlighted above.
`riscv-ovpsim`:: This contains a README pointing to the Imperas OVP riscvOVPsim simulator for use in architectural testing.
== Vocabulary
=== The architectural test
At the heart of the testing infrastructure is the detailed <<The architectural tests, _architectural test_>> available as `.S` assembly files. The specification and format of the tests is defined in the link:./TestFormatSpec.adoc[`Test Format Specification`].
=== The architectural test pool
The <<The architectural test, _architectural tests_>> are grouped into different functional test suites targeting the different subsets of the RISC-V specification. For more details on the test-pool structure, hierarchy and conventions please refer to the link:./TestFormatSpec.adoc[`Test Format Specification`].
For information on the currently supported different test suites, look here: link:../riscv-test-suite/README.md[../riscv-test-suite/README.md]
=== The test signature
Each test in the <<The architectural test pool, _architectural test pool_>> generates a <<The test signature, _test signature_>>, which represents the data written into specific memory locations during the execution of the test. The signature typically will record values (or sanitised values) of the operations carried out in the test. More details on the format and nature of the signatures is available in the link:./TestFormatSpec.adoc[`Test Format Specification`]
=== The reference signature
In order to claim that a device/implementation has passed the RISC-V Architecture Tests, the <<The test signature, _test signatures_>> obtained from the execution of the tests on the implementation need to be compared against a set of _golden_ <<The reference signatures, _reference signature_>>. These reference signatures are currently generated by the link:https://github.com/rems-project/sail-riscv[`RISC-V SAIL`] formal model and statically hosted in the repository for each test.
=== The test target
The <<The test target,_test target_>> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the <<The target shell, _target shell_>> to handle different targets while using the same <<The architectural test pool,_architectural test pool_>> as a test source.
=== The target shell
The <<The target shell, _target shell_>> is the software and hardware environment around the <<The test target,_test target_>> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <<The target shell, _target shell_>> is a .S <<The architectural test,_architectural test_>> file, and the output is a <<The test signature,_test signature_>>.
== Porting a new target
In this section, a short tutorial on how to add a user target to the RISC-V Architectural Test Framework is provided.
The following steps demonstrate an example in which a target was replaced by the RISCV-ISA-SIM
(a.k.a Spike). In a similar way, any RISC-V ISA simulator or any RTL simulation model of the
RISC-V processor can be ported as a potential target for testing.
=== Setup environment variables
NOTE: `ROOTDIR` will always point to the riscv-arch-test repo.
1. Clone the repository:
---
git clone https://github.com/riscv/riscv-arch-test.git
cd riscv-arch-test
---
2. Open the `Makefile.include` available in the root folder of the repository and edit the following
variables based on your target:
a. `TARGETDIR` : set `TARGETDIR` to point to the directory which contains a sub-folder in the same name
as the target. For example, the arch-test repo includes the targets: sail-riscv-c and spike
under the `riscv-target` folder, in which case we set the `TARGETDIR` to riscv-target as shown
below. One can set this completely arbitrary paths as suitable by the user.
---
export TARGETDIR ?= $(ROOTDIR)/riscv-target
---
b. `XLEN`: set XLEN to max supported XLEN. Allowed values are 32 and 64.
---
export XLEN ?= 64
---
c. `RISCV_TARGET`: set this variable to the name of the target. A folder of the same name must exist in
the `TARGETDIR` directory
---
export RISCV_TARGET ?= spike
---
d. `RISCV_DEVICE`: set the `RISCV_DEVICE` environment to the extension you want to compile, simulate and verify. Leave
this blank if you want to iterate through all the supported extensions of the target. Allowed values
are the individual names of the extensions supported by your target like: I, M, C or Zifencei, etc. Multiple extensions are not be provided.
---
export RISCV_DEVICE ?=
---
e. `RISCV_TARGET_FLAGS`: set this to a string which needs to be passed to your target's Makefile.include files
---
export RISCV_TARGET_FLAGS ?=
---
f. `RISCV_ASSERT`: set this if you want to enable assertions on the test-suites. **Currently no tests use assertions.**
---
export RISCV_ASSERT ?= 0
---
g. `JOBS`: set the number of parallel jobs (along with any other arguments) you would like to
execute. Note that the target needs to be coded in such a way to support parallel execution. Some
targets use common intermediate files, rather than unique files, which makes them unsuitable for
parallel execution, these targets will need to be re-coded.
---
JOBS= -j1
---
3. Now inside your `TARGETDIR/RISCV_TARGET` directory you will need to create the following files:
a. `model_test.h`: A header file containing the definition of the various target specific
assembly macros that are required to compile and simulate the tests. The list and definition of the
required target specific macros is available in the link:../spec/TestFormatSpec.adoc[Test Format
Specification]
b. `link.ld`: A linker script to compile the tests for your target.
c. Any other files required by the target (configuration scripts, logs, etc.) can also be placed in
this directory.
4. Inside the `TARGETDIR/RISCV_TARGET` directory create a new folder named: `device`. If your device
is a 32-bit target then create a directory `device/rv32i_m`. If your device is a 64-bit target then
create a directory `device/rv64i_m`. If your target is configurable on the `XLEN` parameter then
both the folders need to be created.
5. Within the `rv32i_m`/`rv64i_m` directories sub-folders in the name of the extensions supported
by the target need to be created. For eg. A target supporting the ISA RV32IMC_Zifence will have the
following directory structure:
---
- rv32i_m/I
- rv32i_m/M
- rv32i_m/C
- rv32i_m/privilege
- rv32i_m/Zifencei
---
6. Each of the above extension directories will now need to include a file: `Makefile.include` which
defines the following Makefile variables:
a. `RUN_TARGET`:: This variable needs to include commands and steps to execute an ELF on target device. Note here that this variable should include all the necessary steps and arguments to run that specific test-suite. For example, in case of spike for the `rv32i_m/C` test-suite the corresponding `Makefile.include` has the `--isa=rv32ic` argument as opposed to just `--isa=rv32i` for the base `rv32i_m/I` test-suite. This variable should also include other steps to extract and sanitize the signature file as well for each test. The only argument available to this variable is the compiled `elf` file.
b. `COMPILE_TARGET`:: This variable should include the commands and steps required to compile an assembly test for the target for each extension mentioned above. Note, currently only the GCC compiler is supported. This compiler takes `march` and `mabi` arguments from the corresponding architectural suite framework. `COMPILE_TARGET` will more or less be the same across test-suites. The only argument available to `COMPILE_TARGET` is the assembly file of one architectural test.
The following figure depicts the final directory structure of a target device that should get created at the end of the above steps:
[#img-testStruct]
.File Structure of the Target directory
image::./file-struct.jpg[TargetStruct]
=== Generating Signature
As previously mentioned the execution of each test on the target must generate a signature file. The name of the signature file should be `<test-file-name.signature_output>`. The signature file should follow the guidelines mentioned in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`].
In case of spike, we have ensured that the signature region is bounded by the labels: `begin_signature` and `end_signature`. This is enforced in the `RVMODEL_DATA_BEGIN` and `RVMODEL_DATA_END` macros defined in the `riscv-target/spike/model_test.h` file. Additionally, if you look closely at the `RUN_TARGET` variable defined in the `Makefile.include` files of the spike target, it includes a few bash commands to sanitize the signature produced from spike. This is done to conform the final signature file to the specification defined in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`].
=== Compile, simulate and verify the tests
Once you have ported your target to the riscv-arch-test framework by following the above steps, you
are now ready to compile, simulate and verify the tests on your target
If you would like to compile, simulate and verify all the extension tests applicable to your target
simply run `make` from the `ROOTDIR`.
NOTE: For the above to work the `RISCV_DEVICE` in `ROOTDIR/Makefile.include` must be left empty.
If you would like to only compile the tests for a particular extension you can use the following
command.
make RISCV_DEVICE=M compile
make RISCV_DEVICE=C compile
The arguments to the `RISCV_DEVICE` variable must be the extensions supported by the target.
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
To simulate the compiled tests on your target:
make RISCV_DEVICE=M simulate
make RISCV_DEVICE=Zifencei simulate
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
To verify if the generated signatures match the corresponding reference signatures.
make RISCV_DEVICE=M verify
NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary
for all targets.
All the above steps create and modify files in the `work` directory created in `ROOTDIR` folder. To
clean the `workdir` simple run :
make clean
By default the working directory is set to `ROOTDIR/work`. This can be overwritten by assigning a
new working directory path via the command line. Note, the path must be absolute and not relative :
make WORK=/home/me/my_path/mywork clean compile simulate

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AsciiDoc
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asciidoctor
aspell
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CGEN
cmake
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creativecommons
CY
Davidmann
discoverable
DUT
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enforceability
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github
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http
https
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ies
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io
IM
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md
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riscvOVPsim
===
A Complete, Fully Functional, Configurable RISC-V Simulator
===
riscvOVPsim has moved to its own GitHub repository.
It can now be found here: [github.com/riscv-ovpsim](https://github.com/riscv-ovpsim/imperas-riscv-tests)
For the enhanced version, please download from [ovpworld.org/riscv-ovpsim-plus](https://www.ovpworld.org/riscvOVPsimPlus).
The simulators implement the full and complete functionality of the RISC-V Foundation's public User and Privilege specifications.
The simulator is command line configurable to enable/disable all current optional and processor specific options.
The simulator is developed, licensed and maintained by [Imperas Software](http://www.imperas.com/riscv) and it is fully compliant to the OVP open standard APIs.
As a member of the RISC-V Foundation community of software and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the riscvOVPsim simulator to assist RISC-V adopters to become compliant to the RISC-V specifications. The latest RISC-V compliance test suite and framework can be downloaded from https://www.github.com/riscv/riscv-compliance.
riscvOVPsim includes an industrial quality model and simulator of RISC-V processors for use for compliance and test development. It has been developed for personal, academic, or commercial use, and the model is provided as open source under the Apache 2.0 license. The simulator is provided under the Open Virtual Platforms (OVP) Fixed Platform Kits license that enables download and usage. riscvOVPsim and Imperas RISC-V support is actively maintained and enhanced. To ensure you make use of the current version of riscvOVPsim versions do expire. Please download the latest version.
![](riscvOVPsim.jpg)
Extending riscvOVPsim and building your own models and platforms
---
riscvOVPsim is a fixed function simulation of one configurable processor model in a fixed platform.
Full extendable platform simulations of reference designs booting FreeRTOS, Linux, SMP Linux etc.
are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com),
[www.OVPworld.org](http://www.OVPworld.org).
About Open Virtual Platforms (OVP) and Imperas Software
---
**Open Virtual Platforms** was created in 2008 to provide an open standard set of APIs and methodology to develop virtual platforms and simulation technology.
[www.OVPworld.org](http://www.OVPworld.org/riscv).
**Imperas Software Ltd.** is the leading independent commercial developer of virtual platforms and high-performance software simulation solutions for embedded processor and systems. Leading semiconductor and embedded software companies use Imperas simulators for their processor based simulation solutions.
[www.imperas.com](http://www.imperas.com/riscv).
![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg)
![Imperas Imperas](https://www.imperas.com/sites/default/files/imperas-web-logo_2.png)
---
This is the riscvOVPsim/README.md

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Copyright (c) 2012-2015, The Regents of the University of California (Regents).
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Regents nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.

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../riscv-test-suite/env/arch_test.h

1
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../riscv-test-suite/env/encoding.h

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
.text.trap : { *(.text.trap) }
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.data.string : { *(.data.string)}
.bss : { *(.bss) }
_end = .;
}

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// See LICENSE for license details.
#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
#define _ENV_PHYSICAL_SINGLE_CORE_H
#include "../encoding.h"
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
#define RVTEST_RV64U \
.macro init; \
.endm
#define RVTEST_RV64UF \
.macro init; \
RVTEST_FP_ENABLE; \
.endm
#define RVTEST_RV32U \
.macro init; \
.endm
#define RVTEST_RV32UF \
.macro init; \
RVTEST_FP_ENABLE; \
.endm
#define RVTEST_RV64M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
.endm
#define RVTEST_RV64S \
.macro init; \
RVTEST_ENABLE_SUPERVISOR; \
.endm
#define RVTEST_RV32M \
.macro init; \
RVTEST_ENABLE_MACHINE; \
.endm
#define RVTEST_RV32S \
.macro init; \
RVTEST_ENABLE_SUPERVISOR; \
.endm
#if __riscv_xlen == 64
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
#else
# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
#endif
#define INIT_PMP \
la t0, 1f; \
csrw mtvec, t0; \
li t0, -1; /* Set up a PMP to permit all accesses */ \
csrw pmpaddr0, t0; \
li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
csrw pmpcfg0, t0; \
.align 2; \
1:
#define INIT_SATP \
la t0, 1f; \
csrw mtvec, t0; \
csrwi satp, 0; \
.align 2; \
1:
#define DELEGATE_NO_TRAPS \
la t0, 1f; \
csrw mtvec, t0; \
csrwi medeleg, 0; \
csrwi mideleg, 0; \
csrwi mie, 0; \
.align 2; \
1:
#define RVTEST_ENABLE_SUPERVISOR \
li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
csrs mstatus, a0; \
li a0, SIP_SSIP | SIP_STIP; \
csrs mideleg, a0; \
#define RVTEST_ENABLE_MACHINE \
li a0, MSTATUS_MPP; \
csrs mstatus, a0; \
#define RVTEST_FP_ENABLE \
li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
csrs mstatus, a0; \
csrwi fcsr, 0
#define RISCV_MULTICORE_DISABLE \
csrr a0, mhartid; \
1: bnez a0, 1b
#define EXTRA_TVEC_USER
#define EXTRA_TVEC_MACHINE
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
//
// undefine some unusable CSR Accesses if no PRIV Mode present
//
#if defined(PRIV_MISA_S)
# if (PRIV_MISA_S==0)
# undef INIT_SATP
# define INIT_SATP
# undef INIT_PMP
# define INIT_PMP
# undef DELEGATE_NO_TRAPS
# define DELEGATE_NO_TRAPS
# undef RVTEST_ENABLE_SUPERVISOR
# define RVTEST_ENABLE_SUPERVISOR
# endif
#endif
#if defined(PRIV_MISA_U)
# if (PRIV_MISA_U==0)
# endif
#endif
#if defined(TRAPHANDLER)
#include TRAPHANDLER
#endif
#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
#define RVTEST_CODE_BEGIN_OLD \
.section .text.init; \
.align 6; \
.weak stvec_handler; \
.weak mtvec_handler; \
.globl _start; \
_start: \
/* reset vector */ \
j reset_vector; \
.align 2; \
trap_vector: \
/* test whether the test came from pass/fail */ \
csrr t5, mcause; \
li t6, CAUSE_USER_ECALL; \
beq t5, t6, write_tohost; \
li t6, CAUSE_SUPERVISOR_ECALL; \
beq t5, t6, write_tohost; \
li t6, CAUSE_MACHINE_ECALL; \
beq t5, t6, write_tohost; \
/* if an mtvec_handler is defined, jump to it */ \
la t5, mtvec_handler; \
beqz t5, 1f; \
jr t5; \
/* was it an interrupt or an exception? */ \
1: csrr t5, mcause; \
bgez t5, handle_exception; \
INTERRUPT_HANDLER; \
handle_exception: \
/* we don't know how to handle whatever the exception was */ \
other_exception: \
/* some unhandlable exception occurred */ \
1: ori TESTNUM, TESTNUM, 1337; \
write_tohost: \
sw TESTNUM, tohost, t5; \
j write_tohost; \
reset_vector: \
RISCV_MULTICORE_DISABLE; \
INIT_SATP; \
INIT_PMP; \
DELEGATE_NO_TRAPS; \
li TESTNUM, 0; \
la t0, trap_vector; \
csrw mtvec, t0; \
CHECK_XLEN; \
/* if an stvec_handler is defined, delegate exceptions to it */ \
la t0, stvec_handler; \
beqz t0, 1f; \
csrw stvec, t0; \
li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
(1 << CAUSE_STORE_PAGE_FAULT) | \
(1 << CAUSE_FETCH_PAGE_FAULT) | \
(1 << CAUSE_MISALIGNED_FETCH) | \
(1 << CAUSE_USER_ECALL) | \
(1 << CAUSE_BREAKPOINT); \
csrw medeleg, t0; \
csrr t1, medeleg; \
bne t0, t1, other_exception; \
1: csrwi mstatus, 0; \
init; \
EXTRA_INIT; \
EXTRA_INIT_TIMER; \
la t0, 1f; \
csrw mepc, t0; \
csrr a0, mhartid; \
mret; \
1: \
begin_testcode:
//-----------------------------------------------------------------------
// End Macro
//-----------------------------------------------------------------------
#define RVTEST_CODE_END_OLD \
end_testcode: \
ecall;
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------
#define RVTEST_SYNC fence
//#define RVTEST_SYNC nop
#define RVTEST_PASS \
RVTEST_SYNC; \
li TESTNUM, 1; \
SWSIG (0, TESTNUM); \
ecall
#define TESTNUM gp
#define RVTEST_FAIL \
RVTEST_SYNC; \
1: beqz TESTNUM, 1b; \
sll TESTNUM, TESTNUM, 1; \
or TESTNUM, TESTNUM, 1; \
SWSIG (0, TESTNUM); \
la x1, end_testcode; \
jr x1;
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
#define EXTRA_DATA
#define RVTEST_DATA_BEGIN_OLD \
.align 4; .global begin_signature; begin_signature:
#define RVTEST_DATA_END_OLD \
.align 4; .global end_signature; end_signature: \
EXTRA_DATA \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
.align 8; .global fromhost; fromhost: .dword 0; \
.popsection; \
.align 8; .global begin_regstate; begin_regstate: \
.word 128; \
.align 8; .global end_regstate; end_regstate: \
.word 4;
#endif

17
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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.bss : { *(.bss) }
_end = .;
}

11
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// See LICENSE for license details.
#ifndef _ENV_PHYSICAL_MULTI_CORE_H
#define _ENV_PHYSICAL_MULTI_CORE_H
#include "../p/riscv_test.h"
#undef RISCV_MULTICORE_DISABLE
#define RISCV_MULTICORE_DISABLE
#endif

17
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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.bss : { *(.bss) }
_end = .;
}

69
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// See LICENSE for license details.
#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
#include "../p/riscv_test.h"
#define TIMER_INTERVAL 2
#undef EXTRA_INIT_TIMER
#define EXTRA_INIT_TIMER \
li a0, MIP_MTIP; \
csrs mie, a0; \
csrr a0, mtime; \
addi a0, a0, TIMER_INTERVAL; \
csrw mtimecmp, a0; \
#if SSTATUS_XS != 0x18000
# error
#endif
#define XS_SHIFT 15
#undef INTERRUPT_HANDLER
#define INTERRUPT_HANDLER \
slli t5, t5, 1; \
srli t5, t5, 1; \
add t5, t5, -IRQ_M_TIMER; \
bnez t5, other_exception; /* other interrups shouldn't happen */\
csrr t5, mtime; \
addi t5, t5, TIMER_INTERVAL; \
csrw mtimecmp, t5; \
mret; \
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
#undef EXTRA_DATA
#define EXTRA_DATA \
.align 3; \
regspill: \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
.dword 0xdeadbeefcafebabe; \
evac: \
.skip 32768; \
#endif

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#include "riscv_test.h"
#if __riscv_xlen == 64
# define STORE sd
# define LOAD ld
# define REGBYTES 8
#else
# define STORE sw
# define LOAD lw
# define REGBYTES 4
#endif
#define STACK_TOP (_end + 4096)
.section ".text.init","ax",@progbits
.globl _start
_start:
j handle_reset
/* NMI vector */
nmi_vector:
j wtf
trap_vector:
j wtf
handle_reset:
la t0, trap_vector
csrw mtvec, t0
la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
csrr t0, mhartid
slli t0, t0, 12
add sp, sp, t0
csrw mscratch, sp
la a0, userstart
j vm_boot
.globl pop_tf
pop_tf:
LOAD t0,33*REGBYTES(a0)
csrw sepc,t0
LOAD x1,1*REGBYTES(a0)
LOAD x2,2*REGBYTES(a0)
LOAD x3,3*REGBYTES(a0)
LOAD x4,4*REGBYTES(a0)
LOAD x5,5*REGBYTES(a0)
LOAD x6,6*REGBYTES(a0)
LOAD x7,7*REGBYTES(a0)
LOAD x8,8*REGBYTES(a0)
LOAD x9,9*REGBYTES(a0)
LOAD x11,11*REGBYTES(a0)
LOAD x12,12*REGBYTES(a0)
LOAD x13,13*REGBYTES(a0)
LOAD x14,14*REGBYTES(a0)
LOAD x15,15*REGBYTES(a0)
LOAD x16,16*REGBYTES(a0)
LOAD x17,17*REGBYTES(a0)
LOAD x18,18*REGBYTES(a0)
LOAD x19,19*REGBYTES(a0)
LOAD x20,20*REGBYTES(a0)
LOAD x21,21*REGBYTES(a0)
LOAD x22,22*REGBYTES(a0)
LOAD x23,23*REGBYTES(a0)
LOAD x24,24*REGBYTES(a0)
LOAD x25,25*REGBYTES(a0)
LOAD x26,26*REGBYTES(a0)
LOAD x27,27*REGBYTES(a0)
LOAD x28,28*REGBYTES(a0)
LOAD x29,29*REGBYTES(a0)
LOAD x30,30*REGBYTES(a0)
LOAD x31,31*REGBYTES(a0)
LOAD a0,10*REGBYTES(a0)
sret
.global trap_entry
trap_entry:
csrrw sp, sscratch, sp
# save gprs
STORE x1,1*REGBYTES(sp)
STORE x3,3*REGBYTES(sp)
STORE x4,4*REGBYTES(sp)
STORE x5,5*REGBYTES(sp)
STORE x6,6*REGBYTES(sp)
STORE x7,7*REGBYTES(sp)
STORE x8,8*REGBYTES(sp)
STORE x9,9*REGBYTES(sp)
STORE x10,10*REGBYTES(sp)
STORE x11,11*REGBYTES(sp)
STORE x12,12*REGBYTES(sp)
STORE x13,13*REGBYTES(sp)
STORE x14,14*REGBYTES(sp)
STORE x15,15*REGBYTES(sp)
STORE x16,16*REGBYTES(sp)
STORE x17,17*REGBYTES(sp)
STORE x18,18*REGBYTES(sp)
STORE x19,19*REGBYTES(sp)
STORE x20,20*REGBYTES(sp)
STORE x21,21*REGBYTES(sp)
STORE x22,22*REGBYTES(sp)
STORE x23,23*REGBYTES(sp)
STORE x24,24*REGBYTES(sp)
STORE x25,25*REGBYTES(sp)
STORE x26,26*REGBYTES(sp)
STORE x27,27*REGBYTES(sp)
STORE x28,28*REGBYTES(sp)
STORE x29,29*REGBYTES(sp)
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)
csrrw t0,sscratch,sp
STORE t0,2*REGBYTES(sp)
# get sr, epc, badvaddr, cause
csrr t0,sstatus
STORE t0,32*REGBYTES(sp)
csrr t0,sepc
STORE t0,33*REGBYTES(sp)
csrr t0,sbadaddr
STORE t0,34*REGBYTES(sp)
csrr t0,scause
STORE t0,35*REGBYTES(sp)
move a0, sp
j handle_trap

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x80000000;
.text.init : { *(.text.init) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
.text : { *(.text) }
. = ALIGN(0x1000);
.data : { *(.data) }
.bss : { *(.bss) }
_end = .;
}

71
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// See LICENSE for license details.
#ifndef _ENV_VIRTUAL_SINGLE_CORE_H
#define _ENV_VIRTUAL_SINGLE_CORE_H
#include "../p/riscv_test.h"
//-----------------------------------------------------------------------
// Begin Macro
//-----------------------------------------------------------------------
#undef RVTEST_FP_ENABLE
#define RVTEST_FP_ENABLE fssr x0
#undef RVTEST_CODE_BEGIN
#define RVTEST_CODE_BEGIN \
.text; \
.global userstart; \
userstart: \
init
//-----------------------------------------------------------------------
// Pass/Fail Macro
//-----------------------------------------------------------------------
#undef RVTEST_PASS
#define RVTEST_PASS li a0, 1; scall
#undef RVTEST_FAIL
#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
//-----------------------------------------------------------------------
// Data Section Macro
//-----------------------------------------------------------------------
#undef RVTEST_DATA_END
#define RVTEST_DATA_END
//-----------------------------------------------------------------------
// Supervisor mode definitions and macros
//-----------------------------------------------------------------------
#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
#define PGSHIFT 12
#define PGSIZE (1UL << PGSHIFT)
#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36)
#ifndef __ASSEMBLER__
typedef unsigned long pte_t;
#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
#define VPN_BITS (PTIDXBITS * LEVELS)
#define VA_BITS (VPN_BITS + PGSHIFT)
#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS)
#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE)
typedef struct
{
long gpr[32];
long sr;
long epc;
long badvaddr;
long cause;
} trapframe_t;
#endif
#endif

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#include <string.h>
#include <stdint.h>
#include <ctype.h>
void* memcpy(void* dest, const void* src, size_t len)
{
if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
const uintptr_t* s = src;
uintptr_t *d = dest;
while (d < (uintptr_t*)(dest + len))
*d++ = *s++;
} else {
const char* s = src;
char *d = dest;
while (d < (char*)(dest + len))
*d++ = *s++;
}
return dest;
}
void* memset(void* dest, int byte, size_t len)
{
if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
uintptr_t word = byte & 0xFF;
word |= word << 8;
word |= word << 16;
word |= word << 16 << 16;
uintptr_t *d = dest;
while (d < (uintptr_t*)(dest + len))
*d++ = word;
} else {
char *d = dest;
while (d < (char*)(dest + len))
*d++ = byte;
}
return dest;
}
size_t strlen(const char *s)
{
const char *p = s;
while (*p)
p++;
return p - s;
}
int strcmp(const char* s1, const char* s2)
{
unsigned char c1, c2;
do {
c1 = *s1++;
c2 = *s2++;
} while (c1 != 0 && c1 == c2);
return c1 - c2;
}
int memcmp(const void* s1, const void* s2, size_t n)
{
if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) {
const uintptr_t* u1 = s1;
const uintptr_t* u2 = s2;
const uintptr_t* end = u1 + (n / sizeof(uintptr_t));
while (u1 < end) {
if (*u1 != *u2)
break;
u1++;
u2++;
}
n -= (const void*)u1 - s1;
s1 = u1;
s2 = u2;
}
while (n--) {
unsigned char c1 = *(const unsigned char*)s1++;
unsigned char c2 = *(const unsigned char*)s2++;
if (c1 != c2)
return c1 - c2;
}
return 0;
}
char* strcpy(char* dest, const char* src)
{
char* d = dest;
while ((*d++ = *src++))
;
return dest;
}
long atol(const char* str)
{
long res = 0;
int sign = 0;
while (*str == ' ')
str++;
if (*str == '-' || *str == '+') {
sign = *str == '-';
str++;
}
while (*str) {
res *= 10;
res += *str++ - '0';
}
return sign ? -res : res;
}

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// See LICENSE for license details.
#include <stdint.h>
#include <string.h>
#include <stdio.h>
#include "riscv_test.h"
void trap_entry();
void pop_tf(trapframe_t*);
volatile uint64_t tohost;
volatile uint64_t fromhost;
static void do_tohost(uint64_t tohost_value)
{
while (tohost)
fromhost = 0;
tohost = tohost_value;
}
#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)
#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory")
static uint64_t lfsr63(uint64_t x)
{
uint64_t bit = (x ^ (x >> 1)) & 1;
return (x >> 1) | (bit << 62);
}
static void cputchar(int x)
{
do_tohost(0x0101000000000000 | (unsigned char)x);
}
static void cputstring(const char* s)
{
while (*s)
cputchar(*s++);
}
static void terminate(int code)
{
do_tohost(code);
while (1);
}
void wtf()
{
terminate(841);
}
#define stringify1(x) #x
#define stringify(x) stringify1(x)
#define assert(x) do { \
if (x) break; \
cputstring("Assertion failed: " stringify(x) "\n"); \
terminate(3); \
} while(0)
#define l1pt pt[0]
#define user_l2pt pt[1]
#if __riscv_xlen == 64
# define NPT 4
#define kernel_l2pt pt[2]
# define user_l3pt pt[3]
#else
# define NPT 2
# define user_l3pt user_l2pt
#endif
pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
typedef struct { pte_t addr; void* next; } freelist_t;
freelist_t user_mapping[MAX_TEST_PAGES];
freelist_t freelist_nodes[MAX_TEST_PAGES];
freelist_t *freelist_head, *freelist_tail;
void printhex(uint64_t x)
{
char str[17];
for (int i = 0; i < 16; i++)
{
str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
x >>= 4;
}
str[16] = 0;
cputstring(str);
}
static void evict(unsigned long addr)
{
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
addr = addr/PGSIZE*PGSIZE;
freelist_t* node = &user_mapping[addr/PGSIZE];
if (node->addr)
{
// check accessed and dirty bits
assert(user_l3pt[addr/PGSIZE] & PTE_A);
uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
assert(user_l3pt[addr/PGSIZE] & PTE_D);
memcpy((void*)addr, uva2kva(addr), PGSIZE);
}
write_csr(sstatus, sstatus);
user_mapping[addr/PGSIZE].addr = 0;
if (freelist_tail == 0)
freelist_head = freelist_tail = node;
else
{
freelist_tail->next = node;
freelist_tail = node;
}
}
}
void handle_fault(uintptr_t addr, uintptr_t cause)
{
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
addr = addr/PGSIZE*PGSIZE;
if (user_l3pt[addr/PGSIZE]) {
if (!(user_l3pt[addr/PGSIZE] & PTE_A)) {
user_l3pt[addr/PGSIZE] |= PTE_A;
} else {
assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
user_l3pt[addr/PGSIZE] |= PTE_D;
}
flush_page(addr);
return;
}
freelist_t* node = freelist_head;
assert(node);
freelist_head = node->next;
if (freelist_head == freelist_tail)
freelist_tail = 0;
uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
flush_page(addr);
assert(user_mapping[addr/PGSIZE].addr == 0);
user_mapping[addr/PGSIZE] = *node;
uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
memcpy((void*)addr, uva2kva(addr), PGSIZE);
write_csr(sstatus, sstatus);
user_l3pt[addr/PGSIZE] = new_pte;
flush_page(addr);
__builtin___clear_cache(0,0);
}
void handle_trap(trapframe_t* tf)
{
if (tf->cause == CAUSE_USER_ECALL)
{
int n = tf->gpr[10];
for (long i = 1; i < MAX_TEST_PAGES; i++)
evict(i*PGSIZE);
terminate(n);
}
else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
{
assert(tf->epc % 4 == 0);
int* fssr;
asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr));
if (*(int*)tf->epc == *fssr)
terminate(1); // FP test on non-FP hardware. "succeed."
else
assert(!"illegal instruction");
tf->epc += 4;
}
else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT)
handle_fault(tf->badvaddr, tf->cause);
else
assert(!"unexpected exception");
pop_tf(tf);
}
static void coherence_torture()
{
// cause coherence misses without affecting program semantics
unsigned int random = ENTROPY;
while (1) {
uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
#ifdef __riscv_atomic
if (random & 1) // perform a no-op write
asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr));
else // perform a read
#endif
asm volatile ("lw zero, (%0)" :: "r"(paddr));
random = lfsr63(random);
}
}
void vm_boot(uintptr_t test_addr)
{
unsigned int random = ENTROPY;
if (read_csr(mhartid) > 0)
coherence_torture();
_Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???");
#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0
# error
#endif
// map user to lowermost megapage
l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
// map kernel to uppermost megapage
#if __riscv_xlen == 64
l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
uintptr_t vm_choice = SATP_MODE_SV39;
#else
l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
uintptr_t vm_choice = SATP_MODE_SV32;
#endif
write_csr(satp, ((uintptr_t)l1pt >> PGSHIFT) |
(vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
// Set up PMPs if present, ignoring illegal instruction trap if not.
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
asm volatile ("la t0, 1f\n\t"
"csrrw t0, mtvec, t0\n\t"
"csrw pmpaddr0, %1\n\t"
"csrw pmpcfg0, %0\n\t"
".align 2\n\t"
"1:"
: : "r" (pmpc), "r" (-1UL) : "t0");
// set up supervisor trap handling
write_csr(stvec, pa2kva(trap_entry));
write_csr(sscratch, pa2kva(read_csr(mscratch)));
write_csr(medeleg,
(1 << CAUSE_USER_ECALL) |
(1 << CAUSE_FETCH_PAGE_FAULT) |
(1 << CAUSE_LOAD_PAGE_FAULT) |
(1 << CAUSE_STORE_PAGE_FAULT));
// FPU on; accelerator on; allow supervisor access to user memory access
write_csr(mstatus, MSTATUS_FS | MSTATUS_XS);
write_csr(mie, 0);
random = 1 + (random % MAX_TEST_PAGES);
freelist_head = pa2kva((void*)&freelist_nodes[0]);
freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]);
for (long i = 0; i < MAX_TEST_PAGES; i++)
{
freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]);
random = LFSR_NEXT(random);
}
freelist_nodes[MAX_TEST_PAGES-1].next = 0;
trapframe_t tf;
memset(&tf, 0, sizeof(tf));
tf.epc = test_addr - DRAM_BASE;
pop_tf(&tf);
}

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#!/bin/bash
printf "\n\nCompare to reference files ... \n\n";
FAIL=0
RUN=0
for ref in ${SUITEDIR}/references/*.reference_output;
do
base=$(basename ${ref})
stub=${base//".reference_output"/}
if [ "${stub}" = "*" ]; then
echo "No Reference Files ${SUITEDIR}/references/*.reference_output"
break
fi
sig=${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/${stub}.signature.output
dif=${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/${stub}.diff
RUN=$((${RUN} + 1))
#
# Ensure both files exist
#
if [ -f ${ref} ] && [ -f ${sig} ]; then
echo -n "Check $(printf %-24s ${stub}) "
else
echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m"
continue
fi
diff --ignore-case --strip-trailing-cr ${ref} ${sig} &> /dev/null
if [ $? == 0 ]
then
echo -e "\e[32m ... OK \e[39m"
else
echo -e "\e[31m ... FAIL \e[39m"
FAIL=$((${FAIL} + 1))
sdiff ${ref} ${sig} > ${dif}
fi
done
# warn on missing reverse reference
for sig in ${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/*.signature.output;
do
base=$(basename ${sig})
stub=${base//".signature.output"/}
ref=${SUITEDIR}/references/${stub}.reference_output
if [ -f $sig ] && [ ! -f ${ref} ]; then
echo -e "\e[31m Error: sig ${sig} no corresponding ${ref} \e[39m"
FAIL=$((${FAIL} + 1))
fi
done
declare -i status=0
if [ ${FAIL} == 0 ]
then
echo "--------------------------------"
echo -n -e "\e[32m OK: ${RUN}/${RUN} "
status=0
else
echo "--------------------------------"
echo -n -e "\e[31m FAIL: ${FAIL}/${RUN} "
status=1
fi
echo -e "RISCV_TARGET=${RISCV_TARGET} RISCV_DEVICE=${RISCV_DEVICE} XLEN=${XLEN} \e[39m"
echo
exit ${status}

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#=======================================================================
# Makefile for riscv-tests/isa
#-----------------------------------------------------------------------
act_dir := .
src_dir := $(act_dir)/src
work_dir := $(WORK)
work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE)
include $(act_dir)/Makefrag
ifneq ($(RISCV_TEST),)
target_tests = $(RISCV_TEST).elf
endif
default: all
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
vpath %.S $(act_dir)
INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m/$(RISCV_DEVICE)/Makefile.include
ifeq ($(wildcard $(INCLUDE)),)
$(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
endif
-include $(INCLUDE)
#------------------------------------------------------------
# Build and run assembly tests
%.log: %.elf
$(V) echo "Execute $(@)"
$(V) $(RUN_TARGET)
define compile_template
$(work_dir_isa)/%.elf: $(src_dir)/%.S
$(V) echo "Compile $$(@)"
@mkdir -p $$(@D)
$(V) $(COMPILE_TARGET)
.PRECIOUS: $(work_dir_isa)/%.elf
endef
target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
target_log = $(patsubst %.elf,%.log,$(target_elf))
compile: $(target_elf)
run: $(target_log)
#------------------------------------------------------------
# Clean up
clean:
rm -rf $(work_dir)

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# RISC-V Test Suites
The tests are grouped based on the different extension subsets of the RISC-V unprivileged ISA.
The tests strictly follow the [Test format](../spec/TestFormatSpec.adoc) specification.
Directory names postfixed with "\_unratified" indicate that tests for extensions that have not yet
been ratified by RVI.
The coverage report (in html format) of the tests available in this suite is generated through
[RISCOF](https://github.com/riscv-software-src/riscof) and is available here: [Coverage Report](../riscv-test-stats/coverage/README.md).
These tests have been generated using the open source Compatibility Test Generator from InCore Semiconductors available
at: [CTG](https://github.com/riscv/riscv-ctg).
The reference signatures are generated using [SAIL](https://github.com/riscv/sail-riscv) or
[SPIKE](https://github.com/riscv-software-src/riscv-isa-sim).
Test directories with the "\_unratified" post-fix indicate test-suites for extensions which have not been
ratified (but are stable and near ratification)
Directory structure
```
├── env # contains the architectural test header files
└── rv32i_m # top level folder indicate rv32 tests for machine mode
├── C # include tests and references for "C" extension
│   ├── references # static references signatures for "C" extension
│   └── src # assembly tests for "C" extension
├── F # include tests and references for "rv32F" extension
│   ├── references # static references signatures for "rv32F" extension
│   └── src # assembly tests for "rv32F" extension
├── I # include tests and references for "I" extension
│   ├── references # static references signatures for "I" extension
│   └── src # assembly tests for "I" extension
├── M # include tests and references for "M" extension
│ ├── references # static references signatures for "M" extension
│ └── src # assembly tests for "M" extension
├── K_unratified # include tests and references for "K" extension
│ ├── references # static references signatures for "K" extension
│ └── src # assembly tests for "K" extension
├── privilege # include tests and references for tests which require Privilege Spec
│ ├── references # static references signatures for tests which require Privilege Spec
│ └── src # assembly tests for tests which require Privilege Spec
└── Zifencei # include tests and references for "Zifencei" extension
├── references # static references signatures for "Zifencei" extension
└── src # assembly tests for "Zifencei" extension
└── rv64i_m # top level folder indicate rv64 tests for machine mode
├── C # include tests and references for "C" extension
│   ├── references # static references signatures for "C" extension
│   └── src # assembly tests for "C" extension
├── I # include tests and references for "I" extension
│   ├── references # static references signatures for "I" extension
│   └── src # assembly tests for "I" extension
├── M # include tests and references for "M" extension
│ ├── references # static references signatures for "M" extension
│ └── src # assembly tests for "M" extension
├── K_unratified # include tests and references for "K" extension
│ ├── references # static references signatures for "K" extension
│ └── src # assembly tests for "K" extension
├── privilege # include tests and references for tests which require Privilege Spec
│ ├── references # static references signatures for tests which require Privilege Spec
│ └── src # assembly tests for tests which require Privilege Spec
└── Zifencei # include tests and references for "Zifencei" extension
├── references # static references signatures for "Zifencei" extension
└── src # assembly tests for "Zifencei" extension
```

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3
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile Normal file
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include ../../Makefile.include
$(eval $(call compile_template,-march=rv32ec -mabi=ilp32e -DXLEN=$(XLEN)))

61
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# RISC-V Architecture Test RV32E Makefrag
#
# Copyright (c) 2017, Codasip Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Codasip Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32E architectural tests
rv32e_sc_tests = \
cadd-01 \
caddi-01 \
caddi16sp-01 \
caddi4spn-01 \
cand-01 \
candi-01 \
cbeqz-01 \
cbnez-01 \
cj-01 \
cjal-01 \
cjalr-01 \
cjr-01 \
cli-01 \
clui-01 \
clw-01 \
clwsp-01 \
cmv-01 \
cnop-01 \
cor-01 \
cslli-01 \
csrai-01 \
csrli-01 \
csub-01 \
csw-01 \
cswsp-01 \
cxor-01
rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests))
target_tests += $(rv32e_tests)

580
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375
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72
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19
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi4spn-01.reference_output Normal file
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586
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86
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85
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87
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581
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68
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70
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580
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7fffffbf

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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi16sp instruction of the RISC-V C extension for the caddi16sp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi16sp)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x2, imm_val == -512, rs1_val == 4194304, rs1_val != imm_val, rs1_val > 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3ffe00, 0x400000, -0x200, x1, 0, x3)
inst_1:
// rs1_val == 2147483647, imm_val == 128, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x7fffffff; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x8000007f, 0x7fffffff, 0x80, x1, 4, x3)
inst_2:
// rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40000001; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0xc000005f, -0x40000001, 0x60, x1, 8, x3)
inst_3:
// rs1_val == -536870913, rs1_val < 0 and imm_val < 0
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20000001; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xdfffff9f, -0x20000001, -0x60, x1, 12, x3)
inst_4:
// rs1_val == -268435457, imm_val == -352
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10000001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xeffffe9f, -0x10000001, -0x160, x1, 16, x3)
inst_5:
// rs1_val == -134217729, imm_val == -80
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8000001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xf7ffffaf, -0x8000001, -0x50, x1, 20, x3)
inst_6:
// rs1_val == -67108865, imm_val == -144
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4000001; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xfbffff6f, -0x4000001, -0x90, x1, 24, x3)
inst_7:
// rs1_val == -33554433,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2000001; immval:0xf0
TEST_CI_OP( c.addi16sp, x2, 0xfe0000ef, -0x2000001, 0xf0, x1, 28, x3)
inst_8:
// rs1_val == -16777217,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1000001; immval:-0x80
TEST_CI_OP( c.addi16sp, x2, 0xfeffff7f, -0x1000001, -0x80, x1, 32, x3)
inst_9:
// rs1_val == -8388609,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x800001; immval:-0x70
TEST_CI_OP( c.addi16sp, x2, 0xff7fff8f, -0x800001, -0x70, x1, 36, x3)
inst_10:
// rs1_val == -4194305, imm_val == 64
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffc0003f, -0x400001, 0x40, x1, 40, x3)
inst_11:
// rs1_val == -2097153,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x200001; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xffdffe9f, -0x200001, -0x160, x1, 44, x3)
inst_12:
// rs1_val == -1048577, imm_val == 16
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x100001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff0000f, -0x100001, 0x10, x1, 48, x3)
inst_13:
// rs1_val == -524289,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xfff8000f, -0x80001, 0x10, x1, 52, x3)
inst_14:
// rs1_val == -262145,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40001; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffbfeff, -0x40001, -0x100, x1, 56, x3)
inst_15:
// rs1_val == -131073, imm_val == 336
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20001; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xfffe014f, -0x20001, 0x150, x1, 60, x3)
inst_16:
// rs1_val == -65537,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10001; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xfffeffaf, -0x10001, -0x50, x1, 64, x3)
inst_17:
// rs1_val == -32769,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8001; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0xffff803f, -0x8001, 0x40, x1, 68, x3)
inst_18:
// rs1_val == -16385,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4001; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffc04f, -0x4001, 0x50, x1, 72, x3)
inst_19:
// rs1_val == -8193,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2001; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffdfbf, -0x2001, -0x40, x1, 76, x3)
inst_20:
// rs1_val == -4097,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1001; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff07f, -0x1001, 0x80, x1, 80, x3)
inst_21:
// rs1_val == -2049,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x801; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xfffff87f, -0x801, 0x80, x1, 84, x3)
inst_22:
// rs1_val == -1025,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x401; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0xfffffbef, -0x401, -0x10, x1, 88, x3)
inst_23:
// rs1_val == -513,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x201; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0xffffff4f, -0x201, 0x150, x1, 92, x3)
inst_24:
// rs1_val == -257, imm_val == -32
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x101; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xfffffedf, -0x101, -0x20, x1, 96, x3)
inst_25:
// rs1_val == -129,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x81; immval:-0x20
TEST_CI_OP( c.addi16sp, x2, 0xffffff5f, -0x81, -0x20, x1, 100, x3)
inst_26:
// rs1_val == -65,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x41; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x4f, -0x41, 0x90, x1, 104, x3)
inst_27:
// rs1_val == -33,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x21; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0xffffffef, -0x21, 0x10, x1, 108, x3)
inst_28:
// rs1_val == -17,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x11; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0xfffffe8f, -0x11, -0x160, x1, 112, x3)
inst_29:
// rs1_val == -9,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x9; immval:-0x60
TEST_CI_OP( c.addi16sp, x2, 0xffffff97, -0x9, -0x60, x1, 116, x3)
inst_30:
// rs1_val == -5,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xfffffefb, -0x5, -0x100, x1, 120, x3)
inst_31:
// rs1_val == -3,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x3; immval:-0x90
TEST_CI_OP( c.addi16sp, x2, 0xffffff6d, -0x3, -0x90, x1, 124, x3)
inst_32:
// rs1_val == -2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x6e, -0x2, 0x70, x1, 128, x3)
inst_33:
// imm_val == 496,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x4001f0, 0x400000, 0x1f0, x1, 132, x3)
inst_34:
// imm_val == -272,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffeeb, -0x5, -0x110, x1, 136, x3)
inst_35:
// imm_val == -48,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:-0x30
TEST_CI_OP( c.addi16sp, x2, 0xffbfffcf, -0x400001, -0x30, x1, 140, x3)
inst_36:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7fffff60, -0x80000000, -0xa0, x1, 144, x3)
inst_37:
// rs1_val == 1073741824, imm_val == 256
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000000; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x40000100, 0x40000000, 0x100, x1, 148, x3)
inst_38:
// rs1_val == 536870912,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000000; immval:-0x10
TEST_CI_OP( c.addi16sp, x2, 0x1ffffff0, 0x20000000, -0x10, x1, 152, x3)
inst_39:
// rs1_val == 268435456,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000000; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0x10000030, 0x10000000, 0x30, x1, 156, x3)
inst_40:
// rs1_val == 134217728,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x7ffff60, 0x8000000, -0xa0, x1, 160, x3)
inst_41:
// rs1_val == 64,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0xc0, 0x40, 0x80, x1, 164, x3)
inst_42:
// rs1_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x210, 0x20, 0x1f0, x1, 168, x3)
inst_43:
// rs1_val == 16,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x200, 0x10, 0x1f0, x1, 172, x3)
inst_44:
// rs1_val == 8,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8; immval:0x70
TEST_CI_OP( c.addi16sp, x2, 0x78, 0x8, 0x70, x1, 176, x3)
inst_45:
// rs1_val == 4,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4; immval:-0x110
TEST_CI_OP( c.addi16sp, x2, 0xfffffef4, 0x4, -0x110, x1, 180, x3)
inst_46:
// rs1_val == 2,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2; immval:-0x50
TEST_CI_OP( c.addi16sp, x2, 0xffffffb2, 0x2, -0x50, x1, 184, x3)
inst_47:
// rs1_val == 1,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x51, 0x1, 0x50, x1, 188, x3)
inst_48:
// imm_val == 32,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x9; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x29, 0x9, 0x20, x1, 192, x3)
inst_49:
// rs1_val == -1431655766,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x55555556; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xaaaaaada, -0x55555556, 0x30, x1, 196, x3)
inst_50:
// rs1_val == 1431655765,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x55555555; immval:0x60
TEST_CI_OP( c.addi16sp, x2, 0x555555b5, 0x55555555, 0x60, x1, 200, x3)
inst_51:
// rs1_val == 0,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x0; immval:-0x100
TEST_CI_OP( c.addi16sp, x2, 0xffffff00, 0x0, -0x100, x1, 204, x3)
inst_52:
// rs1_val == imm_val,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x80, 0x40, 0x40, x1, 208, x3)
inst_53:
// rs1_val == 67108864,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x3fffe00, 0x4000000, -0x200, x1, 212, x3)
inst_54:
// rs1_val == 33554432,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000000; immval:-0x200
TEST_CI_OP( c.addi16sp, x2, 0x1fffe00, 0x2000000, -0x200, x1, 216, x3)
inst_55:
// rs1_val == 16777216,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000000; immval:-0x40
TEST_CI_OP( c.addi16sp, x2, 0xffffc0, 0x1000000, -0x40, x1, 220, x3)
inst_56:
// rs1_val == 8388608,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800000; immval:0x10
TEST_CI_OP( c.addi16sp, x2, 0x800010, 0x800000, 0x10, x1, 224, x3)
inst_57:
// rs1_val == 2097152,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200000; immval:0x20
TEST_CI_OP( c.addi16sp, x2, 0x200020, 0x200000, 0x20, x1, 228, x3)
inst_58:
// rs1_val == 1048576,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100000; immval:0x90
TEST_CI_OP( c.addi16sp, x2, 0x100090, 0x100000, 0x90, x1, 232, x3)
inst_59:
// rs1_val == 524288,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80000; immval:0x50
TEST_CI_OP( c.addi16sp, x2, 0x80050, 0x80000, 0x50, x1, 236, x3)
inst_60:
// rs1_val == 262144,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000; immval:-0x160
TEST_CI_OP( c.addi16sp, x2, 0x3fea0, 0x40000, -0x160, x1, 240, x3)
inst_61:
// rs1_val == 131072,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000; immval:-0xa0
TEST_CI_OP( c.addi16sp, x2, 0x1ff60, 0x20000, -0xa0, x1, 244, x3)
inst_62:
// rs1_val == 65536,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x10150, 0x10000, 0x150, x1, 248, x3)
inst_63:
// rs1_val == 32768,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x81f0, 0x8000, 0x1f0, x1, 252, x3)
inst_64:
// rs1_val == 16384,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000; immval:0x40
TEST_CI_OP( c.addi16sp, x2, 0x4040, 0x4000, 0x40, x1, 256, x3)
inst_65:
// rs1_val == 8192,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000; immval:0x80
TEST_CI_OP( c.addi16sp, x2, 0x2080, 0x2000, 0x80, x1, 260, x3)
inst_66:
// rs1_val == 4096,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x11f0, 0x1000, 0x1f0, x1, 264, x3)
inst_67:
// rs1_val == 2048,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800; immval:0x100
TEST_CI_OP( c.addi16sp, x2, 0x900, 0x800, 0x100, x1, 268, x3)
inst_68:
// rs1_val == 1024,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x5f0, 0x400, 0x1f0, x1, 272, x3)
inst_69:
// rs1_val == 512,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200; immval:0x150
TEST_CI_OP( c.addi16sp, x2, 0x350, 0x200, 0x150, x1, 276, x3)
inst_70:
// rs1_val == 256,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100; immval:0x1f0
TEST_CI_OP( c.addi16sp, x2, 0x2f0, 0x100, 0x1f0, x1, 280, x3)
inst_71:
// rs1_val == 128,
// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80; immval:0x30
TEST_CI_OP( c.addi16sp, x2, 0xb0, 0x80, 0x30, x1, 284, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 72*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

165
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S Normal file
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@ -0,0 +1,165 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi4spn)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x10, imm_val == 1020, imm_val > 0
// opcode:c.addi4spn; dest:x10; immval:0x3fc
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3fc, 0x3fc, x1, 0, x2)
inst_1:
// rd==x13, imm_val == 508,
// opcode:c.addi4spn; dest:x13; immval:0x1fc
TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x1fc, 0x1fc, x1, 4, x2)
inst_2:
// rd==x9, imm_val == 764,
// opcode:c.addi4spn; dest:x9; immval:0x2fc
TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x2fc, 0x2fc, x1, 8, x2)
inst_3:
// rd==x8, imm_val == 892,
// opcode:c.addi4spn; dest:x8; immval:0x37c
TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x37c, 0x37c, x1, 12, x2)
inst_4:
// rd==x14, imm_val == 956,
// opcode:c.addi4spn; dest:x14; immval:0x3bc
TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x3bc, 0x3bc, x1, 16, x2)
inst_5:
// rd==x11, imm_val == 988,
// opcode:c.addi4spn; dest:x11; immval:0x3dc
TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x3dc, 0x3dc, x1, 20, x2)
inst_6:
// rd==x15, imm_val == 1004,
// opcode:c.addi4spn; dest:x15; immval:0x3ec
TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x3ec, 0x3ec, x1, 24, x2)
inst_7:
// rd==x12, imm_val == 1012,
// opcode:c.addi4spn; dest:x12; immval:0x3f4
TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x3f4, 0x3f4, x1, 28, x2)
inst_8:
// imm_val == 1016,
// opcode:c.addi4spn; dest:x10; immval:0x3f8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 32, x2)
inst_9:
// imm_val == 512,
// opcode:c.addi4spn; dest:x10; immval:0x200
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)
inst_10:
// imm_val == 256,
// opcode:c.addi4spn; dest:x10; immval:0x100
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 40, x2)
inst_11:
// imm_val == 128,
// opcode:c.addi4spn; dest:x10; immval:0x80
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x80, 0x80, x1, 44, x2)
inst_12:
// imm_val == 4,
// opcode:c.addi4spn; dest:x10; immval:0x4
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x4, 0x4, x1, 48, x2)
inst_13:
// imm_val == 680,
// opcode:c.addi4spn; dest:x10; immval:0x2a8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 52, x2)
inst_14:
// imm_val == 340,
// opcode:c.addi4spn; dest:x10; immval:0x154
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 56, x2)
inst_15:
// imm_val == 64,
// opcode:c.addi4spn; dest:x10; immval:0x40
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x40, 0x40, x1, 60, x2)
inst_16:
// imm_val == 32,
// opcode:c.addi4spn; dest:x10; immval:0x20
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x20, 0x20, x1, 64, x2)
inst_17:
// imm_val == 16,
// opcode:c.addi4spn; dest:x10; immval:0x10
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 68, x2)
inst_18:
// imm_val == 8,
// opcode:c.addi4spn; dest:x10; immval:0x8
TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x8, 0x8, x1, 72, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 19*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.beqz instruction of the RISC-V C extension for the cbeqz covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbeqz)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < 0, rs1_val == -4097
// opcode:c.beqz; op1:x10; op1val:-0x1001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1001, 0xac, 1b, x1, 0)
inst_1:
// rs1==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val < 0
// opcode:c.beqz; op1:x14; op1val:0x7fffffff; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x14, 0x7fffffff, 0x14, 1b, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode:c.beqz; op1:x8; op1val:-0x40000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x8, -0x40000001, 0x20, 3f, x1, 8)
inst_3:
// rs1==x15, rs1_val == -536870913,
// opcode:c.beqz; op1:x15; op1val:-0x20000001; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x15, -0x20000001, 0xac, 1b, x1, 12)
inst_4:
// rs1==x12, rs1_val == -268435457,
// opcode:c.beqz; op1:x12; op1val:-0x10000001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x12, -0x10000001, 0x12, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode:c.beqz; op1:x13; op1val:-0x8000001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x13, -0x8000001, 0x7e, 3f, x1, 20)
inst_6:
// rs1==x11, rs1_val == -67108865,
// opcode:c.beqz; op1:x11; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x11, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x9, rs1_val == -33554433,
// opcode:c.beqz; op1:x9; op1val:-0x2000001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x9, -0x2000001, 0xc, 1b, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode:c.beqz; op1:x10; op1val:-0x1000001; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1000001, 0x20, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode:c.beqz; op1:x10; op1val:-0x800001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x800001, 0x80, 1b, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode:c.beqz; op1:x10; op1val:-0x400001; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x400001, 0xe, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode:c.beqz; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode:c.beqz; op1:x10; op1val:-0x100001; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x100001, 0x22, 1b, x1, 48)
inst_13:
// rs1_val == -524289,
// opcode:c.beqz; op1:x10; op1val:-0x80001; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80001, 0x82, 1b, x1, 52)
inst_14:
// rs1_val == -262145,
// opcode:c.beqz; op1:x10; op1val:-0x40001; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x40001, 0xc, 3f, x1, 56)
inst_15:
// rs1_val == -131073,
// opcode:c.beqz; op1:x10; op1val:-0x20001; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x20001, 0x6, 3f, x1, 60)
inst_16:
// rs1_val == -65537,
// opcode:c.beqz; op1:x10; op1val:-0x10001; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x10001, 0x12, 3f, x1, 64)
inst_17:
// rs1_val == -32769,
// opcode:c.beqz; op1:x10; op1val:-0x8001; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x8001, 0x42, 1b, x1, 68)
inst_18:
// rs1_val == -16385,
// opcode:c.beqz; op1:x10; op1val:-0x4001; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x4001, 0x80, 3f, x1, 72)
inst_19:
// rs1_val == -8193,
// opcode:c.beqz; op1:x10; op1val:-0x2001; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2001, 0x7e, 3f, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode:c.beqz; op1:x10; op1val:-0x801; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x801, 0xe, 1b, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode:c.beqz; op1:x10; op1val:-0x401; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x401, 0x80, 1b, x1, 84)
inst_22:
// rs1_val == -513,
// opcode:c.beqz; op1:x10; op1val:-0x201; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x201, 0xc, 3f, x1, 88)
inst_23:
// rs1_val == -257,
// opcode:c.beqz; op1:x10; op1val:-0x101; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x101, 0xa, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode:c.beqz; op1:x10; op1val:-0x81; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x81, 0x14, 1b, x1, 96)
inst_25:
// rs1_val == -65,
// opcode:c.beqz; op1:x10; op1val:-0x41; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x41, 0xa, 1b, x1, 100)
inst_26:
// rs1_val == -33,
// opcode:c.beqz; op1:x10; op1val:-0x21; immval:0xac
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x21, 0xac, 1b, x1, 104)
inst_27:
// rs1_val == -17,
// opcode:c.beqz; op1:x10; op1val:-0x11; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x11, 0x12, 1b, x1, 108)
inst_28:
// rs1_val == -9,
// opcode:c.beqz; op1:x10; op1val:-0x9; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x9, 0x20, 3f, x1, 112)
inst_29:
// rs1_val == -5,
// opcode:c.beqz; op1:x10; op1val:-0x5; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x5, 0x42, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode:c.beqz; op1:x10; op1val:-0x3; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x3, 0x42, 1b, x1, 120)
inst_31:
// rs1_val == -2,
// opcode:c.beqz; op1:x10; op1val:-0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2, 0xa, 3f, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode:c.beqz; op1:x10; op1val:-0x80000000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80000000, 0x6, 3f, x1, 128)
inst_33:
// rs1_val == 1073741824, rs1_val > 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912,
// opcode:c.beqz; op1:x10; op1val:0x20000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000000, 0x22, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode:c.beqz; op1:x10; op1val:0x10000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000000, 0x40, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode:c.beqz; op1:x10; op1val:0x8000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000000, 0x80, 3f, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode:c.beqz; op1:x10; op1val:0x4000000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000000, 0x80, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode:c.beqz; op1:x10; op1val:0x2000000; immval:0x22
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000000, 0x22, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode:c.beqz; op1:x10; op1val:0x1000000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000000, 0x40, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode:c.beqz; op1:x10; op1val:0x800000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800000, 0xe, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode:c.beqz; op1:x10; op1val:0x400000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400000, 0x80, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode:c.beqz; op1:x10; op1val:0x200000; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200000, 0xe, 3f, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode:c.beqz; op1:x10; op1val:0x100000; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100000, 0x6, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode:c.beqz; op1:x10; op1val:0x80000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80000, 0x82, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode:c.beqz; op1:x10; op1val:0x40000; immval:0x42
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000, 0x42, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode:c.beqz; op1:x10; op1val:0x20000; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000, 0xc, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode:c.beqz; op1:x10; op1val:0x10000; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000, 0x82, 1b, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode:c.beqz; op1:x10; op1val:0x8000; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000, 0x4, 1b, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode:c.beqz; op1:x10; op1val:0x4000; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000, 0xa, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode:c.beqz; op1:x10; op1val:0x2000; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000, 0x80, 1b, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode:c.beqz; op1:x10; op1val:0x1000; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000, 0x40, 3f, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode:c.beqz; op1:x10; op1val:0x800; immval:0x20
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800, 0x20, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode:c.beqz; op1:x10; op1val:0x400; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400, 0xc, 3f, x1, 212)
inst_54:
// rs1_val == 512,
// opcode:c.beqz; op1:x10; op1val:0x200; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200, 0x10, 1b, x1, 216)
inst_55:
// rs1_val == 256,
// opcode:c.beqz; op1:x10; op1val:0x100; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100, 0x7e, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode:c.beqz; op1:x10; op1val:0x80; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80, 0x6, 3f, x1, 224)
inst_57:
// rs1_val == 64,
// opcode:c.beqz; op1:x10; op1val:0x40; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40, 0xa, 3f, x1, 228)
inst_58:
// rs1_val == 32,
// opcode:c.beqz; op1:x10; op1val:0x20; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20, 0x12, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode:c.beqz; op1:x10; op1val:0x10; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10, 0x4, 1b, x1, 236)
inst_60:
// rs1_val == 1,
// opcode:c.beqz; op1:x10; op1val:0x1; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1, 0xe, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode:c.beqz; op1:x10; op1val:0xb505; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb505, 0x10, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode:c.beqz; op1:x10; op1val:-0xb503; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb503, 0x82, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode:c.beqz; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode:c.beqz; op1:x10; op1val:0x33333334; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333334, 0x8, 3f, x1, 256)
inst_65:
// rs1_val==6,
// opcode:c.beqz; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode:c.beqz; op1:x10; op1val:-0x55555555; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555555, 0x80, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode:c.beqz; op1:x10; op1val:0x55555556; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555556, 0x14, 1b, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode:c.beqz; op1:x10; op1val:0x4; immval:0x82
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4, 0x82, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode:c.beqz; op1:x10; op1val:0xb503; immval:0x14
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb503, 0x14, 1b, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val > 0
// opcode:c.beqz; op1:x10; op1val:0x0; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x0, 0xe, 3f, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode:c.beqz; op1:x10; op1val:0x66666665; immval:0x80
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666665, 0x80, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode:c.beqz; op1:x10; op1val:0x33333332; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333332, 0xa, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode:c.beqz; op1:x10; op1val:0x55555554; immval:0xc
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555554, 0xc, 1b, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode:c.beqz; op1:x10; op1val:0x2; immval:0xa
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2, 0xa, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode:c.beqz; op1:x10; op1val:0xb504; immval:0x8
TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb504, 0x8, 1b, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode:c.beqz; op1:x10; op1val:-0xb504; immval:0x7e
TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb504, 0x7e, 3f, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode:c.beqz; op1:x10; op1val:0x66666666; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666666, 0xe, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode:c.beqz; op1:x10; op1val:0x33333333; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333333, 0x12, 3f, x1, 312)
inst_79:
// rs1_val==5,
// opcode:c.beqz; op1:x10; op1val:0x5; immval:0x10
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x5, 0x10, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode:c.beqz; op1:x10; op1val:-0x55555556; immval:0x40
TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555556, 0x40, 3f, x1, 320)
inst_81:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.beqz; op1:x10; op1val:0x55555555; immval:0x12
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555555, 0x12, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode:c.beqz; op1:x10; op1val:0x8; immval:0xe
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8, 0xe, 1b, x1, 328)
inst_83:
// rs1_val==3,
// opcode:c.beqz; op1:x10; op1val:0x3; immval:0x4
TEST_CBRANCH_OP(c.beqz, x2, x10, 0x3, 0x4, 1b, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

490
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S Normal file
View file

@ -0,0 +1,490 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.bnez instruction of the RISC-V C extension for the cbnez covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbnez)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x11, rs1_val < 0 and imm_val < 0, rs1_val == -524289
// opcode: c.bnez; op1:x11; op1val:-0x80001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x11, -0x80001, 0x4, 1b, x1, 0)
inst_1:
// rs1==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
// opcode: c.bnez; op1:x10; op1val:0x7fffffff; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x7fffffff, 0x7e, 3f, x1, 4)
inst_2:
// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
// opcode: c.bnez; op1:x8; op1val:-0x40000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x8, -0x40000001, 0xaa, 3f, x1, 8)
inst_3:
// rs1==x12, rs1_val == -536870913,
// opcode: c.bnez; op1:x12; op1val:-0x20000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x12, -0x20000001, 0xe, 1b, x1, 12)
inst_4:
// rs1==x15, rs1_val == -268435457,
// opcode: c.bnez; op1:x15; op1val:-0x10000001; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x15, -0x10000001, 0x8, 3f, x1, 16)
inst_5:
// rs1==x13, rs1_val == -134217729,
// opcode: c.bnez; op1:x13; op1val:-0x8000001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x13, -0x8000001, 0xa, 1b, x1, 20)
inst_6:
// rs1==x9, rs1_val == -67108865,
// opcode: c.bnez; op1:x9; op1val:-0x4000001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x9, -0x4000001, 0xe, 1b, x1, 24)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode: c.bnez; op1:x14; op1val:-0x2000001; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x14, -0x2000001, 0x4, 3f, x1, 28)
inst_8:
// rs1_val == -16777217,
// opcode: c.bnez; op1:x10; op1val:-0x1000001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1000001, 0xaa, 3f, x1, 32)
inst_9:
// rs1_val == -8388609,
// opcode: c.bnez; op1:x10; op1val:-0x800001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x800001, 0xc, 3f, x1, 36)
inst_10:
// rs1_val == -4194305,
// opcode: c.bnez; op1:x10; op1val:-0x400001; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x400001, 0x6, 1b, x1, 40)
inst_11:
// rs1_val == -2097153,
// opcode: c.bnez; op1:x10; op1val:-0x200001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x200001, 0x40, 3f, x1, 44)
inst_12:
// rs1_val == -1048577,
// opcode: c.bnez; op1:x10; op1val:-0x100001; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x100001, 0xaa, 3f, x1, 48)
inst_13:
// rs1_val == -262145,
// opcode: c.bnez; op1:x10; op1val:-0x40001; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x40001, 0xe, 3f, x1, 52)
inst_14:
// rs1_val == -131073,
// opcode: c.bnez; op1:x10; op1val:-0x20001; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x20001, 0x20, 3f, x1, 56)
inst_15:
// rs1_val == -65537,
// opcode: c.bnez; op1:x10; op1val:-0x10001; immval:0x40
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x10001, 0x40, 3f, x1, 60)
inst_16:
// rs1_val == -32769,
// opcode: c.bnez; op1:x10; op1val:-0x8001; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x8001, 0xa, 1b, x1, 64)
inst_17:
// rs1_val == -16385,
// opcode: c.bnez; op1:x10; op1val:-0x4001; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x4001, 0x12, 3f, x1, 68)
inst_18:
// rs1_val == -8193,
// opcode: c.bnez; op1:x10; op1val:-0x2001; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2001, 0xc, 1b, x1, 72)
inst_19:
// rs1_val == -4097,
// opcode: c.bnez; op1:x10; op1val:-0x1001; immval:0x42
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1001, 0x42, 1b, x1, 76)
inst_20:
// rs1_val == -2049,
// opcode: c.bnez; op1:x10; op1val:-0x801; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x801, 0x80, 3f, x1, 80)
inst_21:
// rs1_val == -1025,
// opcode: c.bnez; op1:x10; op1val:-0x401; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x401, 0x12, 3f, x1, 84)
inst_22:
// rs1_val == -513,
// opcode: c.bnez; op1:x10; op1val:-0x201; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x201, 0x82, 1b, x1, 88)
inst_23:
// rs1_val == -257,
// opcode: c.bnez; op1:x10; op1val:-0x101; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x101, 0x80, 1b, x1, 92)
inst_24:
// rs1_val == -129,
// opcode: c.bnez; op1:x10; op1val:-0x81; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x81, 0xe, 3f, x1, 96)
inst_25:
// rs1_val == -65,
// opcode: c.bnez; op1:x10; op1val:-0x41; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x41, 0x10, 3f, x1, 100)
inst_26:
// rs1_val == -33,
// opcode: c.bnez; op1:x10; op1val:-0x21; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x21, 0x7e, 3f, x1, 104)
inst_27:
// rs1_val == -17,
// opcode: c.bnez; op1:x10; op1val:-0x11; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x11, 0x20, 3f, x1, 108)
inst_28:
// rs1_val == -9,
// opcode: c.bnez; op1:x10; op1val:-0x9; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x9, 0x4, 1b, x1, 112)
inst_29:
// rs1_val == -5,
// opcode: c.bnez; op1:x10; op1val:-0x5; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x5, 0x80, 1b, x1, 116)
inst_30:
// rs1_val == -3,
// opcode: c.bnez; op1:x10; op1val:-0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x3, 0xaa, 3f, x1, 120)
inst_31:
// rs1_val == -2,
// opcode: c.bnez; op1:x10; op1val:-0x2; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2, 0x10, 1b, x1, 124)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
// opcode: c.bnez; op1:x10; op1val:-0x80000000; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x80000000, 0x80, 1b, x1, 128)
inst_33:
// rs1_val == 1073741824,
// opcode: c.bnez; op1:x10; op1val:0x40000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
inst_34:
// rs1_val == 536870912, rs1_val > 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x20000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000000, 0xc, 1b, x1, 136)
inst_35:
// rs1_val == 268435456,
// opcode: c.bnez; op1:x10; op1val:0x10000000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000000, 0x7e, 3f, x1, 140)
inst_36:
// rs1_val == 134217728,
// opcode: c.bnez; op1:x10; op1val:0x8000000; immval:0x82
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000000, 0x82, 1b, x1, 144)
inst_37:
// rs1_val == 67108864,
// opcode: c.bnez; op1:x10; op1val:0x4000000; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000000, 0xaa, 3f, x1, 148)
inst_38:
// rs1_val == 33554432,
// opcode: c.bnez; op1:x10; op1val:0x2000000; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000000, 0xe, 1b, x1, 152)
inst_39:
// rs1_val == 16777216,
// opcode: c.bnez; op1:x10; op1val:0x1000000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000000, 0xc, 3f, x1, 156)
inst_40:
// rs1_val == 8388608,
// opcode: c.bnez; op1:x10; op1val:0x800000; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800000, 0x20, 3f, x1, 160)
inst_41:
// rs1_val == 4194304,
// opcode: c.bnez; op1:x10; op1val:0x400000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400000, 0x8, 3f, x1, 164)
inst_42:
// rs1_val == 2097152,
// opcode: c.bnez; op1:x10; op1val:0x200000; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200000, 0x22, 1b, x1, 168)
inst_43:
// rs1_val == 1048576,
// opcode: c.bnez; op1:x10; op1val:0x100000; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100000, 0x4, 1b, x1, 172)
inst_44:
// rs1_val == 524288,
// opcode: c.bnez; op1:x10; op1val:0x80000; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80000, 0x8, 1b, x1, 176)
inst_45:
// rs1_val == 262144,
// opcode: c.bnez; op1:x10; op1val:0x40000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000, 0x6, 1b, x1, 180)
inst_46:
// rs1_val == 131072,
// opcode: c.bnez; op1:x10; op1val:0x20000; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000, 0x6, 1b, x1, 184)
inst_47:
// rs1_val == 65536,
// opcode: c.bnez; op1:x10; op1val:0x10000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000, 0x7e, 3f, x1, 188)
inst_48:
// rs1_val == 32768,
// opcode: c.bnez; op1:x10; op1val:0x8000; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000, 0x7e, 3f, x1, 192)
inst_49:
// rs1_val == 16384,
// opcode: c.bnez; op1:x10; op1val:0x4000; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000, 0xac, 1b, x1, 196)
inst_50:
// rs1_val == 8192,
// opcode: c.bnez; op1:x10; op1val:0x2000; immval:0x10
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000, 0x10, 3f, x1, 200)
inst_51:
// rs1_val == 4096,
// opcode: c.bnez; op1:x10; op1val:0x1000; immval:0xc
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000, 0xc, 1b, x1, 204)
inst_52:
// rs1_val == 2048,
// opcode: c.bnez; op1:x10; op1val:0x800; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800, 0x7e, 3f, x1, 208)
inst_53:
// rs1_val == 1024,
// opcode: c.bnez; op1:x10; op1val:0x400; immval:0xa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400, 0xa, 1b, x1, 212)
inst_54:
// rs1_val == 512,
// opcode: c.bnez; op1:x10; op1val:0x200; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200, 0x12, 3f, x1, 216)
inst_55:
// rs1_val == 256,
// opcode: c.bnez; op1:x10; op1val:0x100; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100, 0xe, 3f, x1, 220)
inst_56:
// rs1_val == 128,
// opcode: c.bnez; op1:x10; op1val:0x80; immval:0xe
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80, 0xe, 1b, x1, 224)
inst_57:
// rs1_val == 64,
// opcode: c.bnez; op1:x10; op1val:0x40; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40, 0x22, 1b, x1, 228)
inst_58:
// rs1_val == 32,
// opcode: c.bnez; op1:x10; op1val:0x20; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20, 0x4, 1b, x1, 232)
inst_59:
// rs1_val == 16,
// opcode: c.bnez; op1:x10; op1val:0x10; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10, 0x8, 3f, x1, 236)
inst_60:
// rs1_val == 1,
// opcode: c.bnez; op1:x10; op1val:0x1; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1, 0x4, 3f, x1, 240)
inst_61:
// rs1_val==46341,
// opcode: c.bnez; op1:x10; op1val:0xb505; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb505, 0x12, 1b, x1, 244)
inst_62:
// rs1_val==-46339,
// opcode: c.bnez; op1:x10; op1val:-0xb503; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb503, 0x22, 1b, x1, 248)
inst_63:
// rs1_val==1717986919,
// opcode: c.bnez; op1:x10; op1val:0x66666667; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
inst_64:
// rs1_val==858993460,
// opcode: c.bnez; op1:x10; op1val:0x33333334; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333334, 0x4, 1b, x1, 256)
inst_65:
// rs1_val==6,
// opcode: c.bnez; op1:x10; op1val:0x6; immval:0x6
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x6, 0x6, 1b, x1, 260)
inst_66:
// rs1_val==-1431655765,
// opcode: c.bnez; op1:x10; op1val:-0x55555555; immval:0x20
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555555, 0x20, 3f, x1, 264)
inst_67:
// rs1_val==1431655766,
// opcode: c.bnez; op1:x10; op1val:0x55555556; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555556, 0x12, 3f, x1, 268)
inst_68:
// rs1_val==4, rs1_val == 4
// opcode: c.bnez; op1:x10; op1val:0x4; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4, 0xac, 1b, x1, 272)
inst_69:
// rs1_val==46339,
// opcode: c.bnez; op1:x10; op1val:0xb503; immval:0x7e
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb503, 0x7e, 3f, x1, 276)
inst_70:
// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val < 0
// opcode: c.bnez; op1:x10; op1val:0x0; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x0, 0x12, 1b, x1, 280)
inst_71:
// rs1_val==1717986917,
// opcode: c.bnez; op1:x10; op1val:0x66666665; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666665, 0x8, 3f, x1, 284)
inst_72:
// rs1_val==858993458,
// opcode: c.bnez; op1:x10; op1val:0x33333332; immval:0x80
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333332, 0x80, 1b, x1, 288)
inst_73:
// rs1_val==1431655764,
// opcode: c.bnez; op1:x10; op1val:0x55555554; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555554, 0x12, 3f, x1, 292)
inst_74:
// rs1_val==2, rs1_val == 2
// opcode: c.bnez; op1:x10; op1val:0x2; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2, 0x12, 1b, x1, 296)
inst_75:
// rs1_val==46340,
// opcode: c.bnez; op1:x10; op1val:0xb504; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb504, 0xaa, 3f, x1, 300)
inst_76:
// rs1_val==-46340,
// opcode: c.bnez; op1:x10; op1val:-0xb504; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb504, 0x4, 1b, x1, 304)
inst_77:
// rs1_val==1717986918,
// opcode: c.bnez; op1:x10; op1val:0x66666666; immval:0x8
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666666, 0x8, 3f, x1, 308)
inst_78:
// rs1_val==858993459,
// opcode: c.bnez; op1:x10; op1val:0x33333333; immval:0x22
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333333, 0x22, 1b, x1, 312)
inst_79:
// rs1_val==5,
// opcode: c.bnez; op1:x10; op1val:0x5; immval:0x12
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x5, 0x12, 1b, x1, 316)
inst_80:
// rs1_val==-1431655766, rs1_val == -1431655766
// opcode: c.bnez; op1:x10; op1val:-0x55555556; immval:0xac
TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555556, 0xac, 1b, x1, 320)
inst_81:
// rs1_val==1431655765, rs1_val == 1431655765
// opcode: c.bnez; op1:x10; op1val:0x55555555; immval:0x4
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555555, 0x4, 1b, x1, 324)
inst_82:
// rs1_val == 8,
// opcode: c.bnez; op1:x10; op1val:0x8; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8, 0xaa, 3f, x1, 328)
inst_83:
// rs1_val==3,
// opcode: c.bnez; op1:x10; op1val:0x3; immval:0xaa
TEST_CBRANCH_OP(c.bnez, x2, x10, 0x3, 0xaa, 3f, x1, 332)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 84*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

155
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.j instruction of the RISC-V C extension for the cj covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cj)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val < 0, imm_val == -66
// opcode:c.j; immval:0x42
TEST_CJ_OP(c.j, x2, 0x42, 1b, x1, 0)
inst_1:
// imm_val == -1026,
// opcode:c.j; immval:0x402
TEST_CJ_OP(c.j, x2, 0x402, 1b, x1, 4)
inst_2:
// imm_val == -514,
// opcode:c.j; immval:0x202
TEST_CJ_OP(c.j, x2, 0x202, 1b, x1, 8)
inst_3:
// imm_val == -258,
// opcode:c.j; immval:0x102
TEST_CJ_OP(c.j, x2, 0x102, 1b, x1, 12)
inst_4:
// imm_val == -130,
// opcode:c.j; immval:0x82
TEST_CJ_OP(c.j, x2, 0x82, 1b, x1, 16)
inst_5:
// imm_val == -34,
// opcode:c.j; immval:0x22
TEST_CJ_OP(c.j, x2, 0x22, 1b, x1, 20)
inst_6:
// imm_val == -18,
// opcode:c.j; immval:0x12
TEST_CJ_OP(c.j, x2, 0x12, 1b, x1, 24)
inst_7:
// imm_val == -10,
// opcode:c.j; immval:0xa
TEST_CJ_OP(c.j, x2, 0xa, 1b, x1, 28)
inst_8:
// imm_val == 1024, imm_val > 0
// opcode:c.j; immval:0x400
TEST_CJ_OP(c.j, x2, 0x400, 3f, x1, 32)
inst_9:
// imm_val == 512,
// opcode:c.j; immval:0x200
TEST_CJ_OP(c.j, x2, 0x200, 3f, x1, 36)
inst_10:
// imm_val == 1364,
// opcode:c.j; immval:0x554
TEST_CJ_OP(c.j, x2, 0x554, 3f, x1, 40)
inst_11:
// imm_val == -1366,
// opcode:c.j; immval:0x556
TEST_CJ_OP(c.j, x2, 0x556, 1b, x1, 44)
inst_12:
// imm_val == 256,
// opcode:c.j; immval:0x100
TEST_CJ_OP(c.j, x2, 0x100, 3f, x1, 48)
inst_13:
// imm_val == 128,
// opcode:c.j; immval:0x80
TEST_CJ_OP(c.j, x2, 0x80, 3f, x1, 52)
inst_14:
// imm_val == 64,
// opcode:c.j; immval:0x40
TEST_CJ_OP(c.j, x2, 0x40, 3f, x1, 56)
inst_15:
// imm_val == 32,
// opcode:c.j; immval:0x20
TEST_CJ_OP(c.j, x2, 0x20, 3f, x1, 60)
inst_16:
// imm_val == 16,
// opcode:c.j; immval:0x10
TEST_CJ_OP(c.j, x2, 0x10, 3f, x1, 64)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 17*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jal instruction of the RISC-V C extension for the cjal covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjal)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// imm_val < 0,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 1b, x2, 0)
inst_1:
// imm_val == -1026,
// opcode:c.jal; immval:0x402
TEST_CJAL_OP(c.jal, x3, 0x402, 1b, x2, 4)
inst_2:
// imm_val == -514,
// opcode:c.jal; immval:0x202
TEST_CJAL_OP(c.jal, x3, 0x202, 1b, x2, 8)
inst_3:
// imm_val == -258,
// opcode:c.jal; immval:0x102
TEST_CJAL_OP(c.jal, x3, 0x102, 1b, x2, 12)
inst_4:
// imm_val == -130,
// opcode:c.jal; immval:0x82
TEST_CJAL_OP(c.jal, x3, 0x82, 1b, x2, 16)
inst_5:
// imm_val == -66,
// opcode:c.jal; immval:0x42
TEST_CJAL_OP(c.jal, x3, 0x42, 1b, x2, 20)
inst_6:
// imm_val == -34,
// opcode:c.jal; immval:0x22
TEST_CJAL_OP(c.jal, x3, 0x22, 1b, x2, 24)
inst_7:
// imm_val == -18,
// opcode:c.jal; immval:0x12
TEST_CJAL_OP(c.jal, x3, 0x12, 1b, x2, 28)
inst_8:
// imm_val == -10,
// opcode:c.jal; immval:0xa
TEST_CJAL_OP(c.jal, x3, 0xa, 1b, x2, 32)
inst_9:
// imm_val == 1024, imm_val > 0
// opcode:c.jal; immval:0x400
TEST_CJAL_OP(c.jal, x3, 0x400, 3f, x2, 36)
inst_10:
// imm_val == 512,
// opcode:c.jal; immval:0x200
TEST_CJAL_OP(c.jal, x3, 0x200, 3f, x2, 40)
inst_11:
// imm_val == 1364,
// opcode:c.jal; immval:0x554
TEST_CJAL_OP(c.jal, x3, 0x554, 3f, x2, 44)
inst_12:
// imm_val == -1366,
// opcode:c.jal; immval:0x556
TEST_CJAL_OP(c.jal, x3, 0x556, 1b, x2, 48)
inst_13:
// imm_val == 256,
// opcode:c.jal; immval:0x100
TEST_CJAL_OP(c.jal, x3, 0x100, 3f, x2, 52)
inst_14:
// imm_val == 128,
// opcode:c.jal; immval:0x80
TEST_CJAL_OP(c.jal, x3, 0x80, 3f, x2, 56)
inst_15:
// imm_val == 64,
// opcode:c.jal; immval:0x40
TEST_CJAL_OP(c.jal, x3, 0x40, 3f, x2, 60)
inst_16:
// imm_val == 32,
// opcode:c.jal; immval:0x20
TEST_CJAL_OP(c.jal, x3, 0x20, 3f, x2, 64)
inst_17:
// imm_val == 16,
// opcode:c.jal; immval:0x10
TEST_CJAL_OP(c.jal, x3, 0x10, 3f, x2, 68)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 18*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jalr instruction of the RISC-V C extension for the cjalr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjalr)
RVTEST_SIGBASE( x10,signature_x10_1)
inst_0:
// rs1==x6,
// opcode:c.jalr; op1:x6
TEST_CJALR_OP(x11, x6, x10, 0)
inst_1:
// rs1==x4,
// opcode:c.jalr; op1:x4
TEST_CJALR_OP(x11, x4, x10, 4)
inst_2:
// rs1==x3,
// opcode:c.jalr; op1:x3
TEST_CJALR_OP(x11, x3, x10, 8)
inst_3:
// rs1==x1,
// opcode:c.jalr; op1:x1
TEST_CJALR_OP(x11, x1, x10, 12)
inst_4:
// rs1==x12,
// opcode:c.jalr; op1:x12
TEST_CJALR_OP(x11, x12, x10, 16)
inst_5:
// rs1==x2,
// opcode:c.jalr; op1:x2
TEST_CJALR_OP(x11, x2, x10, 20)
inst_6:
// rs1==x8,
// opcode:c.jalr; op1:x8
TEST_CJALR_OP(x11, x8, x10, 24)
inst_7:
// rs1==x7,
// opcode:c.jalr; op1:x7
TEST_CJALR_OP(x11, x7, x10, 28)
inst_8:
// rs1==x15,
// opcode:c.jalr; op1:x15
TEST_CJALR_OP(x11, x15, x10, 32)
inst_9:
// rs1==x5,
// opcode:c.jalr; op1:x5
TEST_CJALR_OP(x11, x5, x10, 36)
inst_10:
// rs1==x9,
// opcode:c.jalr; op1:x9
TEST_CJALR_OP(x11, x9, x10, 40)
inst_11:
// rs1==x14,
// opcode:c.jalr; op1:x14
TEST_CJALR_OP(x3, x14, x10, 44)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_12:
// rs1==x11,
// opcode:c.jalr; op1:x11
TEST_CJALR_OP(x3, x11, x2, 0)
inst_13:
// rs1==x13,
// opcode:c.jalr; op1:x13
TEST_CJALR_OP(x3, x13, x2, 4)
inst_14:
// rs1==x10,
// opcode:c.jalr; op1:x10
TEST_CJALR_OP(x3, x10, x2, 8)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x10_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x10_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x6,
// opcode: c.jr; op1:x6
TEST_CJR_OP(x7, x6, x1, 0)
inst_1:
// rs1==x15,
// opcode: c.jr; op1:x15
TEST_CJR_OP(x7, x15, x1, 4)
inst_2:
// rs1==x14,
// opcode: c.jr; op1:x14
TEST_CJR_OP(x7, x14, x1, 8)
inst_3:
// rs1==x13,
// opcode: c.jr; op1:x13
TEST_CJR_OP(x7, x13, x1, 12)
inst_4:
// rs1==x3,
// opcode: c.jr; op1:x3
TEST_CJR_OP(x7, x3, x1, 16)
inst_5:
// rs1==x8,
// opcode: c.jr; op1:x8
TEST_CJR_OP(x7, x8, x1, 20)
inst_6:
// rs1==x2,
// opcode: c.jr; op1:x2
TEST_CJR_OP(x7, x2, x1, 24)
inst_7:
// rs1==x4,
// opcode: c.jr; op1:x4
TEST_CJR_OP(x7, x4, x1, 28)
inst_8:
// rs1==x12,
// opcode: c.jr; op1:x12
TEST_CJR_OP(x7, x12, x1, 32)
inst_9:
// rs1==x5,
// opcode: c.jr; op1:x5
TEST_CJR_OP(x7, x5, x1, 36)
inst_10:
// rs1==x7,
// opcode: c.jr; op1:x7
TEST_CJR_OP(x3, x7, x1, 40)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_11:
// rs1==x9,
// opcode: c.jr; op1:x9
TEST_CJR_OP(x3, x9, x2, 0)
inst_12:
// rs1==x1,
// opcode: c.jr; op1:x1
TEST_CJR_OP(x3, x1, x2, 4)
inst_13:
// rs1==x11,
// opcode: c.jr; op1:x11
TEST_CJR_OP(x3, x11, x2, 8)
inst_14:
// rs1==x10,
// opcode: c.jr; op1:x10
TEST_CJR_OP(x3, x10, x2, 12)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 11*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

160
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S Normal file
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.li instruction of the RISC-V C extension for the cli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cli)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rd==x15, imm_val == (-2**(6-1)), imm_val == -32
// opcode:c.li; dest:x15; immval:-0x20
TEST_CASE(x7, x15, -0x20, x4, 0, c.li x15, -0x20;)
inst_1:
// rd==x8, imm_val == 31, imm_val == (2**(6-1)-1)
// opcode:c.li; dest:x8; immval:0x1f
TEST_CASE(x7, x8, 0x1f, x4, 4, c.li x8, 0x1f;)
inst_2:
// rd==x13, imm_val == -17,
// opcode:c.li; dest:x13; immval:-0x11
TEST_CASE(x7, x13, -0x11, x4, 8, c.li x13, -0x11;)
inst_3:
// rd==x6, imm_val == -9,
// opcode:c.li; dest:x6; immval:-0x9
TEST_CASE(x7, x6, -0x9, x4, 12, c.li x6, -0x9;)
inst_4:
// rd==x2, imm_val == -5,
// opcode:c.li; dest:x2; immval:-0x5
TEST_CASE(x7, x2, -0x5, x4, 16, c.li x2, -0x5;)
inst_5:
// rd==x12, imm_val == -3,
// opcode:c.li; dest:x12; immval:-0x3
TEST_CASE(x7, x12, -0x3, x4, 20, c.li x12, -0x3;)
inst_6:
// rd==x1, imm_val == -2,
// opcode:c.li; dest:x1; immval:-0x2
TEST_CASE(x7, x1, -0x2, x4, 24, c.li x1, -0x2;)
inst_7:
// rd==x14, imm_val == 16,
// opcode:c.li; dest:x14; immval:0x10
TEST_CASE(x7, x14, 0x10, x4, 28, c.li x14, 0x10;)
inst_8:
// rd==x3, imm_val == 0,
// opcode:c.li; dest:x3; immval:0x0
TEST_CASE(x7, x3, 0x0, x4, 32, c.li x3, 0x0;)
inst_9:
// rd==x5, imm_val == 8,
// opcode:c.li; dest:x5; immval:0x8
TEST_CASE(x7, x5, 0x8, x4, 36, c.li x5, 0x8;)
inst_10:
// rd==x10, imm_val == 4,
// opcode:c.li; dest:x10; immval:0x4
TEST_CASE(x7, x10, 0x4, x4, 40, c.li x10, 0x4;)
inst_11:
// rd==x0, imm_val == 2,
// opcode:c.li; dest:x0; immval:0x2
TEST_CASE(x2, x0, 0, x4, 44, c.li x0, 0x2;)
inst_12:
// rd==x11, imm_val == 1,
// opcode:c.li; dest:x11; immval:0x1
TEST_CASE(x2, x11, 0x1, x4, 48, c.li x11, 0x1;)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x7, imm_val == -22,
// opcode:c.li; dest:x7; immval:-0x16
TEST_CASE(x2, x7, -0x16, x1, 0, c.li x7, -0x16;)
inst_14:
// rd==x4, imm_val == 21,
// opcode:c.li; dest:x4; immval:0x15
TEST_CASE(x2, x4, 0x15, x1, 4, c.li x4, 0x15;)
inst_15:
// rd==x9,
// opcode:c.li; dest:x9; immval:0x0
TEST_CASE(x2, x9, 0x0, x1, 8, c.li x9, 0x0;)
inst_16:
// imm_val == 2,
// opcode:c.li; dest:x10; immval:0x2
TEST_CASE(x2, x10, 0x2, x1, 12, c.li x10, 0x2;)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 4*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S Normal file
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clui)
RVTEST_SIGBASE( x2,signature_x2_1)
inst_0:
// rd==x8, rs1_val < 0 and imm_val < 32 and imm_val !=0 , imm_val == 4
// opcode:c.lui; op1:x8; dest:x8 op1val:-0x1000001; immval:0x4
TEST_CI_OP( c.lui, x8, 0x4000, -0x1000001, 0x4, x2, 0, x5)
inst_1:
// rd==x10, imm_val == 31,
// opcode:c.lui; op1:x10; dest:x10 op1val:-0x4; immval:0x1f
TEST_CI_OP( c.lui, x10, 0x1f000, -0x4, 0x1f, x2, 4, x5)
inst_2:
// rd==x6, imm_val == 47, rs1_val > 0 and imm_val > 32
// opcode:c.lui; op1:x6; dest:x6 op1val:0x4000; immval:0xfffef
TEST_CI_OP( c.lui, x6, -0x11000, 0x4000, 0xfffef, x2, 8, x5)
inst_3:
// rd==x9, imm_val == 55, rs1_val < 0 and imm_val > 32
// opcode:c.lui; op1:x9; dest:x9 op1val:-0x3; immval:0xffff7
TEST_CI_OP( c.lui, x9, -0x9000, -0x3, 0xffff7, x2, 12, x5)
inst_4:
// rd==x15, imm_val == 59,
// opcode:c.lui; op1:x15; dest:x15 op1val:0x4; immval:0xffffb
TEST_CI_OP( c.lui, x15, -0x5000, 0x4, 0xffffb, x2, 16, x5)
inst_5:
// rd==x1, imm_val == 61,
// opcode:c.lui; op1:x1; dest:x1 op1val:-0x20000001; immval:0xffffd
TEST_CI_OP( c.lui, x1, -0x3000, -0x20000001, 0xffffd, x2, 20, x5)
inst_6:
// rd==x0, imm_val == 62,
// opcode:c.lui; op1:x0; dest:x0 op1val:-0x20000001; immval:0xffffe
TEST_CI_OP( c.lui, x0, 0, -0x20000001, 0xffffe, x2, 24, x5)
inst_7:
// rd==x7, imm_val == 32,
// opcode:c.lui; op1:x7; dest:x7 op1val:0x4000; immval:0xfffe0
TEST_CI_OP( c.lui, x7, -0x20000, 0x4000, 0xfffe0, x2, 28, x5)
inst_8:
// rd==x3, rs1_val > 0 and imm_val < 32 and imm_val !=0 ,
// opcode:c.lui; op1:x3; dest:x3 op1val:0x10; immval:0xc
TEST_CI_OP( c.lui, x3, 0xc000, 0x10, 0xc, x2, 32, x5)
inst_9:
// rd==x4, imm_val == 16,
// opcode:c.lui; op1:x4; dest:x4 op1val:0x7fffffff; immval:0x10
TEST_CI_OP( c.lui, x4, 0x10000, 0x7fffffff, 0x10, x2, 36, x5)
inst_10:
// rd==x11, imm_val == 8,
// opcode:c.lui; op1:x11; dest:x11 op1val:-0x20001; immval:0x8
TEST_CI_OP( c.lui, x11, 0x8000, -0x20001, 0x8, x2, 40, x5)
inst_11:
// rd==x12, imm_val == 2,
// opcode:c.lui; op1:x12; dest:x12 op1val:0x200000; immval:0x2
TEST_CI_OP( c.lui, x12, 0x2000, 0x200000, 0x2, x2, 44, x5)
inst_12:
// rd==x13, imm_val == 1,
// opcode:c.lui; op1:x13; dest:x13 op1val:-0x2001; immval:0x1
TEST_CI_OP( c.lui, x13, 0x1000, -0x2001, 0x1, x2, 48, x3)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_13:
// rd==x14, imm_val == 42,
// opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffea
TEST_CI_OP( c.lui, x14, -0x16000, 0x400000, 0xfffea, x1, 0, x3)
inst_14:
// rd==x5, imm_val == 21,
// opcode:c.lui; op1:x5; dest:x5 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.lui, x5, 0x15000, -0x10001, 0x15, x1, 4, x3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x2_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x2_1:
.fill 13*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 2*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

135
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 == rd, rd==x8, rs1==x8, imm_val == 0,
// opcode: c.lw; op1:x8; dest:x8; immval:0x0
TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0)
inst_1:
// rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0
// opcode: c.lw; op1:x12; dest:x14; immval:0x3c
TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0)
inst_2:
// rd==x15, rs1==x11, imm_val == 92,
// opcode: c.lw; op1:x11; dest:x15; immval:0x5c
TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0)
inst_3:
// rd==x10, rs1==x15, imm_val == 108,
// opcode: c.lw; op1:x15; dest:x10; immval:0x6c
TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0)
inst_4:
// rd==x13, rs1==x14, imm_val == 116,
// opcode: c.lw; op1:x14; dest:x13; immval:0x74
TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0)
inst_5:
// rd==x11, rs1==x13, imm_val == 120,
// opcode: c.lw; op1:x13; dest:x11; immval:0x78
TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0)
inst_6:
// rd==x12, rs1==x10, imm_val == 64,
// opcode: c.lw; op1:x10; dest:x12; immval:0x40
TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0)
inst_7:
// rd==x9, imm_val == 32,
// opcode: c.lw; op1:x10; dest:x9; immval:0x20
TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0)
inst_8:
// rs1==x9, imm_val == 16,
// opcode: c.lw; op1:x9; dest:x8; immval:0x10
TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0)
inst_9:
// imm_val == 8,
// opcode: c.lw; op1:x11; dest:x10; immval:0x8
TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0)
inst_10:
// imm_val == 4,
// opcode: c.lw; op1:x11; dest:x10; immval:0x4
TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0)
inst_11:
// imm_val == 40,
// opcode: c.lw; op1:x11; dest:x10; immval:0x28
TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0)
inst_12:
// imm_val == 84,
// opcode: c.lw; op1:x11; dest:x10; immval:0x54
TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 13*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

150
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S Normal file
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clwsp)
RVTEST_SIGBASE( x5,signature_x5_1)
inst_0:
// rd==x2, imm_val == 0,
// opcode: c.lwsp; op1:x2; dest:x2; immval:0x0
TEST_LOAD(x5,x7,0,x2,x2,0x0,0,c.lwsp,0)
inst_1:
// rd==x11, imm_val == 124, imm_val > 0
// opcode: c.lwsp; op1:x2; dest:x11; immval:0x7c
TEST_LOAD(x5,x7,0,x2,x11,0x7c,4,c.lwsp,0)
inst_2:
// rd==x3, imm_val == 188,
// opcode: c.lwsp; op1:x2; dest:x3; immval:0xbc
TEST_LOAD(x5,x7,0,x2,x3,0xbc,8,c.lwsp,0)
inst_3:
// rd==x6, imm_val == 220,
// opcode: c.lwsp; op1:x2; dest:x6; immval:0xdc
TEST_LOAD(x5,x7,0,x2,x6,0xdc,12,c.lwsp,0)
inst_4:
// rd==x9, imm_val == 236,
// opcode: c.lwsp; op1:x2; dest:x9; immval:0xec
TEST_LOAD(x5,x7,0,x2,x9,0xec,16,c.lwsp,0)
inst_5:
// rd==x1, imm_val == 244,
// opcode: c.lwsp; op1:x2; dest:x1; immval:0xf4
TEST_LOAD(x5,x7,0,x2,x1,0xf4,20,c.lwsp,0)
inst_6:
// rd==x4, imm_val == 248,
// opcode: c.lwsp; op1:x2; dest:x4; immval:0xf8
TEST_LOAD(x5,x7,0,x2,x4,0xf8,24,c.lwsp,0)
inst_7:
// rd==x8, imm_val == 128,
// opcode: c.lwsp; op1:x2; dest:x8; immval:0x80
TEST_LOAD(x5,x7,0,x2,x8,0x80,28,c.lwsp,0)
inst_8:
// rd==x15, imm_val == 64,
// opcode: c.lwsp; op1:x2; dest:x15; immval:0x40
TEST_LOAD(x5,x7,0,x2,x15,0x40,32,c.lwsp,0)
inst_9:
// rd==x12, imm_val == 32,
// opcode: c.lwsp; op1:x2; dest:x12; immval:0x20
TEST_LOAD(x5,x7,0,x2,x12,0x20,36,c.lwsp,0)
inst_10:
// rd==x10, imm_val == 16,
// opcode: c.lwsp; op1:x2; dest:x10; immval:0x10
TEST_LOAD(x5,x7,0,x2,x10,0x10,40,c.lwsp,0)
inst_11:
// rd==x14, imm_val == 8,
// opcode: c.lwsp; op1:x2; dest:x14; immval:0x8
TEST_LOAD(x5,x3,0,x2,x14,0x8,44,c.lwsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rd==x13, imm_val == 4,
// opcode: c.lwsp; op1:x2; dest:x13; immval:0x4
TEST_LOAD(x1,x3,0,x2,x13,0x4,0,c.lwsp,0)
inst_13:
// rd==x5, imm_val == 168,
// opcode: c.lwsp; op1:x2; dest:x5; immval:0xa8
TEST_LOAD(x1,x3,0,x2,x5,0xa8,4,c.lwsp,0)
inst_14:
// rd==x7, imm_val == 84,
// opcode: c.lwsp; op1:x2; dest:x7; immval:0x54
TEST_LOAD(x1,x3,0,x2,x7,0x54,8,c.lwsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x5_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x5_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

500
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S Normal file
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@ -0,0 +1,500 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.mv instruction of the RISC-V C extension for the cmv covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cmv)
RVTEST_SIGBASE( x4,signature_x4_1)
inst_0:
// rs2 == rd and rs2 != 0, rd==x13, rs2==x13, rs2_val == (-2**(xlen-1)), rs2_val == -2147483648
// opcode: c.mv; op2:x13; dest:x13; op2val:-0x80000000
TEST_CMV_OP( c.mv, x13, x13, -0x80000000, -0x80000000, x4, 0, x10)
inst_1:
// rs2 != rd and rs2 != 0, rd==x3, rs2==x14, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
// opcode: c.mv; op2:x14; dest:x3; op2val:0x7fffffff
TEST_CMV_OP( c.mv, x3, x14, 0x7fffffff, 0x7fffffff, x4, 4, x10)
inst_2:
// rd==x15, rs2==x5, rs2_val == -1073741825,
// opcode: c.mv; op2:x5; dest:x15; op2val:-0x40000001
TEST_CMV_OP( c.mv, x15, x5, -0x40000001, -0x40000001, x4, 8, x10)
inst_3:
// rd==x6, rs2==x2, rs2_val == -536870913,
// opcode: c.mv; op2:x2; dest:x6; op2val:-0x20000001
TEST_CMV_OP( c.mv, x6, x2, -0x20000001, -0x20000001, x4, 12, x10)
inst_4:
// rd==x9, rs2==x7, rs2_val == -268435457,
// opcode: c.mv; op2:x7; dest:x9; op2val:-0x10000001
TEST_CMV_OP( c.mv, x9, x7, -0x10000001, -0x10000001, x4, 16, x10)
inst_5:
// rd==x2, rs2==x11, rs2_val == -134217729,
// opcode: c.mv; op2:x11; dest:x2; op2val:-0x8000001
TEST_CMV_OP( c.mv, x2, x11, -0x8000001, -0x8000001, x4, 20, x10)
inst_6:
// rd==x5, rs2==x15, rs2_val == -67108865,
// opcode: c.mv; op2:x15; dest:x5; op2val:-0x4000001
TEST_CMV_OP( c.mv, x5, x15, -0x4000001, -0x4000001, x4, 24, x10)
inst_7:
// rd==x11, rs2==x9, rs2_val == -33554433,
// opcode: c.mv; op2:x9; dest:x11; op2val:-0x2000001
TEST_CMV_OP( c.mv, x11, x9, -0x2000001, -0x2000001, x4, 28, x10)
inst_8:
// rd==x1, rs2==x8, rs2_val == -16777217,
// opcode: c.mv; op2:x8; dest:x1; op2val:-0x1000001
TEST_CMV_OP( c.mv, x1, x8, -0x1000001, -0x1000001, x4, 32, x10)
RVTEST_SIGBASE( x2,signature_x2_0)
inst_9:
// rd==x7, rs2==x6, rs2_val == -8388609,
// opcode: c.mv; op2:x6; dest:x7; op2val:-0x800001
TEST_CMV_OP( c.mv, x7, x6, -0x800001, -0x800001, x2, 0, x5)
inst_10:
// rd==x12, rs2==x1, rs2_val == -4194305,
// opcode: c.mv; op2:x1; dest:x12; op2val:-0x400001
TEST_CMV_OP( c.mv, x12, x1, -0x400001, -0x400001, x2, 4, x5)
inst_11:
// rd==x14, rs2==x4, rs2_val == -2097153,
// opcode: c.mv; op2:x4; dest:x14; op2val:-0x200001
TEST_CMV_OP( c.mv, x14, x4, -0x200001, -0x200001, x2, 8, x5)
inst_12:
// rd==x10, rs2==x12, rs2_val == -1048577,
// opcode: c.mv; op2:x12; dest:x10; op2val:-0x100001
TEST_CMV_OP( c.mv, x10, x12, -0x100001, -0x100001, x2, 12, x5)
inst_13:
// rd==x8, rs2==x3, rs2_val == -524289,
// opcode: c.mv; op2:x3; dest:x8; op2val:-0x80001
TEST_CMV_OP( c.mv, x8, x3, -0x80001, -0x80001, x2, 16, x5)
inst_14:
// rd==x0, rs2==x10, rs2_val == -262145,
// opcode: c.mv; op2:x10; dest:x0; op2val:-0x40001
TEST_CMV_OP( c.mv, x0, x10, 0, -0x40001, x2, 20, x5)
inst_15:
// rd==x4, rs2_val == -131073,
// opcode: c.mv; op2:x12; dest:x4; op2val:-0x20001
TEST_CMV_OP( c.mv, x4, x12, -0x20001, -0x20001, x2, 24, x5)
inst_16:
// rs2_val == -65537,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x10001
TEST_CMV_OP( c.mv, x10, x11, -0x10001, -0x10001, x2, 28, x5)
inst_17:
// rs2_val == -32769,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x8001
TEST_CMV_OP( c.mv, x10, x11, -0x8001, -0x8001, x2, 32, x5)
inst_18:
// rs2_val == -16385,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x4001
TEST_CMV_OP( c.mv, x10, x11, -0x4001, -0x4001, x2, 36, x5)
inst_19:
// rs2_val == -8193,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2001
TEST_CMV_OP( c.mv, x10, x11, -0x2001, -0x2001, x2, 40, x5)
inst_20:
// rs2_val == -4097,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x1001
TEST_CMV_OP( c.mv, x10, x11, -0x1001, -0x1001, x2, 44, x5)
inst_21:
// rs2_val == -2049,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x801
TEST_CMV_OP( c.mv, x10, x11, -0x801, -0x801, x2, 48, x5)
inst_22:
// rs2_val == -1025,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x401
TEST_CMV_OP( c.mv, x10, x11, -0x401, -0x401, x2, 52, x5)
inst_23:
// rs2_val == -513,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x201
TEST_CMV_OP( c.mv, x10, x11, -0x201, -0x201, x2, 56, x5)
inst_24:
// rs2_val == -257,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x101
TEST_CMV_OP( c.mv, x10, x11, -0x101, -0x101, x2, 60, x5)
inst_25:
// rs2_val == -129,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x81
TEST_CMV_OP( c.mv, x10, x11, -0x81, -0x81, x2, 64, x5)
inst_26:
// rs2_val == -65,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x41
TEST_CMV_OP( c.mv, x10, x11, -0x41, -0x41, x2, 68, x5)
inst_27:
// rs2_val == -33,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x21
TEST_CMV_OP( c.mv, x10, x11, -0x21, -0x21, x2, 72, x5)
inst_28:
// rs2_val == -17,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x11
TEST_CMV_OP( c.mv, x10, x11, -0x11, -0x11, x2, 76, x5)
inst_29:
// rs2_val == -9,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x9
TEST_CMV_OP( c.mv, x10, x11, -0x9, -0x9, x2, 80, x5)
inst_30:
// rs2_val == -5,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x5
TEST_CMV_OP( c.mv, x10, x11, -0x5, -0x5, x2, 84, x5)
inst_31:
// rs2_val == -3,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x3
TEST_CMV_OP( c.mv, x10, x11, -0x3, -0x3, x2, 88, x5)
inst_32:
// rs2_val == -2,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2
TEST_CMV_OP( c.mv, x10, x11, -0x2, -0x2, x2, 92, x5)
inst_33:
// rs2_val == 1073741824,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000000
TEST_CMV_OP( c.mv, x10, x11, 0x40000000, 0x40000000, x2, 96, x5)
inst_34:
// rs2_val == 536870912,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000000
TEST_CMV_OP( c.mv, x10, x11, 0x20000000, 0x20000000, x2, 100, x5)
inst_35:
// rs2_val == 268435456,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000000
TEST_CMV_OP( c.mv, x10, x11, 0x10000000, 0x10000000, x2, 104, x5)
inst_36:
// rs2_val == 134217728,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000000
TEST_CMV_OP( c.mv, x10, x11, 0x8000000, 0x8000000, x2, 108, x5)
inst_37:
// rs2_val == 67108864,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000000
TEST_CMV_OP( c.mv, x10, x11, 0x4000000, 0x4000000, x2, 112, x5)
inst_38:
// rs2_val == 33554432,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000000
TEST_CMV_OP( c.mv, x10, x11, 0x2000000, 0x2000000, x2, 116, x5)
inst_39:
// rs2_val == 16777216,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000000
TEST_CMV_OP( c.mv, x10, x11, 0x1000000, 0x1000000, x2, 120, x5)
inst_40:
// rs2_val == 8388608,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800000
TEST_CMV_OP( c.mv, x10, x11, 0x800000, 0x800000, x2, 124, x5)
inst_41:
// rs2_val == 4194304,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400000
TEST_CMV_OP( c.mv, x10, x11, 0x400000, 0x400000, x2, 128, x5)
inst_42:
// rs2_val == 2097152,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200000
TEST_CMV_OP( c.mv, x10, x11, 0x200000, 0x200000, x2, 132, x5)
inst_43:
// rs2_val == 1048576,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100000
TEST_CMV_OP( c.mv, x10, x11, 0x100000, 0x100000, x2, 136, x5)
inst_44:
// rs2_val == 524288,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80000
TEST_CMV_OP( c.mv, x10, x11, 0x80000, 0x80000, x2, 140, x5)
inst_45:
// rs2_val == 262144,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000
TEST_CMV_OP( c.mv, x10, x11, 0x40000, 0x40000, x2, 144, x5)
inst_46:
// rs2_val == 131072,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000
TEST_CMV_OP( c.mv, x10, x11, 0x20000, 0x20000, x2, 148, x5)
inst_47:
// rs2_val == 65536,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000
TEST_CMV_OP( c.mv, x10, x11, 0x10000, 0x10000, x2, 152, x5)
inst_48:
// rs2_val == 32768,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000
TEST_CMV_OP( c.mv, x10, x11, 0x8000, 0x8000, x2, 156, x5)
inst_49:
// rs2_val == 16384,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000
TEST_CMV_OP( c.mv, x10, x11, 0x4000, 0x4000, x2, 160, x5)
inst_50:
// rs2_val == 8192,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000
TEST_CMV_OP( c.mv, x10, x11, 0x2000, 0x2000, x2, 164, x5)
inst_51:
// rs2_val == 4096,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000
TEST_CMV_OP( c.mv, x10, x11, 0x1000, 0x1000, x2, 168, x5)
inst_52:
// rs2_val == 2048,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x800
TEST_CMV_OP( c.mv, x10, x11, 0x800, 0x800, x2, 172, x5)
inst_53:
// rs2_val == 1024,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x400
TEST_CMV_OP( c.mv, x10, x11, 0x400, 0x400, x2, 176, x5)
inst_54:
// rs2_val == 512,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x200
TEST_CMV_OP( c.mv, x10, x11, 0x200, 0x200, x2, 180, x5)
inst_55:
// rs2_val == 256,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x100
TEST_CMV_OP( c.mv, x10, x11, 0x100, 0x100, x2, 184, x5)
inst_56:
// rs2_val == 128,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x80
TEST_CMV_OP( c.mv, x10, x11, 0x80, 0x80, x2, 188, x5)
inst_57:
// rs2_val == 64,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x40
TEST_CMV_OP( c.mv, x10, x11, 0x40, 0x40, x2, 192, x5)
inst_58:
// rs2_val == 1,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x1
TEST_CMV_OP( c.mv, x10, x11, 0x1, 0x1, x2, 196, x5)
inst_59:
// rs2_val==46341,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb505
TEST_CMV_OP( c.mv, x10, x11, 0xb505, 0xb505, x2, 200, x5)
inst_60:
// rs2_val==-46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb503
TEST_CMV_OP( c.mv, x10, x11, -0xb503, -0xb503, x2, 204, x5)
inst_61:
// rs2_val==1717986919,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666667
TEST_CMV_OP( c.mv, x10, x11, 0x66666667, 0x66666667, x2, 208, x5)
inst_62:
// rs2_val==858993460,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333334
TEST_CMV_OP( c.mv, x10, x11, 0x33333334, 0x33333334, x2, 212, x5)
inst_63:
// rs2_val==6,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x6
TEST_CMV_OP( c.mv, x10, x11, 0x6, 0x6, x2, 216, x5)
inst_64:
// rs2_val==-1431655765,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555555
TEST_CMV_OP( c.mv, x10, x11, -0x55555555, -0x55555555, x2, 220, x5)
inst_65:
// rs2_val==1431655766,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555556
TEST_CMV_OP( c.mv, x10, x11, 0x55555556, 0x55555556, x2, 224, x5)
inst_66:
// rs2_val==4, rs2_val == 4
// opcode: c.mv; op2:x11; dest:x10; op2val:0x4
TEST_CMV_OP( c.mv, x10, x11, 0x4, 0x4, x2, 228, x5)
inst_67:
// rs2_val==46339,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb503
TEST_CMV_OP( c.mv, x10, x11, 0xb503, 0xb503, x2, 232, x5)
inst_68:
// rs2_val==0, rs2_val == 0
// opcode: c.mv; op2:x11; dest:x10; op2val:0x0
TEST_CMV_OP( c.mv, x10, x11, 0x0, 0x0, x2, 236, x5)
inst_69:
// rs2_val==1717986917,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666665
TEST_CMV_OP( c.mv, x10, x11, 0x66666665, 0x66666665, x2, 240, x5)
inst_70:
// rs2_val==858993458,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333332
TEST_CMV_OP( c.mv, x10, x11, 0x33333332, 0x33333332, x2, 244, x5)
inst_71:
// rs2_val==1431655764,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555554
TEST_CMV_OP( c.mv, x10, x11, 0x55555554, 0x55555554, x2, 248, x5)
inst_72:
// rs2_val==2, rs2_val == 2
// opcode: c.mv; op2:x11; dest:x10; op2val:0x2
TEST_CMV_OP( c.mv, x10, x11, 0x2, 0x2, x2, 252, x5)
inst_73:
// rs2_val==46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:0xb504
TEST_CMV_OP( c.mv, x10, x11, 0xb504, 0xb504, x2, 256, x5)
inst_74:
// rs2_val==-46340,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb504
TEST_CMV_OP( c.mv, x10, x11, -0xb504, -0xb504, x2, 260, x5)
inst_75:
// rs2_val==1717986918,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666666
TEST_CMV_OP( c.mv, x10, x11, 0x66666666, 0x66666666, x2, 264, x5)
inst_76:
// rs2_val==858993459,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333333
TEST_CMV_OP( c.mv, x10, x11, 0x33333333, 0x33333333, x2, 268, x5)
inst_77:
// rs2_val==5,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x5
TEST_CMV_OP( c.mv, x10, x11, 0x5, 0x5, x2, 272, x5)
inst_78:
// rs2_val==-1431655766, rs2_val == -1431655766
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555556
TEST_CMV_OP( c.mv, x10, x11, -0x55555556, -0x55555556, x2, 276, x5)
inst_79:
// rs2_val==1431655765, rs2_val == 1431655765
// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555555
TEST_CMV_OP( c.mv, x10, x11, 0x55555555, 0x55555555, x2, 280, x5)
inst_80:
// rs2_val == 32,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x20
TEST_CMV_OP( c.mv, x10, x11, 0x20, 0x20, x2, 284, x5)
inst_81:
// rs2_val == 16,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x10
TEST_CMV_OP( c.mv, x10, x11, 0x10, 0x10, x2, 288, x5)
inst_82:
// rs2_val == 8,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x8
TEST_CMV_OP( c.mv, x10, x11, 0x8, 0x8, x2, 292, x5)
inst_83:
// rs2_val==3,
// opcode: c.mv; op2:x11; dest:x10; op2val:0x3
TEST_CMV_OP( c.mv, x10, x11, 0x3, 0x3, x2, 296, x5)
inst_84:
// rs2_val == -262145,
// opcode: c.mv; op2:x11; dest:x10; op2val:-0x40001
TEST_CMV_OP( c.mv, x10, x11, -0x40001, -0x40001, x2, 300, x5)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x4_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x4_1:
.fill 9*(XLEN/32),4,0xdeadbeef
signature_x2_0:
.fill 76*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

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@ -0,0 +1,140 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.nop instruction of the RISC-V C extension for the cnop covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cnop)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// imm_val == 21,
// opcode:c.nop; immval:0x15
TEST_CNOP_OP(c.nop, x2, 0x15, x1, 0)
inst_1:
// imm_val == 31,
// opcode:c.nop; immval:0x1f
TEST_CNOP_OP(c.nop, x2, 0x1f, x1, 4)
inst_2:
// imm_val == -17,
// opcode:c.nop; immval:-0x11
TEST_CNOP_OP(c.nop, x2, -0x11, x1, 8)
inst_3:
// imm_val == -9,
// opcode:c.nop; immval:-0x9
TEST_CNOP_OP(c.nop, x2, -0x9, x1, 12)
inst_4:
// imm_val == -5,
// opcode:c.nop; immval:-0x5
TEST_CNOP_OP(c.nop, x2, -0x5, x1, 16)
inst_5:
// imm_val == -3,
// opcode:c.nop; immval:-0x3
TEST_CNOP_OP(c.nop, x2, -0x3, x1, 20)
inst_6:
// imm_val == -2,
// opcode:c.nop; immval:-0x2
TEST_CNOP_OP(c.nop, x2, -0x2, x1, 24)
inst_7:
// imm_val == -32,
// opcode:c.nop; immval:-0x20
TEST_CNOP_OP(c.nop, x2, -0x20, x1, 28)
inst_8:
// imm_val == 16,
// opcode:c.nop; immval:0x10
TEST_CNOP_OP(c.nop, x2, 0x10, x1, 32)
inst_9:
// imm_val == 8,
// opcode:c.nop; immval:0x8
TEST_CNOP_OP(c.nop, x2, 0x8, x1, 36)
inst_10:
// imm_val == 4,
// opcode:c.nop; immval:0x4
TEST_CNOP_OP(c.nop, x2, 0x4, x1, 40)
inst_11:
// imm_val == 2,
// opcode:c.nop; immval:0x2
TEST_CNOP_OP(c.nop, x2, 0x2, x1, 44)
inst_12:
// imm_val == 1,
// opcode:c.nop; immval:0x1
TEST_CNOP_OP(c.nop, x2, 0x1, x1, 48)
inst_13:
// imm_val == -22,
// opcode:c.nop; immval:-0x16
TEST_CNOP_OP(c.nop, x2, -0x16, x1, 52)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 14*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

2985
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500
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.slli instruction of the RISC-V C extension for the cslli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cslli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rd==x11, rs1_val < 0 and imm_val < xlen, rs1_val == -65537, imm_val == 29
// opcode:c.slli; op1:x11; dest:x11 op1val:-0x10001; immval:0x1d
TEST_CI_OP( c.slli, x11, 0xe0000000, -0x10001, 0x1d, x1, 0, x2)
inst_1:
// rd==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0xb
TEST_CI_OP( c.slli, x8, 0xfffff800, 0x7fffffff, 0xb, x1, 4, x2)
inst_2:
// rd==x9, rs1_val == -1073741825,
// opcode:c.slli; op1:x9; dest:x9 op1val:-0x40000001; immval:0xc
TEST_CI_OP( c.slli, x9, 0xfffff000, -0x40000001, 0xc, x1, 8, x2)
inst_3:
// rd==x12, rs1_val == -536870913,
// opcode:c.slli; op1:x12; dest:x12 op1val:-0x20000001; immval:0x7
TEST_CI_OP( c.slli, x12, 0xffffff80, -0x20000001, 0x7, x1, 12, x2)
inst_4:
// rd==x14, rs1_val == -268435457,
// opcode:c.slli; op1:x14; dest:x14 op1val:-0x10000001; immval:0x3
TEST_CI_OP( c.slli, x14, 0x7ffffff8, -0x10000001, 0x3, x1, 16, x2)
inst_5:
// rd==x10, rs1_val == -134217729,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8000001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8000001, 0x1f, x1, 20, x2)
inst_6:
// rd==x13, rs1_val == -67108865,
// opcode:c.slli; op1:x13; dest:x13 op1val:-0x4000001; immval:0x13
TEST_CI_OP( c.slli, x13, 0xfff80000, -0x4000001, 0x13, x1, 24, x2)
inst_7:
// rd==x15, rs1_val == -33554433, imm_val == 10
// opcode:c.slli; op1:x15; dest:x15 op1val:-0x2000001; immval:0xa
TEST_CI_OP( c.slli, x15, 0xfffffc00, -0x2000001, 0xa, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x5
TEST_CI_OP( c.slli, x10, 0xdfffffe0, -0x1000001, 0x5, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x800001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x800001, 0x1f, x1, 36, x2)
inst_10:
// rs1_val == -4194305,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x400001; immval:0x13
TEST_CI_OP( c.slli, x10, 0xfff80000, -0x400001, 0x13, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x200001; immval:0x11
TEST_CI_OP( c.slli, x10, 0xfffe0000, -0x200001, 0x11, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x100001; immval:0x9
TEST_CI_OP( c.slli, x10, 0xdffffe00, -0x100001, 0x9, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 21
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80001; immval:0x15
TEST_CI_OP( c.slli, x10, 0xffe00000, -0x80001, 0x15, x1, 52, x2)
inst_14:
// rs1_val == -262145, imm_val == 27
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x40001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x40001, 0x1b, x1, 56, x2)
inst_15:
// rs1_val == -131073, imm_val == 2
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x20001; immval:0x2
TEST_CI_OP( c.slli, x10, 0xfff7fffc, -0x20001, 0x2, x1, 60, x2)
inst_16:
// rs1_val == -32769,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x8001, 0x1f, x1, 64, x2)
inst_17:
// rs1_val == -16385,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x4001; immval:0xd
TEST_CI_OP( c.slli, x10, 0xf7ffe000, -0x4001, 0xd, x1, 68, x2)
inst_18:
// rs1_val == -8193,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2001; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x2001, 0x1d, x1, 72, x2)
inst_19:
// rs1_val == -4097,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1001; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xf8000000, -0x1001, 0x1b, x1, 76, x2)
inst_20:
// rs1_val == -2049, imm_val == 15
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x801; immval:0xf
TEST_CI_OP( c.slli, x10, 0xfbff8000, -0x801, 0xf, x1, 80, x2)
inst_21:
// rs1_val == -1025,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x401; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x401, 0x1f, x1, 84, x2)
inst_22:
// rs1_val == -513,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x201; immval:0x5
TEST_CI_OP( c.slli, x10, 0xffffbfe0, -0x201, 0x5, x1, 88, x2)
inst_23:
// rs1_val == -257,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x101; immval:0x1f
TEST_CI_OP( c.slli, x10, 0x80000000, -0x101, 0x1f, x1, 92, x2)
inst_24:
// rs1_val == -129, imm_val == 30
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x81; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, -0x81, 0x1e, x1, 96, x2)
inst_25:
// rs1_val == -65,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x41; immval:0x3
TEST_CI_OP( c.slli, x10, 0xfffffdf8, -0x41, 0x3, x1, 100, x2)
inst_26:
// rs1_val == -33, imm_val == 23
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x21; immval:0x17
TEST_CI_OP( c.slli, x10, 0xef800000, -0x21, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -17, imm_val == 1
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x11; immval:0x1
TEST_CI_OP( c.slli, x10, 0xffffffde, -0x11, 0x1, x1, 108, x2)
inst_28:
// rs1_val == -9,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x9; immval:0x1d
TEST_CI_OP( c.slli, x10, 0xe0000000, -0x9, 0x1d, x1, 112, x2)
inst_29:
// rs1_val == -5,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x5; immval:0x17
TEST_CI_OP( c.slli, x10, 0xfd800000, -0x5, 0x17, x1, 116, x2)
inst_30:
// rs1_val == -3,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0xe8000000, -0x3, 0x1b, x1, 120, x2)
inst_31:
// rs1_val == -2,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x80000000, -0x2, 0x1e, x1, 124, x2)
inst_32:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, -0x80000000, 0x1d, x1, 128, x2)
inst_33:
// rs1_val == 1073741824,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x40000000, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == 536870912,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x20000000, 0x13, x1, 136, x2)
inst_35:
// rs1_val == 268435456,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x10000000, 0x1e, x1, 140, x2)
inst_36:
// rs1_val == 134217728,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x0, 0x8000000, 0x9, x1, 144, x2)
inst_37:
// rs1_val == 67108864,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000000; immval:0x2
TEST_CI_OP( c.slli, x10, 0x10000000, 0x4000000, 0x2, x1, 148, x2)
inst_38:
// rs1_val == 33554432,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x40000000, 0x2000000, 0x5, x1, 152, x2)
inst_39:
// rs1_val == 16777216,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000000; immval:0x5
TEST_CI_OP( c.slli, x10, 0x20000000, 0x1000000, 0x5, x1, 156, x2)
inst_40:
// rs1_val == 8388608,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800000; immval:0x6
TEST_CI_OP( c.slli, x10, 0x20000000, 0x800000, 0x6, x1, 160, x2)
inst_41:
// rs1_val == 4194304,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0xe
TEST_CI_OP( c.slli, x10, 0x0, 0x400000, 0xe, x1, 164, x2)
inst_42:
// rs1_val == 2097152,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200000; immval:0x7
TEST_CI_OP( c.slli, x10, 0x10000000, 0x200000, 0x7, x1, 168, x2)
inst_43:
// rs1_val == 1048576,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100000; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x100000, 0x1b, x1, 172, x2)
inst_44:
// rs1_val == 524288,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80000; immval:0x13
TEST_CI_OP( c.slli, x10, 0x0, 0x80000, 0x13, x1, 176, x2)
inst_45:
// rs1_val == 262144,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000000, 0x40000, 0x9, x1, 180, x2)
inst_46:
// rs1_val == 131072,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000; immval:0x12
TEST_CI_OP( c.slli, x10, 0x0, 0x20000, 0x12, x1, 184, x2)
inst_47:
// rs1_val == 65536,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000; immval:0xb
TEST_CI_OP( c.slli, x10, 0x8000000, 0x10000, 0xb, x1, 188, x2)
inst_48:
// rs1_val == 32768,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x10000, 0x8000, 0x1, x1, 192, x2)
inst_49:
// rs1_val == 16384,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000; immval:0x1e
TEST_CI_OP( c.slli, x10, 0x0, 0x4000, 0x1e, x1, 196, x2)
inst_50:
// rs1_val == 8192,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000; immval:0x1
TEST_CI_OP( c.slli, x10, 0x4000, 0x2000, 0x1, x1, 200, x2)
inst_51:
// rs1_val == 4096,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000; immval:0x9
TEST_CI_OP( c.slli, x10, 0x200000, 0x1000, 0x9, x1, 204, x2)
inst_52:
// rs1_val == 2048,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x800; immval:0x11
TEST_CI_OP( c.slli, x10, 0x10000000, 0x800, 0x11, x1, 208, x2)
inst_53:
// rs1_val == 1024,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400; immval:0x1d
TEST_CI_OP( c.slli, x10, 0x0, 0x400, 0x1d, x1, 212, x2)
inst_54:
// rs1_val == 512,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x200; immval:0xd
TEST_CI_OP( c.slli, x10, 0x400000, 0x200, 0xd, x1, 216, x2)
inst_55:
// rs1_val == 256,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x100; immval:0x12
TEST_CI_OP( c.slli, x10, 0x4000000, 0x100, 0x12, x1, 220, x2)
inst_56:
// rs1_val == 128,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x80; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2000, 0x80, 0x6, x1, 224, x2)
inst_57:
// rs1_val == 64,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x40; immval:0x9
TEST_CI_OP( c.slli, x10, 0x8000, 0x40, 0x9, x1, 228, x2)
inst_58:
// rs1_val == 32,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x0, 0x20, 0x1b, x1, 232, x2)
inst_59:
// rs1_val == 16, rs1_val == imm_val and imm_val != 0 and imm_val < xlen, imm_val == 16
// opcode:c.slli; op1:x10; dest:x10 op1val:0x10; immval:0x10
TEST_CI_OP( c.slli, x10, 0x100000, 0x10, 0x10, x1, 236, x2)
inst_60:
// rs1_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x8; immval:0x13
TEST_CI_OP( c.slli, x10, 0x400000, 0x8, 0x13, x1, 240, x2)
inst_61:
// rs1_val == 4, rs1_val==4
// opcode:c.slli; op1:x10; dest:x10 op1val:0x4; immval:0x15
TEST_CI_OP( c.slli, x10, 0x800000, 0x4, 0x15, x1, 244, x2)
inst_62:
// rs1_val == 2, rs1_val==2
// opcode:c.slli; op1:x10; dest:x10 op1val:0x2; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x10000000, 0x2, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.slli; op1:x10; dest:x10 op1val:0x1; immval:0x13
TEST_CI_OP( c.slli, x10, 0x80000, 0x1, 0x13, x1, 252, x2)
inst_64:
// imm_val == 8,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0x8
TEST_CI_OP( c.slli, x10, 0x40000000, 0x400000, 0x8, x1, 256, x2)
inst_65:
// imm_val == 4,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x4
TEST_CI_OP( c.slli, x10, 0xfff7fff0, -0x8001, 0x4, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb505; immval:0xf
TEST_CI_OP( c.slli, x10, 0x5a828000, 0xb505, 0xf, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb503; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf400, -0xb503, 0xa, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666667; immval:0x1e
TEST_CI_OP( c.slli, x10, 0xc0000000, 0x66666667, 0x1e, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333334; immval:0x4
TEST_CI_OP( c.slli, x10, 0x33333340, 0x33333334, 0x4, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.slli, x10, 0x30, 0x6, 0x3, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x17
TEST_CI_OP( c.slli, x10, 0x55800000, -0x55555555, 0x17, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555556; immval:0x8
TEST_CI_OP( c.slli, x10, 0x55555600, 0x55555556, 0x8, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb503; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0xb503, 0x1b, x1, 292, x2)
inst_74:
// rs1_val==3,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x3; immval:0x1b
TEST_CI_OP( c.slli, x10, 0x18000000, 0x3, 0x1b, x1, 296, x2)
inst_75:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x3
TEST_CI_OP( c.slli, x10, 0x55555550, -0x55555556, 0x3, x1, 300, x2)
inst_76:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555555; immval:0x4
TEST_CI_OP( c.slli, x10, 0x55555550, 0x55555555, 0x4, x1, 304, x2)
inst_77:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.slli; op1:x10; dest:x10 op1val:0x0; immval:0x15
TEST_CI_OP( c.slli, x10, 0x0, 0x0, 0x15, x1, 308, x2)
inst_78:
// rs1_val==1717986917,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.slli, x10, 0xcccccca0, 0x66666665, 0x5, x1, 312, x2)
inst_79:
// rs1_val==858993458,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333332; immval:0x10
TEST_CI_OP( c.slli, x10, 0x33320000, 0x33333332, 0x10, x1, 316, x2)
inst_80:
// rs1_val==1431655764,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555554; immval:0x17
TEST_CI_OP( c.slli, x10, 0xaa000000, 0x55555554, 0x17, x1, 320, x2)
inst_81:
// rs1_val==46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:0xb504; immval:0x6
TEST_CI_OP( c.slli, x10, 0x2d4100, 0xb504, 0x6, x1, 324, x2)
inst_82:
// rs1_val==-46340,
// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb504; immval:0xa
TEST_CI_OP( c.slli, x10, 0xfd2bf000, -0xb504, 0xa, x1, 328, x2)
inst_83:
// rs1_val==1717986918,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666666; immval:0x12
TEST_CI_OP( c.slli, x10, 0x99980000, 0x66666666, 0x12, x1, 332, x2)
inst_84:
// rs1_val==858993459,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1
TEST_CI_OP( c.slli, x10, 0x66666666, 0x33333333, 0x1, x1, 336, x2)
inst_85:
// rs1_val==5,
// opcode:c.slli; op1:x10; dest:x10 op1val:0x5; immval:0x4
TEST_CI_OP( c.slli, x10, 0x50, 0x5, 0x4, x1, 340, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 86*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

495
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S Normal file
View file

@ -0,0 +1,495 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srai instruction of the RISC-V C extension for the csrai covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrai)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x10, rs1_val < 0 and imm_val < xlen, rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555556; immval:0xe
TEST_CI_OP( c.srai, x10, 0xfffeaaaa, -0x55555556, 0xe, x1, 0, x2)
inst_1:
// rs1==x9, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x9; dest:x9 op1val:0x7fffffff; immval:0x9
TEST_CI_OP( c.srai, x9, 0x3fffff, 0x7fffffff, 0x9, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825,
// opcode:c.srai; op1:x11; dest:x11 op1val:-0x40000001; immval:0x5
TEST_CI_OP( c.srai, x11, 0xfdffffff, -0x40000001, 0x5, x1, 8, x2)
inst_3:
// rs1==x12, rs1_val == -536870913, imm_val == 4
// opcode:c.srai; op1:x12; dest:x12 op1val:-0x20000001; immval:0x4
TEST_CI_OP( c.srai, x12, 0xfdffffff, -0x20000001, 0x4, x1, 12, x2)
inst_4:
// rs1==x14, rs1_val == -268435457, imm_val == 21
// opcode:c.srai; op1:x14; dest:x14 op1val:-0x10000001; immval:0x15
TEST_CI_OP( c.srai, x14, 0xffffff7f, -0x10000001, 0x15, x1, 16, x2)
inst_5:
// rs1==x8, rs1_val == -134217729,
// opcode:c.srai; op1:x8; dest:x8 op1val:-0x8000001; immval:0x13
TEST_CI_OP( c.srai, x8, 0xfffffeff, -0x8000001, 0x13, x1, 20, x2)
inst_6:
// rs1==x13, rs1_val == -67108865,
// opcode:c.srai; op1:x13; dest:x13 op1val:-0x4000001; immval:0xc
TEST_CI_OP( c.srai, x13, 0xffffbfff, -0x4000001, 0xc, x1, 24, x2)
inst_7:
// rs1==x15, rs1_val == -33554433, imm_val == 29
// opcode:c.srai; op1:x15; dest:x15 op1val:-0x2000001; immval:0x1d
TEST_CI_OP( c.srai, x15, 0xffffffff, -0x2000001, 0x1d, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1000001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffff7ff, -0x1000001, 0xd, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x800001; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffefffff, -0x800001, 0x3, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 10
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x400001; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffefff, -0x400001, 0xa, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x200001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xfffffeff, -0x200001, 0xd, x1, 44, x2)
inst_12:
// rs1_val == -1048577,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x100001; immval:0xd
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x100001, 0xd, x1, 48, x2)
inst_13:
// rs1_val == -524289,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80001; immval:0x5
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x80001, 0x5, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x40001; immval:0x4
TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x40001, 0x4, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x20001; immval:0x1d
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x20001, 0x1d, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x10001; immval:0x15
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x10001, 0x15, x1, 64, x2)
inst_17:
// rs1_val == -32769, imm_val == 2
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x8001; immval:0x2
TEST_CI_OP( c.srai, x10, 0xffffdfff, -0x8001, 0x2, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x4001; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x4001, 0x7, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2001; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2001, 0x12, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1001; immval:0x6
TEST_CI_OP( c.srai, x10, 0xffffffbf, -0x1001, 0x6, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x13, x1, 84, x2)
inst_22:
// rs1_val == -1025,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x401; immval:0x3
TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x401, 0x3, x1, 88, x2)
inst_23:
// rs1_val == -513, imm_val == 15
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x201; immval:0xf
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x201, 0xf, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x101; immval:0x7
TEST_CI_OP( c.srai, x10, 0xfffffffd, -0x101, 0x7, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x81; immval:0xa
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x81, 0xa, x1, 100, x2)
inst_26:
// rs1_val == -65, imm_val == 23
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x41; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x41, 0x17, x1, 104, x2)
inst_27:
// rs1_val == -33, imm_val == 30
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x21; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x21, 0x1e, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x11; immval:0x1e
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x11, 0x1e, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x5; immval:0x9
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x5, 0x9, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x3; immval:0x13
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x3, 0x13, x1, 124, x2)
inst_32:
// rs1_val == -2,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2; immval:0x17
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27, rs1_val == 32
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x20, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0xffffe000, -0x80000000, 0x12, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000000; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2000, 0x40000000, 0x11, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000000; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x4, 0x20000000, 0x1b, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x80, 0x10000000, 0x15, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000000; immval:0x12
TEST_CI_OP( c.srai, x10, 0x200, 0x8000000, 0x12, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000000; immval:0x15
TEST_CI_OP( c.srai, x10, 0x20, 0x4000000, 0x15, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x200000, 0x2000000, 0x4, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x1000000, 0x1e, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800000; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x800000, 0x1e, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x200, 0x400000, 0xd, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200000; immval:0xd
TEST_CI_OP( c.srai, x10, 0x100, 0x200000, 0xd, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x2, 0x100000, 0x13, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80000; immval:0x9
TEST_CI_OP( c.srai, x10, 0x400, 0x80000, 0x9, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000; immval:0x4
TEST_CI_OP( c.srai, x10, 0x2000, 0x20000, 0x4, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srai, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x400, 0x8000, 0x5, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x4000, 0x17, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000; immval:0x5
TEST_CI_OP( c.srai, x10, 0x100, 0x2000, 0x5, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srai, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x800; immval:0xa
TEST_CI_OP( c.srai, x10, 0x2, 0x800, 0xa, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x400; immval:0x1e
TEST_CI_OP( c.srai, x10, 0x0, 0x400, 0x1e, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x200; immval:0xb
TEST_CI_OP( c.srai, x10, 0x0, 0x200, 0xb, x1, 224, x2)
inst_57:
// rs1_val == 256,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x100; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x100, 0x1f, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x80; immval:0x3
TEST_CI_OP( c.srai, x10, 0x10, 0x80, 0x3, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x40; immval:0x1b
TEST_CI_OP( c.srai, x10, 0x0, 0x40, 0x1b, x1, 236, x2)
inst_60:
// rs1_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x10; immval:0x6
TEST_CI_OP( c.srai, x10, 0x0, 0x10, 0x6, x1, 240, x2)
inst_61:
// rs1_val == 8,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x8; immval:0x11
TEST_CI_OP( c.srai, x10, 0x0, 0x8, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 4, rs1_val==4
// opcode:c.srai; op1:x10; dest:x10 op1val:0x4; immval:0x13
TEST_CI_OP( c.srai, x10, 0x0, 0x4, 0x13, x1, 248, x2)
inst_63:
// rs1_val == 2, rs1_val==2
// opcode:c.srai; op1:x10; dest:x10 op1val:0x2; immval:0x4
TEST_CI_OP( c.srai, x10, 0x0, 0x2, 0x4, x1, 252, x2)
inst_64:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x1; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0x1, 0x1f, x1, 256, x2)
inst_65:
// imm_val == 16,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x10
TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x10, x1, 260, x2)
inst_66:
// imm_val == 1, rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555555; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2aaaaaaa, 0x55555555, 0x1, x1, 264, x2)
inst_67:
// rs1_val==46341,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb505; immval:0xd
TEST_CI_OP( c.srai, x10, 0x5, 0xb505, 0xd, x1, 268, x2)
inst_68:
// rs1_val==-46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb503; immval:0x5
TEST_CI_OP( c.srai, x10, 0xfffffa57, -0xb503, 0x5, x1, 272, x2)
inst_69:
// rs1_val==1717986919,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666667; immval:0x15
TEST_CI_OP( c.srai, x10, 0x333, 0x66666667, 0x15, x1, 276, x2)
inst_70:
// rs1_val==858993460,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333334; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333334, 0x17, x1, 280, x2)
inst_71:
// rs1_val==6,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x6; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x6, 0x3, x1, 284, x2)
inst_72:
// rs1_val==3, rs1_val == imm_val and imm_val != 0 and imm_val < xlen
// opcode:c.srai; op1:x10; dest:x10 op1val:0x3; immval:0x3
TEST_CI_OP( c.srai, x10, 0x0, 0x3, 0x3, x1, 288, x2)
inst_73:
// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
// opcode:c.srai; op1:x10; dest:x10 op1val:0x0; immval:0x12
TEST_CI_OP( c.srai, x10, 0x0, 0x0, 0x12, x1, 292, x2)
inst_74:
// rs1_val==-1431655765,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555555; immval:0x6
TEST_CI_OP( c.srai, x10, 0xfeaaaaaa, -0x55555555, 0x6, x1, 296, x2)
inst_75:
// rs1_val==1431655766,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555556; immval:0x11
TEST_CI_OP( c.srai, x10, 0x2aaa, 0x55555556, 0x11, x1, 300, x2)
inst_76:
// rs1_val==46339,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb503; immval:0xe
TEST_CI_OP( c.srai, x10, 0x2, 0xb503, 0xe, x1, 304, x2)
inst_77:
// rs1_val==1717986917,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
TEST_CI_OP( c.srai, x10, 0x3333333, 0x66666665, 0x5, x1, 308, x2)
inst_78:
// rs1_val==858993458,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333332; immval:0x8
TEST_CI_OP( c.srai, x10, 0x333333, 0x33333332, 0x8, x1, 312, x2)
inst_79:
// rs1_val==1431655764,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555554; immval:0x8
TEST_CI_OP( c.srai, x10, 0x555555, 0x55555554, 0x8, x1, 316, x2)
inst_80:
// rs1_val==46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:0xb504; immval:0x1f
TEST_CI_OP( c.srai, x10, 0x0, 0xb504, 0x1f, x1, 320, x2)
inst_81:
// rs1_val==-46340,
// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb504; immval:0x8
TEST_CI_OP( c.srai, x10, 0xffffff4a, -0xb504, 0x8, x1, 324, x2)
inst_82:
// rs1_val==1717986918,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666666; immval:0xd
TEST_CI_OP( c.srai, x10, 0x33333, 0x66666666, 0xd, x1, 328, x2)
inst_83:
// rs1_val==858993459,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333333; immval:0x17
TEST_CI_OP( c.srai, x10, 0x66, 0x33333333, 0x17, x1, 332, x2)
inst_84:
// rs1_val==5,
// opcode:c.srai; op1:x10; dest:x10 op1val:0x5; immval:0x1
TEST_CI_OP( c.srai, x10, 0x2, 0x5, 0x1, x1, 336, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 85*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

505
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S Normal file
View file

@ -0,0 +1,505 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.srli instruction of the RISC-V C extension for the csrli covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrli)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1==x15, rs1_val < 0 and imm_val < xlen, rs1_val == -2
// opcode:c.srli; op1:x15; dest:x15 op1val:-0x2; immval:0xe
TEST_CI_OP( c.srli, x15, 0x3ffff, -0x2, 0xe, x1, 0, x2)
inst_1:
// rs1==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0x7
TEST_CI_OP( c.srli, x8, 0xffffff, 0x7fffffff, 0x7, x1, 4, x2)
inst_2:
// rs1==x11, rs1_val == -1073741825, imm_val == 15
// opcode:c.srli; op1:x11; dest:x11 op1val:-0x40000001; immval:0xf
TEST_CI_OP( c.srli, x11, 0x17fff, -0x40000001, 0xf, x1, 8, x2)
inst_3:
// rs1==x10, rs1_val == -536870913,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20000001; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1bffff, -0x20000001, 0xb, x1, 12, x2)
inst_4:
// rs1==x9, rs1_val == -268435457,
// opcode:c.srli; op1:x9; dest:x9 op1val:-0x10000001; immval:0xc
TEST_CI_OP( c.srli, x9, 0xeffff, -0x10000001, 0xc, x1, 16, x2)
inst_5:
// rs1==x13, rs1_val == -134217729, imm_val == 4
// opcode:c.srli; op1:x13; dest:x13 op1val:-0x8000001; immval:0x4
TEST_CI_OP( c.srli, x13, 0xf7fffff, -0x8000001, 0x4, x1, 20, x2)
inst_6:
// rs1==x12, rs1_val == -67108865,
// opcode:c.srli; op1:x12; dest:x12 op1val:-0x4000001; immval:0x3
TEST_CI_OP( c.srli, x12, 0x1f7fffff, -0x4000001, 0x3, x1, 24, x2)
inst_7:
// rs1==x14, rs1_val == -33554433,
// opcode:c.srli; op1:x14; dest:x14 op1val:-0x2000001; immval:0x11
TEST_CI_OP( c.srli, x14, 0x7eff, -0x2000001, 0x11, x1, 28, x2)
inst_8:
// rs1_val == -16777217,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3fbffff, -0x1000001, 0x6, x1, 32, x2)
inst_9:
// rs1_val == -8388609,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x800001; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1feff, -0x800001, 0xf, x1, 36, x2)
inst_10:
// rs1_val == -4194305, imm_val == 21
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x400001; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7fd, -0x400001, 0x15, x1, 40, x2)
inst_11:
// rs1_val == -2097153,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x200001; immval:0x3
TEST_CI_OP( c.srli, x10, 0x1ffbffff, -0x200001, 0x3, x1, 44, x2)
inst_12:
// rs1_val == -1048577, imm_val == 2
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x100001; immval:0x2
TEST_CI_OP( c.srli, x10, 0x3ffbffff, -0x100001, 0x2, x1, 48, x2)
inst_13:
// rs1_val == -524289, imm_val == 16
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfff7, -0x80001, 0x10, x1, 52, x2)
inst_14:
// rs1_val == -262145,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x40001; immval:0x6
TEST_CI_OP( c.srli, x10, 0x3ffefff, -0x40001, 0x6, x1, 56, x2)
inst_15:
// rs1_val == -131073,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20001; immval:0x10
TEST_CI_OP( c.srli, x10, 0xfffd, -0x20001, 0x10, x1, 60, x2)
inst_16:
// rs1_val == -65537,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x10001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fff7f, -0x10001, 0x9, x1, 64, x2)
inst_17:
// rs1_val == -32769,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x8001; immval:0x9
TEST_CI_OP( c.srli, x10, 0x7fffbf, -0x8001, 0x9, x1, 68, x2)
inst_18:
// rs1_val == -16385,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x4001; immval:0xc
TEST_CI_OP( c.srli, x10, 0xffffb, -0x4001, 0xc, x1, 72, x2)
inst_19:
// rs1_val == -8193,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x2001; immval:0xe
TEST_CI_OP( c.srli, x10, 0x3ffff, -0x2001, 0xe, x1, 76, x2)
inst_20:
// rs1_val == -4097,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1001; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7ffff7f, -0x1001, 0x5, x1, 80, x2)
inst_21:
// rs1_val == -2049,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x801; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0x801, 0x15, x1, 84, x2)
inst_22:
// rs1_val == -1025, imm_val == 29
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x401; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x401, 0x1d, x1, 88, x2)
inst_23:
// rs1_val == -513,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x201; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x201, 0xc, x1, 92, x2)
inst_24:
// rs1_val == -257,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x101; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x101, 0xc, x1, 96, x2)
inst_25:
// rs1_val == -129,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1fffffe, -0x81, 0x7, x1, 100, x2)
inst_26:
// rs1_val == -65,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x41; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x7, -0x41, 0x1d, x1, 104, x2)
inst_27:
// rs1_val == -33,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x21; immval:0xf
TEST_CI_OP( c.srli, x10, 0x1ffff, -0x21, 0xf, x1, 108, x2)
inst_28:
// rs1_val == -17,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x11; immval:0xc
TEST_CI_OP( c.srli, x10, 0xfffff, -0x11, 0xc, x1, 112, x2)
inst_29:
// rs1_val == -9,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x9; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1ffffff, -0x9, 0x7, x1, 116, x2)
inst_30:
// rs1_val == -5, imm_val == 30
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x5; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x3, -0x5, 0x1e, x1, 120, x2)
inst_31:
// rs1_val == -3,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x3; immval:0xb
TEST_CI_OP( c.srli, x10, 0x1fffff, -0x3, 0xb, x1, 124, x2)
inst_32:
// imm_val == 23, rs1_val==5
// opcode:c.srli; op1:x10; dest:x10 op1val:0x5; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x5, 0x17, x1, 128, x2)
inst_33:
// imm_val == 27,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x1f, -0x81, 0x1b, x1, 132, x2)
inst_34:
// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x400000, -0x80000000, 0x9, x1, 136, x2)
inst_35:
// rs1_val == 1073741824,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000000; immval:0x7
TEST_CI_OP( c.srli, x10, 0x800000, 0x40000000, 0x7, x1, 140, x2)
inst_36:
// rs1_val == 536870912,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000000; immval:0x6
TEST_CI_OP( c.srli, x10, 0x800000, 0x20000000, 0x6, x1, 144, x2)
inst_37:
// rs1_val == 268435456,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000000; immval:0x9
TEST_CI_OP( c.srli, x10, 0x80000, 0x10000000, 0x9, x1, 148, x2)
inst_38:
// rs1_val == 134217728,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000000; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x8000000, 0x1e, x1, 152, x2)
inst_39:
// rs1_val == 67108864,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000000; immval:0x11
TEST_CI_OP( c.srli, x10, 0x200, 0x4000000, 0x11, x1, 156, x2)
inst_40:
// rs1_val == 33554432,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000000; immval:0x15
TEST_CI_OP( c.srli, x10, 0x10, 0x2000000, 0x15, x1, 160, x2)
inst_41:
// rs1_val == 16777216,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000000; immval:0x10
TEST_CI_OP( c.srli, x10, 0x100, 0x1000000, 0x10, x1, 164, x2)
inst_42:
// rs1_val == 8388608,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x800000, 0x1d, x1, 168, x2)
inst_43:
// rs1_val == 4194304,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x400, 0x400000, 0xc, x1, 172, x2)
inst_44:
// rs1_val == 2097152,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200000; immval:0xc
TEST_CI_OP( c.srli, x10, 0x200, 0x200000, 0xc, x1, 176, x2)
inst_45:
// rs1_val == 1048576,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x100000, 0x17, x1, 180, x2)
inst_46:
// rs1_val == 524288,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x80000, 0x1f, x1, 184, x2)
inst_47:
// rs1_val == 262144,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000; immval:0x13
TEST_CI_OP( c.srli, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
inst_48:
// rs1_val == 131072,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x20000, 0x1f, x1, 192, x2)
inst_49:
// rs1_val == 65536, imm_val == 8
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000; immval:0x8
TEST_CI_OP( c.srli, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
inst_50:
// rs1_val == 32768,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x8000, 0x1d, x1, 200, x2)
inst_51:
// rs1_val == 16384,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000; immval:0x3
TEST_CI_OP( c.srli, x10, 0x800, 0x4000, 0x3, x1, 204, x2)
inst_52:
// rs1_val == 8192,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x2000, 0x1d, x1, 208, x2)
inst_53:
// rs1_val == 4096,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000; immval:0x17
TEST_CI_OP( c.srli, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
inst_54:
// rs1_val == 2048,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x800; immval:0x7
TEST_CI_OP( c.srli, x10, 0x10, 0x800, 0x7, x1, 216, x2)
inst_55:
// rs1_val == 1024,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x400; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x400, 0x10, x1, 220, x2)
inst_56:
// rs1_val == 512,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x200; immval:0x1d
TEST_CI_OP( c.srli, x10, 0x0, 0x200, 0x1d, x1, 224, x2)
inst_57:
// rs1_val == 256, imm_val == 1
// opcode:c.srli; op1:x10; dest:x10 op1val:0x100; immval:0x1
TEST_CI_OP( c.srli, x10, 0x80, 0x100, 0x1, x1, 228, x2)
inst_58:
// rs1_val == 128,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x80; immval:0x7
TEST_CI_OP( c.srli, x10, 0x1, 0x80, 0x7, x1, 232, x2)
inst_59:
// rs1_val == 64,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x40; immval:0xd
TEST_CI_OP( c.srli, x10, 0x0, 0x40, 0xd, x1, 236, x2)
inst_60:
// rs1_val == 32,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x20; immval:0x1e
TEST_CI_OP( c.srli, x10, 0x0, 0x20, 0x1e, x1, 240, x2)
inst_61:
// rs1_val == 16,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x10; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x10, 0x11, x1, 244, x2)
inst_62:
// rs1_val == 8,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x8; immval:0x1b
TEST_CI_OP( c.srli, x10, 0x0, 0x8, 0x1b, x1, 248, x2)
inst_63:
// rs1_val == 4, rs1_val==4
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x11, x1, 252, x2)
inst_64:
// rs1_val == 2, rs1_val==2
// opcode:c.srli; op1:x10; dest:x10 op1val:0x2; immval:0x15
TEST_CI_OP( c.srli, x10, 0x0, 0x2, 0x15, x1, 256, x2)
inst_65:
// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x1; immval:0x12
TEST_CI_OP( c.srli, x10, 0x0, 0x1, 0x12, x1, 260, x2)
inst_66:
// rs1_val==46341,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb505; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0xb505, 0x10, x1, 264, x2)
inst_67:
// rs1_val==-46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb503; immval:0x15
TEST_CI_OP( c.srli, x10, 0x7ff, -0xb503, 0x15, x1, 268, x2)
inst_68:
// rs1_val==1717986919,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666667; immval:0x9
TEST_CI_OP( c.srli, x10, 0x333333, 0x66666667, 0x9, x1, 272, x2)
inst_69:
// rs1_val==858993460,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333334; immval:0xf
TEST_CI_OP( c.srli, x10, 0x6666, 0x33333334, 0xf, x1, 276, x2)
inst_70:
// rs1_val==6,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x6; immval:0x10
TEST_CI_OP( c.srli, x10, 0x0, 0x6, 0x10, x1, 280, x2)
inst_71:
// rs1_val==-1431655765,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x5
TEST_CI_OP( c.srli, x10, 0x5555555, -0x55555555, 0x5, x1, 284, x2)
inst_72:
// rs1_val==1431655766,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555556; immval:0xf
TEST_CI_OP( c.srli, x10, 0xaaaa, 0x55555556, 0xf, x1, 288, x2)
inst_73:
// rs1_val==46339,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb503; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2d40, 0xb503, 0x2, x1, 292, x2)
inst_74:
// rs1_val==0, rs1_val == 0 and imm_val != 0 and imm_val < xlen
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xf
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xf, x1, 296, x2)
inst_75:
// rs1_val==3,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x3; immval:0x6
TEST_CI_OP( c.srli, x10, 0x0, 0x3, 0x6, x1, 300, x2)
inst_76:
// rs1_val == -1431655766, rs1_val==-1431655766
// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x2
TEST_CI_OP( c.srli, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 304, x2)
inst_77:
// rs1_val == 1431655765, rs1_val==1431655765
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555555; immval:0xb
TEST_CI_OP( c.srli, x10, 0xaaaaa, 0x55555555, 0xb, x1, 308, x2)
inst_78:
// imm_val == 10,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xa
TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xa, x1, 312, x2)
inst_79:
// rs1_val == imm_val and imm_val != 0 and imm_val < xlen,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x4
TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x4, x1, 316, x2)
inst_80:
// rs1_val==1717986917,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666665; immval:0xe
TEST_CI_OP( c.srli, x10, 0x19999, 0x66666665, 0xe, x1, 320, x2)
inst_81:
// rs1_val==858993458,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333332; immval:0x6
TEST_CI_OP( c.srli, x10, 0xcccccc, 0x33333332, 0x6, x1, 324, x2)
inst_82:
// rs1_val==1431655764,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555554; immval:0x3
TEST_CI_OP( c.srli, x10, 0xaaaaaaa, 0x55555554, 0x3, x1, 328, x2)
inst_83:
// rs1_val==46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:0xb504; immval:0x11
TEST_CI_OP( c.srli, x10, 0x0, 0xb504, 0x11, x1, 332, x2)
inst_84:
// rs1_val==-46340,
// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb504; immval:0x5
TEST_CI_OP( c.srli, x10, 0x7fffa57, -0xb504, 0x5, x1, 336, x2)
inst_85:
// rs1_val==1717986918,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666666; immval:0x3
TEST_CI_OP( c.srli, x10, 0xccccccc, 0x66666666, 0x3, x1, 340, x2)
inst_86:
// rs1_val==858993459,
// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1f
TEST_CI_OP( c.srli, x10, 0x0, 0x33333333, 0x1f, x1, 344, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 87*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S Normal file
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@ -0,0 +1,410 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Wed Aug 4 06:39:00 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.sw instruction of the RISC-V C extension for the csw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// rs1 != rs2, rs1==x15, rs2==x14, imm_val == 0, rs2_val == -16385
// opcode:c.sw; op1:x15; op2:x14; op2val:-0x4001; immval:0x0
TEST_STORE(x1,x2,0,x15,x14,-0x4001,0x0,0,c.sw,0)
inst_1:
// rs1==x11, rs2==x10, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), imm_val > 0
// opcode:c.sw; op1:x11; op2:x10; op2val:0x7fffffff; immval:0x14
TEST_STORE(x1,x2,0,x11,x10,0x7fffffff,0x14,4,c.sw,0)
inst_2:
// rs1==x13, rs2==x8, rs2_val == -1073741825,
// opcode:c.sw; op1:x13; op2:x8; op2val:-0x40000001; immval:0x14
TEST_STORE(x1,x2,0,x13,x8,-0x40000001,0x14,8,c.sw,0)
inst_3:
// rs1==x9, rs2==x13, rs2_val == -536870913,
// opcode:c.sw; op1:x9; op2:x13; op2val:-0x20000001; immval:0x24
TEST_STORE(x1,x2,0,x9,x13,-0x20000001,0x24,12,c.sw,0)
inst_4:
// rs1==x10, rs2==x12, rs2_val == -268435457, imm_val == 32
// opcode:c.sw; op1:x10; op2:x12; op2val:-0x10000001; immval:0x20
TEST_STORE(x1,x2,0,x10,x12,-0x10000001,0x20,16,c.sw,0)
inst_5:
// rs1==x14, rs2==x15, rs2_val == -134217729,
// opcode:c.sw; op1:x14; op2:x15; op2val:-0x8000001; immval:0x4c
TEST_STORE(x1,x2,0,x14,x15,-0x8000001,0x4c,20,c.sw,0)
inst_6:
// rs1==x8, rs2==x9, rs2_val == -67108865,
// opcode:c.sw; op1:x8; op2:x9; op2val:-0x4000001; immval:0x48
TEST_STORE(x1,x2,0,x8,x9,-0x4000001,0x48,24,c.sw,0)
inst_7:
// rs1==x12, rs2==x11, rs2_val == -33554433, imm_val == 84
// opcode:c.sw; op1:x12; op2:x11; op2val:-0x2000001; immval:0x54
TEST_STORE(x1,x2,0,x12,x11,-0x2000001,0x54,28,c.sw,0)
inst_8:
// rs2_val == -16777217,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1000001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x1000001,0x7c,32,c.sw,0)
inst_9:
// rs2_val == -8388609, imm_val == 4
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x800001; immval:0x4
TEST_STORE(x1,x2,0,x10,x11,-0x800001,0x4,36,c.sw,0)
inst_10:
// rs2_val == -4194305, imm_val == 60
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x400001; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x400001,0x3c,40,c.sw,0)
inst_11:
// rs2_val == -2097153,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x200001; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x30,44,c.sw,0)
inst_12:
// rs2_val == -1048577,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x7c,48,c.sw,0)
inst_13:
// rs2_val == -524289,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80001; immval:0x18
TEST_STORE(x1,x2,0,x10,x11,-0x80001,0x18,52,c.sw,0)
inst_14:
// rs2_val == -262145, imm_val == 40
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x40001; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x40001,0x28,56,c.sw,0)
inst_15:
// rs2_val == -131073,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x20001; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x20001,0x7c,60,c.sw,0)
inst_16:
// rs2_val == -65537,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x10001; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x10001,0x14,64,c.sw,0)
inst_17:
// rs2_val == -32769, imm_val == 64
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x8001; immval:0x40
TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x40,68,c.sw,0)
inst_18:
// rs2_val == -8193,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x0,72,c.sw,0)
inst_19:
// rs2_val == -4097,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x48
TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x48,76,c.sw,0)
inst_20:
// rs2_val == -2049,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x801; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x801,0x24,80,c.sw,0)
inst_21:
// rs2_val == -1025,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x401; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x401,0x28,84,c.sw,0)
inst_22:
// rs2_val == -513, imm_val == 120
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x201; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,-0x201,0x78,88,c.sw,0)
inst_23:
// rs2_val == -257,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x101; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,-0x101,0x24,92,c.sw,0)
inst_24:
// rs2_val == -129,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x81; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,-0x81,0x4c,96,c.sw,0)
inst_25:
// rs2_val == -65,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x41; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,-0x41,0x14,100,c.sw,0)
inst_26:
// rs2_val == -33,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x21; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x21,0x28,104,c.sw,0)
inst_27:
// rs2_val == -17,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x11; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,-0x11,0x34,108,c.sw,0)
inst_28:
// rs2_val == -9,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x9; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,-0x9,0x28,112,c.sw,0)
inst_29:
// rs2_val == -5,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x5; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,-0x5,0xc,116,c.sw,0)
inst_30:
// rs2_val == -3, imm_val == 108
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x3; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,-0x3,0x6c,120,c.sw,0)
inst_31:
// rs2_val == -2, imm_val == 92
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,-0x2,0x5c,124,c.sw,0)
inst_32:
// imm_val == 116, rs2_val == 32768
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000; immval:0x74
TEST_STORE(x1,x2,0,x10,x11,0x8000,0x74,128,c.sw,0)
inst_33:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,-0x80000000,0x7c,132,c.sw,0)
inst_34:
// rs2_val == 1073741824,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x40000000,0x38,136,c.sw,0)
inst_35:
// rs2_val == 536870912,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x20000000,0x7c,140,c.sw,0)
inst_36:
// rs2_val == 268435456,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000000; immval:0x1c
TEST_STORE(x1,x2,0,x10,x11,0x10000000,0x1c,144,c.sw,0)
inst_37:
// rs2_val == 134217728,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x5c,148,c.sw,0)
inst_38:
// rs2_val == 32,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20; immval:0x2c
TEST_STORE(x1,x2,0,x10,x11,0x20,0x2c,152,c.sw,0)
inst_39:
// rs2_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10; immval:0x30
TEST_STORE(x1,x2,0,x10,x11,0x10,0x30,156,c.sw,0)
inst_40:
// rs2_val == 8,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x8; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x8,0x24,160,c.sw,0)
inst_41:
// rs2_val == 4,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x4,0x7c,164,c.sw,0)
inst_42:
// rs2_val == 2,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x2,0x34,168,c.sw,0)
inst_43:
// rs2_val == 1,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1; immval:0x54
TEST_STORE(x1,x2,0,x10,x11,0x1,0x54,172,c.sw,0)
inst_44:
// imm_val == 16,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x10,176,c.sw,0)
inst_45:
// imm_val == 8, rs2_val == 524288
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80000; immval:0x8
TEST_STORE(x1,x2,0,x10,x11,0x80000,0x8,180,c.sw,0)
inst_46:
// rs2_val == -1431655766,
// opcode:c.sw; op1:x10; op2:x11; op2val:-0x55555556; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,-0x55555556,0x3c,184,c.sw,0)
inst_47:
// rs2_val == 1431655765,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x10,188,c.sw,0)
inst_48:
// rs2_val == 0,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x0; immval:0x38
TEST_STORE(x1,x2,0,x10,x11,0x0,0x38,192,c.sw,0)
inst_49:
// rs2_val == 67108864,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000000; immval:0xc
TEST_STORE(x1,x2,0,x10,x11,0x4000000,0xc,196,c.sw,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x2000000,0x3c,200,c.sw,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x1000000,0x20,204,c.sw,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800000; immval:0x10
TEST_STORE(x1,x2,0,x10,x11,0x800000,0x10,208,c.sw,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400000; immval:0x0
TEST_STORE(x1,x2,0,x10,x11,0x400000,0x0,212,c.sw,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200000; immval:0x24
TEST_STORE(x1,x2,0,x10,x11,0x200000,0x24,216,c.sw,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100000; immval:0x34
TEST_STORE(x1,x2,0,x10,x11,0x100000,0x34,220,c.sw,0)
inst_56:
// rs2_val == 262144,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000; immval:0x14
TEST_STORE(x1,x2,0,x10,x11,0x40000,0x14,224,c.sw,0)
inst_57:
// rs2_val == 131072,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x20000,0x20,228,c.sw,0)
inst_58:
// rs2_val == 65536,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000; immval:0x44
TEST_STORE(x1,x2,0,x10,x11,0x10000,0x44,232,c.sw,0)
inst_59:
// rs2_val == 16384,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000; immval:0x20
TEST_STORE(x1,x2,0,x10,x11,0x4000,0x20,236,c.sw,0)
inst_60:
// rs2_val == 8192,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x2000,0x78,240,c.sw,0)
inst_61:
// rs2_val == 4096,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7c
TEST_STORE(x1,x2,0,x10,x11,0x1000,0x7c,244,c.sw,0)
inst_62:
// rs2_val == 2048,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x800; immval:0x6c
TEST_STORE(x1,x2,0,x10,x11,0x800,0x6c,248,c.sw,0)
inst_63:
// rs2_val == 1024,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x400; immval:0x4c
TEST_STORE(x1,x2,0,x10,x11,0x400,0x4c,252,c.sw,0)
inst_64:
// rs2_val == 512,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x200; immval:0x5c
TEST_STORE(x1,x2,0,x10,x11,0x200,0x5c,256,c.sw,0)
inst_65:
// rs2_val == 256,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x100; immval:0x28
TEST_STORE(x1,x2,0,x10,x11,0x100,0x28,260,c.sw,0)
inst_66:
// rs2_val == 128,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x80; immval:0x78
TEST_STORE(x1,x2,0,x10,x11,0x80,0x78,264,c.sw,0)
inst_67:
// rs2_val == 64,
// opcode:c.sw; op1:x10; op2:x11; op2val:0x40; immval:0x3c
TEST_STORE(x1,x2,0,x10,x11,0x40,0x3c,268,c.sw,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 68*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

425
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S Normal file
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@ -0,0 +1,425 @@
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.5.1
// timestamp : Mon Sep 13 07:01:20 2021 GMT
// usage : riscv_ctg \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32ec.cgf \
// --base-isa rv32e \
// --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.swsp instruction of the RISC-V C extension for the cswsp covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cswsp)
RVTEST_SIGBASE( x8,signature_x8_1)
inst_0:
// rs2==x12, imm_val == 0,
// opcode:c.swsp; op1:x2; op2:x12; op2val:0x3; immval:0x0
TEST_STORE(x8,x9,0,x2,x12,0x3,0x0,0,c.swsp,0)
inst_1:
// rs2==x1, rs2_val == 2147483647, imm_val > 0, rs2_val == (2**(xlen-1)-1), imm_val == 236
// opcode:c.swsp; op1:x2; op2:x1; op2val:0x7fffffff; immval:0xec
TEST_STORE(x8,x9,0,x2,x1,0x7fffffff,0xec,4,c.swsp,0)
inst_2:
// rs2==x7, rs2_val == -1073741825,
// opcode:c.swsp; op1:x2; op2:x7; op2val:-0x40000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x7,-0x40000001,0x48,8,c.swsp,0)
inst_3:
// rs2==x13, rs2_val == -536870913,
// opcode:c.swsp; op1:x2; op2:x13; op2val:-0x20000001; immval:0x48
TEST_STORE(x8,x9,0,x2,x13,-0x20000001,0x48,12,c.swsp,0)
inst_4:
// rs2==x2, rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x2; op2val:-0x10000001; immval:0x8
TEST_STORE(x8,x9,0,x2,x2,-0x10000001,0x8,16,c.swsp,0)
inst_5:
// rs2==x4, rs2_val == -134217729,
// opcode:c.swsp; op1:x2; op2:x4; op2val:-0x8000001; immval:0x28
TEST_STORE(x8,x9,0,x2,x4,-0x8000001,0x28,20,c.swsp,0)
inst_6:
// rs2==x10, rs2_val == -67108865,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4000001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x10,-0x4000001,0x4c,24,c.swsp,0)
inst_7:
// rs2==x15, rs2_val == -33554433,
// opcode:c.swsp; op1:x2; op2:x15; op2val:-0x2000001; immval:0x18
TEST_STORE(x8,x9,0,x2,x15,-0x2000001,0x18,28,c.swsp,0)
inst_8:
// rs2==x5, rs2_val == -16777217, imm_val == 244
// opcode:c.swsp; op1:x2; op2:x5; op2val:-0x1000001; immval:0xf4
TEST_STORE(x8,x9,0,x2,x5,-0x1000001,0xf4,32,c.swsp,0)
inst_9:
// rs2==x3, rs2_val == -8388609,
// opcode:c.swsp; op1:x2; op2:x3; op2val:-0x800001; immval:0x4c
TEST_STORE(x8,x9,0,x2,x3,-0x800001,0x4c,36,c.swsp,0)
inst_10:
// rs2==x6, rs2_val == -4194305,
// opcode:c.swsp; op1:x2; op2:x6; op2val:-0x400001; immval:0x30
TEST_STORE(x8,x9,0,x2,x6,-0x400001,0x30,40,c.swsp,0)
inst_11:
// rs2==x9, rs2_val == -2097153, imm_val == 128
// opcode:c.swsp; op1:x2; op2:x9; op2val:-0x200001; immval:0x80
TEST_STORE(x8,x3,0,x2,x9,-0x200001,0x80,44,c.swsp,0)
RVTEST_SIGBASE( x1,signature_x1_0)
inst_12:
// rs2==x11, rs2_val == -1048577, imm_val == 124
// opcode:c.swsp; op1:x2; op2:x11; op2val:-0x100001; immval:0x7c
TEST_STORE(x1,x3,0,x2,x11,-0x100001,0x7c,0,c.swsp,0)
inst_13:
// rs2==x14, rs2_val == -524289,
// opcode:c.swsp; op1:x2; op2:x14; op2val:-0x80001; immval:0x34
TEST_STORE(x1,x3,0,x2,x14,-0x80001,0x34,4,c.swsp,0)
inst_14:
// rs2==x8, rs2_val == -262145, imm_val == 168
// opcode:c.swsp; op1:x2; op2:x8; op2val:-0x40001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x8,-0x40001,0xa8,8,c.swsp,0)
inst_15:
// rs2_val == -131073,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x20001; immval:0xf4
TEST_STORE(x1,x3,0,x2,x10,-0x20001,0xf4,12,c.swsp,0)
inst_16:
// rs2_val == -65537,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10001; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x10001,0x3c,16,c.swsp,0)
inst_17:
// rs2_val == -32769,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0x1c,20,c.swsp,0)
inst_18:
// rs2_val == -16385, imm_val == 4
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4001; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,-0x4001,0x4,24,c.swsp,0)
inst_19:
// rs2_val == -8193,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2001; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,-0x2001,0xa8,28,c.swsp,0)
inst_20:
// rs2_val == -4097, imm_val == 248
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x1001; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x1001,0xf8,32,c.swsp,0)
inst_21:
// rs2_val == -2049, imm_val == 64
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x801; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,-0x801,0x40,36,c.swsp,0)
inst_22:
// rs2_val == -1025,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x401; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,-0x401,0xc,40,c.swsp,0)
inst_23:
// rs2_val == -513,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x201; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,-0x201,0x38,44,c.swsp,0)
inst_24:
// rs2_val == -257, imm_val == 220
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x101; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x101,0xdc,48,c.swsp,0)
inst_25:
// rs2_val == -129, imm_val == 32
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x81; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x81,0x20,52,c.swsp,0)
inst_26:
// rs2_val == -65,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x41; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,-0x41,0x34,56,c.swsp,0)
inst_27:
// rs2_val == -33,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x21; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,-0x21,0xf8,60,c.swsp,0)
inst_28:
// rs2_val == -17,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x11; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,-0x11,0x4c,64,c.swsp,0)
inst_29:
// rs2_val == -9,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x9; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,-0x9,0x30,68,c.swsp,0)
inst_30:
// rs2_val == -5,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x5; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,-0x5,0x3c,72,c.swsp,0)
inst_31:
// rs2_val == -3,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x3; immval:0x80
TEST_STORE(x1,x3,0,x2,x10,-0x3,0x80,76,c.swsp,0)
inst_32:
// rs2_val == -2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2; immval:0x24
TEST_STORE(x1,x3,0,x2,x10,-0x2,0x24,80,c.swsp,0)
inst_33:
// imm_val == 188,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,-0x8001,0xbc,84,c.swsp,0)
inst_34:
// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x80000000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,-0x80000000,0x20,88,c.swsp,0)
inst_35:
// rs2_val == 1073741824,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000000; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x40000000,0x38,92,c.swsp,0)
inst_36:
// rs2_val == 536870912,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x20000000,0x7c,96,c.swsp,0)
inst_37:
// rs2_val == 268435456,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000000; immval:0xfc
TEST_STORE(x1,x3,0,x2,x10,0x10000000,0xfc,100,c.swsp,0)
inst_38:
// rs2_val == 134217728,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000000; immval:0x48
TEST_STORE(x1,x3,0,x2,x10,0x8000000,0x48,104,c.swsp,0)
inst_39:
// rs2_val == 67108864, imm_val == 84
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x4000000,0x54,108,c.swsp,0)
inst_40:
// rs2_val == 64, imm_val == 16
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x40,0x10,112,c.swsp,0)
inst_41:
// rs2_val == 32,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20; immval:0x14
TEST_STORE(x1,x3,0,x2,x10,0x20,0x14,116,c.swsp,0)
inst_42:
// rs2_val == 16,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x10,0x4c,120,c.swsp,0)
inst_43:
// rs2_val == 8,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x8,0x4c,124,c.swsp,0)
inst_44:
// rs2_val == 4,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x4,0xf8,128,c.swsp,0)
inst_45:
// rs2_val == 2,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2; immval:0x2c
TEST_STORE(x1,x3,0,x2,x10,0x2,0x2c,132,c.swsp,0)
inst_46:
// rs2_val == 1,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1; immval:0xbc
TEST_STORE(x1,x3,0,x2,x10,0x1,0xbc,136,c.swsp,0)
inst_47:
// rs2_val == -1431655766,
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x55555556; immval:0xdc
TEST_STORE(x1,x3,0,x2,x10,-0x55555556,0xdc,140,c.swsp,0)
inst_48:
// rs2_val == 1431655765,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x55555555; immval:0x4c
TEST_STORE(x1,x3,0,x2,x10,0x55555555,0x4c,144,c.swsp,0)
inst_49:
// rs2_val == 0,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x0; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x0,0x40,148,c.swsp,0)
inst_50:
// rs2_val == 33554432,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000000,0x4,152,c.swsp,0)
inst_51:
// rs2_val == 16777216,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000000; immval:0x7c
TEST_STORE(x1,x3,0,x2,x10,0x1000000,0x7c,156,c.swsp,0)
inst_52:
// rs2_val == 8388608,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800000; immval:0x18
TEST_STORE(x1,x3,0,x2,x10,0x800000,0x18,160,c.swsp,0)
inst_53:
// rs2_val == 4194304,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400000; immval:0x40
TEST_STORE(x1,x3,0,x2,x10,0x400000,0x40,164,c.swsp,0)
inst_54:
// rs2_val == 2097152,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200000; immval:0x54
TEST_STORE(x1,x3,0,x2,x10,0x200000,0x54,168,c.swsp,0)
inst_55:
// rs2_val == 1048576,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x100000,0x34,172,c.swsp,0)
inst_56:
// rs2_val == 524288,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80000; immval:0x20
TEST_STORE(x1,x3,0,x2,x10,0x80000,0x20,176,c.swsp,0)
inst_57:
// rs2_val == 262144,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000; immval:0x44
TEST_STORE(x1,x3,0,x2,x10,0x40000,0x44,180,c.swsp,0)
inst_58:
// rs2_val == 131072,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000; immval:0xa8
TEST_STORE(x1,x3,0,x2,x10,0x20000,0xa8,184,c.swsp,0)
inst_59:
// rs2_val == 65536,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x10000,0x3c,188,c.swsp,0)
inst_60:
// rs2_val == 32768,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000; immval:0x34
TEST_STORE(x1,x3,0,x2,x10,0x8000,0x34,192,c.swsp,0)
inst_61:
// rs2_val == 16384,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000; immval:0xc
TEST_STORE(x1,x3,0,x2,x10,0x4000,0xc,196,c.swsp,0)
inst_62:
// rs2_val == 8192,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000; immval:0x4
TEST_STORE(x1,x3,0,x2,x10,0x2000,0x4,200,c.swsp,0)
inst_63:
// rs2_val == 4096,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000; immval:0x30
TEST_STORE(x1,x3,0,x2,x10,0x1000,0x30,204,c.swsp,0)
inst_64:
// rs2_val == 2048,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800; immval:0x38
TEST_STORE(x1,x3,0,x2,x10,0x800,0x38,208,c.swsp,0)
inst_65:
// rs2_val == 1024,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400; immval:0x10
TEST_STORE(x1,x3,0,x2,x10,0x400,0x10,212,c.swsp,0)
inst_66:
// rs2_val == 512,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200; immval:0x3c
TEST_STORE(x1,x3,0,x2,x10,0x200,0x3c,216,c.swsp,0)
inst_67:
// rs2_val == 256,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100; immval:0x1c
TEST_STORE(x1,x3,0,x2,x10,0x100,0x1c,220,c.swsp,0)
inst_68:
// rs2_val == 128,
// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80; immval:0xf8
TEST_STORE(x1,x3,0,x2,x10,0x80,0xf8,224,c.swsp,0)
inst_69:
// rs2_val == -268435457, imm_val == 8
// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10000001; immval:0x8
TEST_STORE(x1,x3,0,x2,x10,-0x10000001,0x8,228,c.swsp,0)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
signature_x8_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x8_1:
.fill 12*(XLEN/32),4,0xdeadbeef
signature_x1_0:
.fill 58*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

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3
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile Normal file
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include ../../Makefile.include
$(eval $(call compile_template,-march=rv32e -mabi=ilp32e -DXLEN=$(XLEN)))

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# RISC-V Architecture Test RV32E Makefrag
#
# Copyright (c) 2017, Codasip Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Codasip Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Description: Makefrag for RV32E architectural tests
rv32e_sc_tests = \
add-01 \
addi-01 \
and-01 \
andi-01 \
auipc-01 \
beq-01 \
bge-01 \
bgeu-01 \
blt-01 \
bltu-01 \
bne-01 \
jal-01 \
jalr-01 \
lb-align-01 \
lbu-align-01 \
lh-align-01 \
lhu-align-01 \
lui-01 \
lw-align-01 \
or-01 \
ori-01 \
sb-align-01 \
sh-align-01 \
sll-01 \
slli-01 \
slt-01 \
slti-01 \
sltiu-01 \
sltu-01 \
sra-01 \
srai-01 \
srl-01 \
srli-01 \
sub-01 \
sw-align-01 \
xor-01 \
xori-01
rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests))
target_tests += $(rv32e_tests)

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561
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586
tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output Normal file
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@ -0,0 +1,586 @@
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