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Adjusted synthesis scripts to report on DESIGN even when a wrapper is used

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This commit is contained in:
David Harris 2023-10-19 06:16:52 -07:00
parent 4873b9c0a8
commit 7c1606264a
3 changed files with 13 additions and 5 deletions
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1
.gitignore vendored
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@ -82,6 +82,7 @@ synthDC/ppa/plots
synthDC/wallyplots/
synthDC/runArchive
synthDC/hdl
synthDC/wrappers
sim/power.saif
tests/fp/vectors/*.tv
synthDC/Summary.csv

15
synthDC/scripts/synth.tcl
View file

@ -53,6 +53,7 @@ if { $wrapper == 1 } {
} else {
set my_toplevel $::env(DESIGN)
}
set my_design $::env(DESIGN)
# Set number of significant digits
set report_default_significant_digits 6
@ -238,6 +239,12 @@ set write_rep 1 ;# generates estimated area and timing report
set write_cst 1 ;# generate report of constraints
set write_hier 1 ;# generate hierarchy report
# Report on DESIGN, not wrapper. However, design has a suffix for the parameters.
if { $wrapper == 1 } {
set designname [format "%s%s" $my_design "__*"]
current_design $designname
}
# Report Constraint Violators
set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
redirect $filename {report_constraint -all_violators}
@ -246,16 +253,16 @@ redirect $filename {report_constraint -all_violators}
redirect $outputDir/reports/check_design.rpt { check_design }
# Report Final Netlist (Hierarchical)
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sv"]
write_file -f verilog -hierarchy -output $filename
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdc"]
write_sdc $filename
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"]
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".ddc"]
write_file -format ddc -hierarchy -o $filename
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
write_sdf $filename
# QoR

2
synthDC/wallySynth.py
View file

@ -7,7 +7,7 @@ import argparse
def runSynth(config, mod, tech, freq, maxopt, usesram):
global pool
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1 WRAPPER=1".format(config, mod, tech, freq, maxopt, usesram)
pool.map(mask, [command])
def mask(command):