mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 22:07:12 -04:00
More cleanup.
This commit is contained in:
parent
0d008c9281
commit
83dc9cd926
2 changed files with 7 additions and 4 deletions
|
@ -60,8 +60,8 @@ if {$2 eq "buildroot"} {
|
|||
# vsim -fprofile+perf
|
||||
# visualizer -fprofile+perf+dir=fprofile
|
||||
#
|
||||
eval vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
|
||||
-G INSTR_LIMIT=1000000 -G TEST=$2 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
|
||||
eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
|
||||
-G TEST=$2 -o testbenchopt
|
||||
eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \
|
||||
-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
|
||||
$env(OTHERFLAGS)
|
||||
|
@ -73,9 +73,9 @@ if {$2 eq "buildroot"} {
|
|||
#run 100 ns
|
||||
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
run 9800 ms
|
||||
add log -recursive /testbench/dut/*
|
||||
do wave.do
|
||||
run 9800 ms
|
||||
run 200 ms
|
||||
#run -all
|
||||
|
||||
|
|
|
@ -655,6 +655,9 @@ end
|
|||
void'(rvviRefCsrSetVolatile(0, 32'h104)); // SIE - Temporary!!!!
|
||||
|
||||
// Load memory
|
||||
// *** RT: This section can probably be moved into the same chunk of code which
|
||||
// loads the memories. However I'm not sure that ImperasDV supports reloading
|
||||
// the memories without relaunching the simulator.
|
||||
begin
|
||||
longint x64;
|
||||
int x32[2];
|
||||
|
@ -696,7 +699,7 @@ end
|
|||
|
||||
$display("RVVI Loading Complete");
|
||||
|
||||
void'(rvviRefPcSet(0, 'h1000)); // set BOOTROM address
|
||||
void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
|
||||
end
|
||||
end
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue