github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-22 12:57:23 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Don't delete hdl directory at end of run

Browse source
This commit is contained in:
David Harris 2022-07-17 01:39:57 +00:00
parent e3ed40620c
commit 9514abf0e0
3 changed files with 9 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
synthDC/Makefile
View file

@ -107,7 +107,7 @@ ifeq ($(SAIFPOWER), 1)
cp -f ../pipelined/regression/power.saif .
endif
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
rm -rf $(OUTPUTDIR)/hdl
# rm -rf $(OUTPUTDIR)/hdl
rm -rf $(OUTPUTDIR)/WORK
rm -rf $(OUTPUTDIR)/alib-52

7
synthDC/extractSummary.py
View file

@ -78,6 +78,13 @@ def freqPlot(tech, width, config):
''' plots delay, area for syntheses with specified tech, module, width
'''
current_directory = os.getcwd()
final_directory = os.path.join(current_directory, 'plots/wally')
# if not os.path.exists(final_directory):
# os.makedirs(final_directory)
# os.chdir(final_directory)
freqsL, delaysL, areasL = ([[], []] for i in range(3))
for oneSynth in allSynths:
if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special):

2
synthDC/scripts/synth.tcl
View file

@ -56,7 +56,7 @@ set vhdlout_show_unconnected_pins "true"
# Due to parameterized Verilog must use analyze/elaborate and not
# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
#
set alib_library_analysis_path ./$outputDir
#set alib_library_analysis_path ./$outputDir
define_design_lib WORK -path ./$outputDir/WORK
analyze -f sverilog -lib WORK $my_verilog_files
elaborate $my_toplevel -lib WORK