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100% coverage tlbcontrol

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This commit is contained in:
David Harris 2025-04-18 19:15:07 -07:00
parent ae2846b1ec
commit 9a46061716
2 changed files with 11 additions and 1 deletions
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2
src/mmu/tlb/tlb.sv
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@ -117,7 +117,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .Matches, .TLBHit, .WriteEnables);
tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS)
tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs,
tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs,
.SATP_ASID, .Matches, .HitPageType, .CAMHit);
tlbram #(P, TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs, .PTE_NAPOTs);

10
tests/coverage/tlbmisc.S
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@ -156,6 +156,16 @@ ConcurrentICacheMissDTLBMiss:
#sd zero, 0(t0)
#amoadd.w t1, t0, (t0)
# Access page with R=0 W = 1
li t0, 0x80804000
li t1, 0x8067 # ret
sw t1, 0(t0) # have something to return from
jalr ra, t0
# Good PBMT with menvcfg.PBMT = 1,
li t0, 0x80806000
jalr ra, t0
# Good PBMT with menvcfg.PBMTE = 0
li a0, 3
ecall # switch to machine mode