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Cleaned up HPTW reset

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David Harris 2025-04-17 11:22:17 -07:00
parent ed93cca5f4
commit ae2846b1ec
1 changed files with 5 additions and 6 deletions
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11
src/mmu/hptw.sv
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@ -86,7 +86,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic [1:0] NextPageType;
logic [P.SVMODE_BITS-1:0] SvMode;
logic [P.XLEN-1:0] TranslationVAdr;
logic [P.XLEN-1:0] NextPTE;
logic [P.XLEN-1:0] NextPTE, NextPTE2;
logic UpdatePTE;
logic HPTWUpdateDA;
logic [P.PA_BITS-1:0] HPTWReadAdr;
@ -107,8 +107,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic DAUFaultM;
logic PBMTOrDAUFaultM;
logic HPTWFaultM;
logic ResetPTE;
// map hptw access faults onto either the original LSU load/store fault or instruction access fault
assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
assign PBMTOrDAUFaultM = PBMTFaultM | DAUFaultM;
@ -146,8 +145,9 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// State flops
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE;
flopenr #(P.XLEN) PTEReg(clk, ResetPTE, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE | (NextWalkerState == IDLE);
assign NextPTE2 = (NextWalkerState == IDLE) ? '0 : NextPTE;
flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE2, PTE); // Capture page table entry from data cache
// Assign PTE descriptors common across all XLEN values
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
@ -310,7 +310,6 @@ module hptw import cvw::*; #(parameter cvw_t P) (
assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM);
assign ResetPTE = reset | (NextWalkerState == IDLE);
assign SelHPTW = WalkerState != IDLE;
assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA);