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Initial trickbox

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This commit is contained in:
David Harris 2025-05-21 10:26:32 -07:00
commit 9dc82f38fc
69 changed files with 978 additions and 3366 deletions
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6
testbench/common/loggers.sv
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@ -3,6 +3,7 @@
//
// Written: Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
// Modified by sanarayanan@hmc.edu, May 2025
//
// Purpose: Log branch instructions, log instruction fetches,
// log I$ misses, log data memory accesses, log D$ misses, and
@ -40,6 +41,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
// input logic StartSample,
// input logic EndSample,
input string memfilename,
input string sim_log_prefix,
input string TEST
);
@ -180,7 +182,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
initial begin
LogFile = "ICache.log";
LogFile = {sim_log_prefix, "ICache.log"}; // Prepend the directory
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end
@ -234,7 +236,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
(AccessTypeString != "NULL");
initial begin
LogFile = "DCache.log";
LogFile = {sim_log_prefix, "DCache.log"}; // Prepend the directory
file = $fopen(LogFile, "w");
$fwrite(file, "BEGIN %s\n", memfilename);
end

10
testbench/testbench.sv
View file

@ -2,6 +2,7 @@
// testbench.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
//// Modified by sanarayanan@hmc.edu, May 2025
// Modified:
//
// Purpose: Wally Testbench and helper modules
@ -85,7 +86,7 @@ module testbench;
logic ResetMem;
// Variables that can be overwritten with $value$plusargs at start of simulation
string TEST, ElfFile;
string TEST, ElfFile, sim_log_prefix;
integer INSTR_LIMIT;
// DUT signals
@ -141,6 +142,10 @@ module testbench;
ElfFile = "none";
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
INSTR_LIMIT = 0;
// Check if sim_log_prefix is passed as a command-line argument
if (!$value$plusargs("sim_log_prefix=%s", sim_log_prefix)) begin
sim_log_prefix = ""; // Assign default value if not passed
end
//$display("TEST = %s ElfFile = %s", TEST, ElfFile);
// pick tests based on modes supported
@ -290,6 +295,7 @@ module testbench;
integer begin_signature_addr, end_signature_addr, signature_size;
integer uartoutfile;
assign ResetThreshold = 3'd5;
initial begin
@ -688,7 +694,7 @@ module testbench;
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, sim_log_prefix, TEST);
// track the current function or global label
if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : functionName

5
testbench/tests.vh
View file

@ -259,9 +259,7 @@ string arch64priv[] = '{
"rv64i_m/privilege/src/misalign-blt-01.S",
"rv64i_m/privilege/src/misalign-bltu-01.S",
"rv64i_m/privilege/src/misalign-bne-01.S",
"rv64i_m/privilege/src/misalign-jal-01.S"
// commented out for now because rv64gc supports Zicclsm, but Sail does not yet. Restore when Sail supports Zicclsm.
/* -----\/----- EXCLUDED -----\/-----
"rv64i_m/privilege/src/misalign-jal-01.S",
"rv64i_m/privilege/src/misalign-ld-01.S",
"rv64i_m/privilege/src/misalign-lh-01.S",
"rv64i_m/privilege/src/misalign-lhu-01.S",
@ -270,7 +268,6 @@ string arch64priv[] = '{
"rv64i_m/privilege/src/misalign-sd-01.S",
"rv64i_m/privilege/src/misalign-sh-01.S",
"rv64i_m/privilege/src/misalign-sw-01.S"
-----/\----- EXCLUDED -----/\----- */
};
string arch64zifencei[] = '{