mirror of
https://github.com/openhwgroup/cvw.git
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Initial trickbox
This commit is contained in:
David Harris
commit
9dc82f38fc
69 changed files with 978 additions and 3366 deletions
155
tests/coverage/WALLY-init-lib-misalignedSpill.h
Normal file
155
tests/coverage/WALLY-init-lib-misalignedSpill.h
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@ -0,0 +1,155 @@
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///////////////////////////////////////////
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// WALLY-init-lib.h
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//
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// Written: David_Harris@hmc.edu 21 March 2023
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//
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// Purpose: Initialize stack, handle interrupts, terminate test case
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// The PMP tests are sensitive to the exact addresses in this code, so unfortunately
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// modifying anything breaks those tests.
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.section .text.init
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.global rvtest_entry_point
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rvtest_entry_point:
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la sp, topofstack # Initialize stack pointer (not used)
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# Set up interrupts
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la t0, trap_handler
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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csrw mideleg, zero # Don't delegate interrupts
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csrw medeleg, zero # Don't delegate exceptions
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# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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# li t1, 0x02004000 # MTIMECMP in CLINT
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# sd t0, 0(t1)
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li t0, 0x80
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# li t0, 0x00
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csrw mie, t0 # Enable machine timer interrupt
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la t0, topoftrapstack
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csrw mscratch, t0 # MSCRATCH holds trap stack pointer
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csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
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# set up PMP so user and supervisor mode can access full address space
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csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
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li t0, 0xFFFFFFFF
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csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
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j main # Call main function in user test program
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done:
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li a0, 4 # argument to finish program
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ecall # system call to finish program
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j self_loop # wait forever (not taken)
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.align 4 # trap handlers must be aligned to multiple of 4
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trap_handler:
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# Load trap handler stack pointer tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t1, -8(tp)
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csrr t0, mcause # Check the cause
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csrr t1, mtval # And the trap value
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bgez t0, exception # if msb is clear, it is an exception
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interrupt: # must be a timer interrupt
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLIN
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sd t0, 0(t1)
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csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
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li t0, 32
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csrc sip, t0 # clears stimer interrupt
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j trap_return # clean up and return
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exception:
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csrr t0, mcause
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li t1, 0xC # is it an instruction page fault
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li a0, 3 # set a0 to 3 to ecall looks like a program terminate
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beq t0, t1, ecall # terminate program for instruction page fault
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li t1, 8 # is it an ecall trap?
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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bne t0, t1, trap_return # ignore other exceptions
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ecall:
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li t0, 4
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beq a0, t0, write_tohost # call 4: terminate program
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bltu a0, t0, changeprivilege # calls 0-3: change privilege level
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j trap_return # ignore other ecalls
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changeprivilege:
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li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12
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csrc mstatus, t0
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andi a0, a0, 0x003 # only keep bottom two bits of argument
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slli a0, a0, 11 # move into mstatus.MPP position
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csrs mstatus, a0 # set mstatus.MPP with desired privilege
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trap_return: # return from trap handler
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csrr t0, mepc # get address of instruction that caused exception
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li t1, 0x20000
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csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped
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lh t0, 0(t0) # get instruction that caused exception
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csrc mstatus, t1 # clear mprv bit to restore normal operation
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li t1, 3
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and t0, t0, t1 # mask off upper bits
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beq t0, t1, instr32 # if lower 2 bits are 11, instruction is uncompresssed
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li t0, 2 # increment PC by 2 for compressed instruction
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j updateepc
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instr32:
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li t0, 4
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updateepc:
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csrr t1, mepc # add 2 or 4 (from t0) to MEPC to determine return Address
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add t1, t1, t0
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csrw mepc, t1
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ld t1, -8(tp) # restore t1 and t0
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ld t0, 0(tp)
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csrrw tp, mscratch, tp # restore tp
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mret # return from trap
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write_tohost:
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la t1, tohost
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li t0, 1 # 1 for success, 3 for failure
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sd t0, 0(t1) # send success code
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self_loop:
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j self_loop # wait
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.section .tohost
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tohost: # write to HTIF
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.dword 0
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fromhost:
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.dword 0
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.EQU XLEN,64
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begin_signature:
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.fill 6*(XLEN/32),4,0xdeadbeef #
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end_signature:
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# Initialize stack with room for 512 bytes
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.bss
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.space 512
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topofstack:
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# And another stack for the trap handler
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.bss
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.space 512
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topoftrapstack:
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.align 4
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.section .text.main
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@ -214,6 +214,9 @@ TestData2:
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.int 0xbf800000 #FP -1.0
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.int 0x7fa00000 #SNaN
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.int 0x3fffffff #OverFlow Test
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# workaround for binutils 2.44 bug with displaying 6 byte instructions (https://sourceware.org/pipermail/binutils/2025-February/139413.html)
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.word 0x0000
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.align 3
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TestData3:
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.dword 0xABCD543212345678 # NaN box test
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DivTestData:
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@ -26,7 +26,7 @@
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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#include "WALLY-init-lib-misalignedSpill.h"
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# run-elf.bash find this in project description
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main:
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@ -18,7 +18,7 @@ current_dir := $(shell pwd)
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.PHONY: all riscv-arch-test wally-riscv-arch-test clean
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all: riscv-arch-test wally-riscv-arch-test
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riscv-arch-test: arch32e arch32 arch64
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cvw-riscv-arch-test: cvw-arch32e cvw-arch32 cvw-arch64
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cvw-riscv-arch-test: cvw-arch32 cvw-arch64 # cvw-arch32e
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wally-riscv-arch-test: wally32 wally64
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# Generate config.ini files
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@ -34,9 +34,10 @@ arch%: config$$*.ini | $(work_dir) $(arch_workdir)
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# Generate cvw-riscv-arch-test targets
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# Generate riscv-arch-test targets
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cvw-arch%: config$$*.ini | $(work_dir) $(cvw_arch_workdir)
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riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(cvw_arch_dir)/riscv-test-suite/ --env=$(cvw_arch_dir)/riscv-test-suite/env --no-browser
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export COLLECT_COVERAGE=true; riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(cvw_arch_dir)/riscv-test-suite/ --env=$(cvw_arch_dir)/riscv-test-suite/env --no-browser
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$(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*)
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rsync -a $(work_dir)/$@/rv*/* $(cvw_arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*)) || echo "error suppressed"
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${CVW_ARCH_VERIF}/bin/trace-coverreport.py $(cvw_arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))
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# Generate wally-riscv-arch-test targets
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wally%: config$$*.ini | $(work_dir) $(wally_workdir)
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@ -25,6 +25,7 @@ class sail_cSim(pluginTemplate):
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'64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_rv64d")}
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self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
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self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
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# self.coverage_file = os.path.abspath(config['coverage']) if 'coverage' in config else ''
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self.make = config['make'] if 'make' in config else 'make'
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logger.debug("SAIL CSim plugin initialised using the following configuration.")
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for entry in config:
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@ -45,7 +46,6 @@ class sail_cSim(pluginTemplate):
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ispec = utils.load_yaml(isa_yaml)['hart0']
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self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
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self.isa = 'rv' + self.xlen
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self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
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self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
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if "I" in ispec["ISA"]:
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self.isa += 'i'
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@ -61,8 +61,6 @@ class sail_cSim(pluginTemplate):
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self.isa += 'f'
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if "D" in ispec["ISA"]:
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self.isa += 'd'
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if "Zcb" in ispec["ISA"]: # for some strange reason, Sail requires a command line argument to enable Zcb
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self.sailargs += "--enable-zcb"
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if "Q" in ispec["ISA"]:
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self.isa += 'q'
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objdump = "riscv64-unknown-elf-objdump"
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@ -86,6 +84,13 @@ class sail_cSim(pluginTemplate):
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os.remove(self.work_dir+ "/Makefile." + self.name[:-1])
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make = utils.makeUtil(makefilePath=os.path.join(self.work_dir, "Makefile." + self.name[:-1]))
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make.makeCommand = self.make + ' -j' + self.num_jobs
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# TODO: This bit is temporary until riscof properly copies over the coverage file
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self.coverage_file = f"{self.pluginpath}/../spike/coverage_rv{self.xlen}gc.svh"
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# Copy coverage file to wkdir
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cov_copy_command = f'cp {self.coverage_file} {self.work_dir}/coverage.svh;'
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os.system(cov_copy_command)
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for file in testList:
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testentry = testList[file]
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test = testentry['test_path']
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@ -109,24 +114,19 @@ class sail_cSim(pluginTemplate):
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reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
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execute += f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
|
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else:
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execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + f' --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
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execute += self.sail_exe[self.xlen] + f' --config {self.pluginpath}/rv{self.xlen}gc.json --trace=step --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
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cov_str = ' '
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for label in testentry['coverage_labels']:
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cov_str+=' -l '+label
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# Coverage
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if (os.environ.get('COLLECT_COVERAGE') == "true"): # TODO: update this to take a proper flag from riscof, not use env vars
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# Generate trace from sail log
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cvw_arch_verif_dir = os.getenv('CVW_ARCH_VERIF') # TODO: update this to not depend on env var
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trace_command = f'{cvw_arch_verif_dir}/bin/sail-parse.py {test_name}.log {test_name}.trace;'
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execute += trace_command
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if cgf_file is not None:
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coverage_cmd = 'riscv_isac --verbose info coverage -d \
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-t {}.log --parser-name c_sail -o coverage.rpt \
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--sig-label begin_signature end_signature \
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--test-label rvtest_code_begin rvtest_code_end \
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-e ref.elf -c {} -x{} {};'.format(\
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test_name, ' -c '.join(cgf_file), self.xlen, cov_str)
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else:
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coverage_cmd = ''
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execute+=coverage_cmd
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# Generate ucdb coverage file
|
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questa_do_file = f'{cvw_arch_verif_dir}/bin/cvw-arch-verif.do'
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coverage_command = f'vsim -c -do "do {questa_do_file} {test_dir} {test_name} {cvw_arch_verif_dir}/fcov {self.work_dir}";'
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execute += coverage_command
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make.add_target(execute)
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# make.execute_all(self.work_dir)
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|
|
|
|||
221
tests/riscof/sail_cSim/rv32gc.json
Normal file
221
tests/riscof/sail_cSim/rv32gc.json
Normal file
|
|
@ -0,0 +1,221 @@
|
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{
|
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"base": {
|
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"writable_misa": false,
|
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"writable_fiom": true,
|
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"writable_hpm_counters": {
|
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"len": 32,
|
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"value": "0xFFFF_FFFF"
|
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},
|
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"mtval_has_illegal_instruction_bits": true
|
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},
|
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"memory": {
|
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"pmp": {
|
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"grain": 0,
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"count": 16
|
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},
|
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"misaligned": {
|
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"supported": false,
|
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"byte_by_byte": false,
|
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"order_decreasing": false,
|
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"allowed_within_exp": 0
|
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},
|
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"translation": {
|
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"dirty_update": false
|
||||
}
|
||||
},
|
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"platform": {
|
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"vendorid": 1538,
|
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"archid": 36,
|
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"impid": 256,
|
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"hartid": 0,
|
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"reset_vector": 4096,
|
||||
"cache_block_size_exp": 6,
|
||||
"ram": {
|
||||
"base": 2147483648,
|
||||
"size": 2147483648
|
||||
},
|
||||
"rom": {
|
||||
"base": 4096,
|
||||
"size": 4096
|
||||
},
|
||||
"clint": {
|
||||
"base": 33554432,
|
||||
"size": 786432
|
||||
},
|
||||
"instructions_per_tick": 2,
|
||||
"wfi_is_nop": true
|
||||
},
|
||||
"extensions": {
|
||||
"M": {
|
||||
"supported": true
|
||||
},
|
||||
"A": {
|
||||
"supported": true
|
||||
},
|
||||
"FD": {
|
||||
"supported": true
|
||||
},
|
||||
"V": {
|
||||
"supported": false,
|
||||
"vlen_exp": 9,
|
||||
"elen_exp": 6,
|
||||
"vl_use_ceil": false
|
||||
},
|
||||
"B": {
|
||||
"supported": true
|
||||
},
|
||||
"S": {
|
||||
"supported": true
|
||||
},
|
||||
"U": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicbom": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicboz": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicond": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicntr": {
|
||||
"supported": true
|
||||
},
|
||||
"Zifencei": {
|
||||
"supported": true
|
||||
},
|
||||
"Zihpm": {
|
||||
"supported": true
|
||||
},
|
||||
"Zimop": {
|
||||
"supported": false
|
||||
},
|
||||
"Zmmul": {
|
||||
"supported": false
|
||||
},
|
||||
"Zaamo": {
|
||||
"supported": false
|
||||
},
|
||||
"Zabha": {
|
||||
"supported": false
|
||||
},
|
||||
"Zalrsc": {
|
||||
"supported": false
|
||||
},
|
||||
"Zfa": {
|
||||
"supported": true
|
||||
},
|
||||
"Zfh": {
|
||||
"supported": true
|
||||
},
|
||||
"Zfhmin": {
|
||||
"supported": false
|
||||
},
|
||||
"Zfinx": {
|
||||
"supported": false
|
||||
},
|
||||
"Zca": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcf": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcd": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcb": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcmop": {
|
||||
"supported": false
|
||||
},
|
||||
"Zba": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbs": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbc": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkb": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkc": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkx": {
|
||||
"supported": true
|
||||
},
|
||||
"Zknd": {
|
||||
"supported": true
|
||||
},
|
||||
"Zkne": {
|
||||
"supported": true
|
||||
},
|
||||
"Zknh": {
|
||||
"supported": true
|
||||
},
|
||||
"Zkr": {
|
||||
"supported": false
|
||||
},
|
||||
"Zksed": {
|
||||
"supported": false
|
||||
},
|
||||
"Zksh": {
|
||||
"supported": false
|
||||
},
|
||||
"Zhinx": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvbb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvkb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvbc": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvknha": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvknhb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvksh": {
|
||||
"supported": false
|
||||
},
|
||||
"Sscofpmf": {
|
||||
"supported": false
|
||||
},
|
||||
"Smcntrpmf": {
|
||||
"supported": false
|
||||
},
|
||||
"Sstc": {
|
||||
"supported": true
|
||||
},
|
||||
"Svinval": {
|
||||
"supported": true
|
||||
},
|
||||
"Svbare": {
|
||||
"supported": true
|
||||
},
|
||||
"Sv32": {
|
||||
"supported": true
|
||||
},
|
||||
"Sv39": {
|
||||
"supported": false
|
||||
},
|
||||
"Sv48": {
|
||||
"supported": false
|
||||
},
|
||||
"Sv57": {
|
||||
"supported": false
|
||||
}
|
||||
}
|
||||
}
|
||||
221
tests/riscof/sail_cSim/rv64gc.json
Normal file
221
tests/riscof/sail_cSim/rv64gc.json
Normal file
|
|
@ -0,0 +1,221 @@
|
|||
{
|
||||
"base": {
|
||||
"writable_misa": false,
|
||||
"writable_fiom": true,
|
||||
"writable_hpm_counters": {
|
||||
"len": 32,
|
||||
"value": "0xFFFF_FFFF"
|
||||
},
|
||||
"mtval_has_illegal_instruction_bits": true
|
||||
},
|
||||
"memory": {
|
||||
"pmp": {
|
||||
"grain": 0,
|
||||
"count": 16
|
||||
},
|
||||
"misaligned": {
|
||||
"supported": true,
|
||||
"byte_by_byte": false,
|
||||
"order_decreasing": false,
|
||||
"allowed_within_exp": 0
|
||||
},
|
||||
"translation": {
|
||||
"dirty_update": false
|
||||
}
|
||||
},
|
||||
"platform": {
|
||||
"vendorid": 1538,
|
||||
"archid": 36,
|
||||
"impid": 256,
|
||||
"hartid": 0,
|
||||
"reset_vector": 4096,
|
||||
"cache_block_size_exp": 6,
|
||||
"ram": {
|
||||
"base": 2147483648,
|
||||
"size": 2147483648
|
||||
},
|
||||
"rom": {
|
||||
"base": 4096,
|
||||
"size": 4096
|
||||
},
|
||||
"clint": {
|
||||
"base": 33554432,
|
||||
"size": 786432
|
||||
},
|
||||
"instructions_per_tick": 2,
|
||||
"wfi_is_nop": true
|
||||
},
|
||||
"extensions": {
|
||||
"M": {
|
||||
"supported": true
|
||||
},
|
||||
"A": {
|
||||
"supported": true
|
||||
},
|
||||
"FD": {
|
||||
"supported": true
|
||||
},
|
||||
"V": {
|
||||
"supported": false,
|
||||
"vlen_exp": 9,
|
||||
"elen_exp": 6,
|
||||
"vl_use_ceil": false
|
||||
},
|
||||
"B": {
|
||||
"supported": true
|
||||
},
|
||||
"S": {
|
||||
"supported": true
|
||||
},
|
||||
"U": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicbom": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicboz": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicond": {
|
||||
"supported": true
|
||||
},
|
||||
"Zicntr": {
|
||||
"supported": true
|
||||
},
|
||||
"Zifencei": {
|
||||
"supported": true
|
||||
},
|
||||
"Zihpm": {
|
||||
"supported": true
|
||||
},
|
||||
"Zimop": {
|
||||
"supported": false
|
||||
},
|
||||
"Zmmul": {
|
||||
"supported": false
|
||||
},
|
||||
"Zaamo": {
|
||||
"supported": false
|
||||
},
|
||||
"Zabha": {
|
||||
"supported": false
|
||||
},
|
||||
"Zalrsc": {
|
||||
"supported": false
|
||||
},
|
||||
"Zfa": {
|
||||
"supported": true
|
||||
},
|
||||
"Zfh": {
|
||||
"supported": true
|
||||
},
|
||||
"Zfhmin": {
|
||||
"supported": false
|
||||
},
|
||||
"Zfinx": {
|
||||
"supported": false
|
||||
},
|
||||
"Zca": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcf": {
|
||||
"supported": false
|
||||
},
|
||||
"Zcd": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcb": {
|
||||
"supported": true
|
||||
},
|
||||
"Zcmop": {
|
||||
"supported": false
|
||||
},
|
||||
"Zba": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbs": {
|
||||
"supported": false
|
||||
},
|
||||
"Zbc": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkb": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkc": {
|
||||
"supported": true
|
||||
},
|
||||
"Zbkx": {
|
||||
"supported": true
|
||||
},
|
||||
"Zknd": {
|
||||
"supported": true
|
||||
},
|
||||
"Zkne": {
|
||||
"supported": true
|
||||
},
|
||||
"Zknh": {
|
||||
"supported": true
|
||||
},
|
||||
"Zkr": {
|
||||
"supported": false
|
||||
},
|
||||
"Zksed": {
|
||||
"supported": false
|
||||
},
|
||||
"Zksh": {
|
||||
"supported": false
|
||||
},
|
||||
"Zhinx": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvbb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvkb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvbc": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvknha": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvknhb": {
|
||||
"supported": false
|
||||
},
|
||||
"Zvksh": {
|
||||
"supported": false
|
||||
},
|
||||
"Sscofpmf": {
|
||||
"supported": false
|
||||
},
|
||||
"Smcntrpmf": {
|
||||
"supported": false
|
||||
},
|
||||
"Sstc": {
|
||||
"supported": true
|
||||
},
|
||||
"Svinval": {
|
||||
"supported": true
|
||||
},
|
||||
"Svbare": {
|
||||
"supported": true
|
||||
},
|
||||
"Sv32": {
|
||||
"supported": false
|
||||
},
|
||||
"Sv39": {
|
||||
"supported": true
|
||||
},
|
||||
"Sv48": {
|
||||
"supported": true
|
||||
},
|
||||
"Sv57": {
|
||||
"supported": false
|
||||
}
|
||||
}
|
||||
}
|
||||
1
tests/riscof/spike/coverage_rv32gc.svh
Symbolic link
1
tests/riscof/spike/coverage_rv32gc.svh
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
../../../config/rv32gc/coverage.svh
|
||||
1
tests/riscof/spike/coverage_rv64gc.svh
Symbolic link
1
tests/riscof/spike/coverage_rv64gc.svh
Symbolic link
|
|
@ -0,0 +1 @@
|
|||
../../../config/rv64gc/coverage.svh
|
||||
|
|
@ -196,7 +196,7 @@ class spike(pluginTemplate):
|
|||
reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
|
||||
simcmd = f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
|
||||
else:
|
||||
simcmd = self.dut_exe + f' --isa={self.isa} +signature={sig_file} +signature-granularity=4 {elf}'
|
||||
simcmd = self.dut_exe + f' {"--misaligned" if self.xlen == "64" else ""} --isa={self.isa} +signature={sig_file} +signature-granularity=4 {elf}'
|
||||
else:
|
||||
simcmd = 'echo "NO RUN"'
|
||||
|
||||
|
|
|
|||
|
|
@ -1,29 +1,33 @@
|
|||
hart_ids: [0]
|
||||
hart0:
|
||||
ISA: RV32EMCZicsr_Zifencei_Zbkc
|
||||
ISA: RV32EMCZicsr_Zifencei
|
||||
physical_addr_sz: 32
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [32]
|
||||
misa:
|
||||
reset-val: 0x40001014
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- mxl[1:0] in [0x1]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x0001034, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
|
||||
reset-val: 0x40001014
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- mxl[1:0] in [0x1]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x0001034, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
PMP:
|
||||
implemented: False
|
||||
pmp-grain: 0
|
||||
pmp-count: 0
|
||||
pmp-writable: 0
|
||||
|
|
|
|||
|
|
@ -1,29 +1,33 @@
|
|||
hart_ids: [0]
|
||||
hart0:
|
||||
# ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
|
||||
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
|
||||
physical_addr_sz: 32
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [32]
|
||||
misa:
|
||||
reset-val: 0x4014112D
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- mxl[1:0] in [0x1]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x014112D, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
reset-val: 0x4014112D
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- mxl[1:0] in [0x1]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x014112D, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
PMP:
|
||||
implemented: True
|
||||
pmp-grain: 0
|
||||
pmp-count: 16
|
||||
pmp-writable: 12
|
||||
|
|
|
|||
|
|
@ -1,34 +1,35 @@
|
|||
hart_ids: [0]
|
||||
hart0:
|
||||
# ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
|
||||
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
|
||||
# ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
|
||||
physical_addr_sz: 56
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [64]
|
||||
misa:
|
||||
reset-val: 0x800000000014112D
|
||||
# reset-val: 0x800000000015112D
|
||||
rv32:
|
||||
reset-val: 0x800000000014112D
|
||||
rv32:
|
||||
accessible: false
|
||||
rv64:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
rv64:
|
||||
accessible: true
|
||||
mxl:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- mxl[1:0] in [0x2]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x015112D, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
|
||||
extensions:
|
||||
implemented: true
|
||||
type:
|
||||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x015112D, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
PMP:
|
||||
implemented: True
|
||||
pmp-grain: 0
|
||||
pmp-count: 16
|
||||
pmp-writable: 12
|
||||
|
|
|
|||
|
|
@ -1,188 +0,0 @@
|
|||
deadbeef # begin_signature
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000000 # destination 1
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000 # destination 2
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies.
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
0bad0bad
|
||||
0bad0bad
|
||||
|
|
@ -1,410 +0,0 @@
|
|||
0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
|
||||
00000002 # S mode write to mstatush with illegal instruction
|
||||
00000002 # S mode read from mstatush with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to menvcfgh with illegal instruction
|
||||
00000002 # S mode read from menvcfgh with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mseccfgh with illegal instruction
|
||||
00000002 # S mode read from mseccfgh with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpcfg1 with illegal instruction
|
||||
00000002 # S mode read from pmpcfg1 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpcfg3 with illegal instruction
|
||||
00000002 # S mode read from pmpcfg3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mcycleh with illegal instruction
|
||||
00000002 # S mode read from mcycleh with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to minstreth with illegal instruction
|
||||
00000002 # S mode read from minstreth with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter3h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter3h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter4h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter4h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter5h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter5h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter6h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter6h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter7h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter7h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter8h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter8h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter9h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter9h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter10h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter10h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter11h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter11h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter12h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter12h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter13h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter13h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter14h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter14h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter15h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter15h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter16h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter16h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter17h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter17h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter18h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter18h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter19h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter19h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter20h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter20h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter21h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter21h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter22h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter22h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter23h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter23h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter24h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter24h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter25h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter25h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter26h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter26h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter27h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter27h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter28h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter28h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter29h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter29h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter30h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter30h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter31h with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter31h with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mvendorid with illegal instruction
|
||||
00000002 # S mode read from mvendorid with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to marchid with illegal instruction
|
||||
00000002 # S mode read from marchid with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mimpid with illegal instruction
|
||||
00000002 # S mode read from mimpid with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhartid with illegal instruction
|
||||
00000002 # S mode read from mhartid with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mconfigptr with illegal instruction
|
||||
00000002 # S mode read from mconfigptr with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mstatus with illegal instruction
|
||||
00000002 # S mode read from mstatus with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mstatush with illegal instruction
|
||||
00000002 # S mode read from mstatush with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to misa with illegal instruction
|
||||
00000002 # S mode read from misa with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to medeleg with illegal instruction
|
||||
00000002 # S mode read from medeleg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mideleg with illegal instruction
|
||||
00000002 # S mode read from mideleg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mie with illegal instruction
|
||||
00000002 # S mode read from mie with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mtvec with illegal instruction
|
||||
00000002 # S mode read from mtvec with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mcounteren with illegal instruction
|
||||
00000002 # S mode read from mcounteren with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mscratch with illegal instruction
|
||||
00000002 # S mode read from mscratch with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mepc with illegal instruction
|
||||
00000002 # S mode read from mepc with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mcause with illegal instruction
|
||||
00000002 # S mode read from mcause with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mtval with illegal instruction
|
||||
00000002 # S mode read from mtval with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mip with illegal instruction
|
||||
00000002 # S mode read from mip with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to menvcfg with illegal instruction
|
||||
00000002 # S mode read from menvcfg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to menvcfgh with illegal instruction
|
||||
00000002 # S mode read from menvcfgh with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mseccfg with illegal instruction
|
||||
00000002 # S mode read from mseccfg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpcfg0 with illegal instruction
|
||||
00000002 # S mode read from pmpcfg0 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpcfg2 with illegal instruction
|
||||
00000002 # S mode read from pmpcfg2 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr0 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr0 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr1 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr1 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr2 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr2 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr3 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr4 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr5 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr6 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr7 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr8 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr9 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr10 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr11 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr12 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr13 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr14 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to pmpaddr15 with illegal instruction
|
||||
00000002 # S mode read from pmpaddr15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mcycle with illegal instruction
|
||||
00000002 # S mode read from mcycle with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to minstret with illegal instruction
|
||||
00000002 # S mode read from minstret with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter3 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter4 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter5 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter6 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter7 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter8 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter9 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter10 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter11 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter12 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter13 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter14 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter15 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter16 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter16 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter17 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter17 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter18 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter18 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter19 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter19 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter20 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter20 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter21 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter21 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter22 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter22 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter23 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter23 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter24 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter24 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter25 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter25 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter26 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter26 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter27 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter27 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter28 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter28 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter29 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter29 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter30 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter30 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmcounter31 with illegal instruction
|
||||
00000002 # S mode read from mhpmcounter31 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mcountinhibit with illegal instruction
|
||||
00000002 # S mode read from mcountinhibit with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent3 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent4 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent5 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent6 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent7 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent8 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent9 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent10 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent11 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent12 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent13 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent14 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent15 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent16 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent16 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent17 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent17 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent18 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent18 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent19 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent19 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent20 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent20 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent21 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent21 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent22 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent22 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent23 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent23 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent24 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent24 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent25 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent25 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent26 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent26 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent27 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent27 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent28 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent28 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent29 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent29 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent30 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent30 with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mhpmevent31 with illegal instruction
|
||||
00000002 # S mode read from mhpmevent31 with illegal instruction
|
||||
00000bad
|
||||
00000009 # ecall from terminating tess from S mode
|
||||
|
|
@ -1,335 +0,0 @@
|
|||
0000000b # Test 5.2.3.6: ecall from going to U mode from M mode
|
||||
00000002 # U mode write to sstatus with illegal instruction
|
||||
00000002 # U mode read from sstatus with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to sie with illegal instruction
|
||||
00000002 # U mode read from sie with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to stvec with illegal instruction
|
||||
00000002 # U mode read from stvec with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to scounteren with illegal instruction
|
||||
00000002 # U mode read from scounteren with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to sscratch with illegal instruction
|
||||
00000002 # U mode read from sscratch with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to sepc with illegal instruction
|
||||
00000002 # U mode read from sepc with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to scause with illegal instruction
|
||||
00000002 # U mode read from scause with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to stval with illegal instruction
|
||||
00000002 # U mode read from stval with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to sip with illegal instruction
|
||||
00000002 # U mode read from sip with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to satp with illegal instruction
|
||||
00000002 # U mode read from satp with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mvendorid with illegal instruction
|
||||
00000002 # U mode read from mvendorid with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to marchid with illegal instruction
|
||||
00000002 # U mode read from marchid with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mimpid with illegal instruction
|
||||
00000002 # U mode read from mimpid with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhartid with illegal instruction
|
||||
00000002 # U mode read from mhartid with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mconfigptr with illegal instruction
|
||||
00000002 # S mode read from mconfigptr with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mstatus with illegal instruction
|
||||
00000002 # U mode read from mstatus with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mstatush with illegal instruction
|
||||
00000002 # U mode read from mstatush with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to misa with illegal instruction
|
||||
00000002 # U mode read from misa with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to medeleg with illegal instruction
|
||||
00000002 # U mode read from medeleg with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mideleg with illegal instruction
|
||||
00000002 # U mode read from mideleg with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mie with illegal instruction
|
||||
00000002 # U mode read from mie with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mtvec with illegal instruction
|
||||
00000002 # U mode read from mtvec with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mcounteren with illegal instruction
|
||||
00000002 # U mode read from mcounteren with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mscratch with illegal instruction
|
||||
00000002 # U mode read from mscratch with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mepc with illegal instruction
|
||||
00000002 # U mode read from mepc with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mcause with illegal instruction
|
||||
00000002 # U mode read from mcause with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mtval with illegal instruction
|
||||
00000002 # U mode read from mtval with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mip with illegal instruction
|
||||
00000002 # U mode read from mip with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to menvcfg with illegal instruction
|
||||
00000002 # S mode read from menvcfg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to menvcfgh with illegal instruction
|
||||
00000002 # S mode read from menvcfgh with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to mseccfg with illegal instruction
|
||||
00000002 # S mode read from mseccfg with illegal instruction
|
||||
00000bad
|
||||
00000002 # S mode write to senvcfg with illegal instruction
|
||||
00000002 # S mode read from senvcfg with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpcfg0 with illegal instruction
|
||||
00000002 # U mode read from pmpcfg0 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpcfg2 with illegal instruction
|
||||
00000002 # U mode read from pmpcfg2 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr0 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr0 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr1 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr1 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr2 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr2 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr3 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr4 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr5 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr6 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr7 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr8 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr9 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr10 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr11 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr12 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr13 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr14 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to pmpaddr15 with illegal instruction
|
||||
00000002 # U mode read from pmpaddr15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mcycle with illegal instruction
|
||||
00000002 # U mode read from mcycle with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to minstret with illegal instruction
|
||||
00000002 # U mode read from minstret with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter3 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter4 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter5 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter6 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter7 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter8 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter9 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter10 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter11 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter12 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter13 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter14 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter15 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter16 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter16 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter17 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter17 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter18 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter18 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter19 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter19 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter20 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter20 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter21 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter21 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter22 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter22 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter23 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter23 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter24 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter24 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter25 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter25 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter26 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter26 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter27 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter27 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter28 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter28 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter29 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter29 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter30 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter30 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmcounter31 with illegal instruction
|
||||
00000002 # U mode read from mhpmcounter31 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mcountinhibit with illegal instruction
|
||||
00000002 # U mode read from mcountinhibit with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent3 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent3 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent4 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent4 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent5 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent5 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent6 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent6 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent7 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent7 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent8 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent8 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent9 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent9 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent10 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent10 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent11 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent11 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent12 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent12 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent13 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent13 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent14 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent14 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent15 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent15 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent16 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent16 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent17 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent17 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent18 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent18 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent19 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent19 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent20 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent20 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent21 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent21 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent22 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent22 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent23 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent23 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent24 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent24 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent25 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent25 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent26 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent26 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent27 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent27 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent28 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent28 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent29 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent29 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent30 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent30 with illegal instruction
|
||||
00000bad
|
||||
00000002 # U mode write to mhpmevent31 with illegal instruction
|
||||
00000002 # U mode read from mhpmevent31 with illegal instruction
|
||||
00000bad
|
||||
00000008 # ecall from terminating tests in U mode
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction
|
||||
00000011 # confirm read-only permissions of mvendorid
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000011 # confirm read-only permissions of marchid
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000011 # confirm read-only permissions of mimpid
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000011 # confirm read-only permissions of mhartid
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000011 # confirm read-only permissions of mconfigptr
|
||||
0000000b # ecall from terminating tests in M mode
|
||||
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
00000111 # Test 5.3.2.2: successful read of nonzero misa
|
||||
0000000b # ecall from terminating tests in machine mode
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
0ffffff0 # writeback of value written to PMPADDR0, less trailing 4 bits for G = 4
|
||||
20040000
|
||||
20040030
|
||||
20040080
|
||||
20040080
|
||||
200400c0
|
||||
20040130
|
||||
2ffffff0
|
||||
0009001f
|
||||
0018980c
|
||||
1f000000
|
||||
0018980c
|
||||
200400c7
|
||||
00000005
|
||||
00000bad
|
||||
00600dbb
|
||||
0000000b
|
||||
00600d15
|
||||
00600d02
|
||||
00600d12
|
||||
00000007
|
||||
00600daa
|
||||
00000007
|
||||
00000005
|
||||
00000bad
|
||||
00000001
|
||||
00000bad
|
||||
00000111
|
||||
00000009
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
0000000b # Test *** Number: Ecall from going from M mode to S mode
|
||||
00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address
|
||||
00000009 # ecall from ending tests in S mode.
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
00002000 # read SD = 0, FS = 01
|
||||
80006000 # read SD = 1, FS = 11
|
||||
00004000 # read written SD = 1, FS = 10
|
||||
80006000 # read SD = 1, FS = 11
|
||||
00000002 # mcause from attempting fmv with status.FS cleared
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
0000000b # test 5.3.1.6: mcause for ecall from going to S mode from M mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000002 # mcause for illegal sret instruction due to status.tsr bit being set.
|
||||
10200073 # mtval of illegal instruction (illegal instruction's machine code)
|
||||
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000009 # mcause from S mode ecall from test termination
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
|
|
@ -31,7 +31,7 @@ rvtest_entry_point:
|
|||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
|
||||
|
||||
RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",minfo)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",misa)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr_Zifencei")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",pmp)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32IAF_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-fp-enabled)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
RVTEST_ISA("RV32I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",trap-sret)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -1,204 +0,0 @@
|
|||
deadbeef # begin_signature
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000000 # destination 1
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000 # destination 2
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies.
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
0bad0bad
|
||||
0bad0bad
|
||||
0bad0bad
|
||||
0bad0bad
|
||||
|
|
@ -1,592 +0,0 @@
|
|||
0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
|
||||
00000000
|
||||
00000002 # S mode write to mvendorid with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mvendorid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to marchid with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from marchid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mimpid with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mimpid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhartid with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhartid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mconfigptr with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mconfigptr with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mstatus with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mstatus with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to misa with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from misa with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to medeleg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from medeleg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mideleg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mideleg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mie with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mie with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mtvec with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mtvec with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mcounteren with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mcounteren with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mscratch with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mscratch with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mepc with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mepc with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mcause with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mcause with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mtval with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mtval with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mip with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mip with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to menvcfg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from menvcfg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mseccfg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mseccfg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpcfg0 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpcfg0 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpcfg2 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpcfg2 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr0 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr0 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr1 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr1 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr2 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr2 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr3 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr4 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr5 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr6 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr7 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr8 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr9 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr10 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr11 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr12 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr13 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr14 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to pmpaddr15 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from pmpaddr15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mcycle with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mcycle with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to minstret with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from minstret with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter3 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter4 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter5 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter6 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter7 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter8 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter9 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter10 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter11 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter12 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter13 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter14 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter15 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter16 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter16 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter17 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter17 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter18 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter18 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter19 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter19 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter20 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter20 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter21 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter21 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter22 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter22 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter23 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter23 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter24 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter24 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter25 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter25 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter26 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter26 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter27 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter27 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter28 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter28 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter29 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter29 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter30 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter30 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmcounter31 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmcounter31 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mcountinhibit with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mcountinhibit with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent3 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent4 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent5 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent6 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent7 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent8 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent9 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent10 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent11 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent12 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent13 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent14 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent15 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent16 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent16 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent17 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent17 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent18 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent18 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent19 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent19 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent20 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent20 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent21 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent21 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent22 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent22 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent23 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent23 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent24 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent24 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent25 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent25 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent26 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent26 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent27 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent27 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent28 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent28 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent29 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent29 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent30 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent30 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mhpmevent31 with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mhpmevent31 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000009 # ecall from terminating tess from S mode
|
||||
00000000
|
||||
|
|
@ -1,652 +0,0 @@
|
|||
0000000b # Test 5.2.3.6: ecall from going to U mode from M mode
|
||||
00000000
|
||||
00000002 # U mode write to sstatus with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from sstatus with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to sie with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from sie with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to stvec with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from stvec with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to scounteren with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from scounteren with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to sscratch with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from sscratch with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to sepc with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from sepc with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to scause with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from scause with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to stval with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from stval with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to sip with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from sip with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to satp with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from satp with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mvendorid with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mvendorid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to marchid with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from marchid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mimpid with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mimpid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhartid with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhartid with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mconfigptr with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mconfigptr with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mstatus with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mstatus with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to misa with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from misa with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to medeleg with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from medeleg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mideleg with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mideleg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mie with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mie with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mtvec with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mtvec with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mcounteren with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mcounteren with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mscratch with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mscratch with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mepc with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mepc with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mcause with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mcause with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mtval with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mtval with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mip with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mip with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to menvcfg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from menvcfg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # S mode write to mseccfg with illegal instruction
|
||||
00000000
|
||||
00000002 # S mode read from mseccfg with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpcfg0 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpcfg0 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpcfg2 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpcfg2 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr0 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr0 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr1 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr1 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr2 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr2 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr3 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr4 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr5 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr6 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr7 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr8 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr9 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr10 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr11 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr12 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr13 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr14 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to pmpaddr15 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from pmpaddr15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mcycle with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mcycle with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to minstret with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from minstret with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter3 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter4 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter5 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter6 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter7 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter8 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter9 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter10 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter11 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter12 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter13 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter14 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter15 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter16 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter16 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter17 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter17 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter18 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter18 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter19 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter19 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter20 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter20 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter21 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter21 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter22 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter22 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter23 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter23 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter24 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter24 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter25 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter25 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter26 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter26 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter27 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter27 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter28 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter28 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter29 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter29 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter30 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter30 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmcounter31 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmcounter31 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mcountinhibit with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mcountinhibit with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent3 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent3 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent4 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent4 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent5 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent5 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent6 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent6 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent7 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent7 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent8 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent8 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent9 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent9 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent10 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent10 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent11 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent11 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent12 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent12 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent13 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent13 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent14 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent14 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent15 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent15 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent16 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent16 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent17 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent17 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent18 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent18 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent19 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent19 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent20 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent20 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent21 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent21 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent22 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent22 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent23 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent23 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent24 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent24 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent25 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent25 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent26 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent26 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent27 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent27 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent28 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent28 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent29 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent29 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent30 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent30 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # U mode write to mhpmevent31 with illegal instruction
|
||||
00000000
|
||||
00000002 # U mode read from mhpmevent31 with illegal instruction
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000008 # ecall from terminating tests in U mode
|
||||
00000000
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction
|
||||
00000000
|
||||
00000011 # confirm read-only permissions of mvendorid
|
||||
00000000
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000000
|
||||
00000011 # confirm read-only permissions of marchid
|
||||
00000000
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000000
|
||||
00000011 # confirm read-only permissions of mimpid
|
||||
00000000
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000000
|
||||
00000011 # confirm read-only permissions of mhartid
|
||||
00000000
|
||||
00000002 # write to read-only CSR failed with illegal instruction
|
||||
00000000
|
||||
00000011 # confirm read-only permissions of mconfigptr
|
||||
00000000
|
||||
0000000b # ecall from terminating tests in M mode
|
||||
00000000
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
00000111 # Test 5.3.2.2: successful read of nonzero misa
|
||||
00000000
|
||||
0000000b # ecall from terminating tests in machine mode
|
||||
00000000
|
||||
|
|
@ -1,560 +0,0 @@
|
|||
03020100 # ByteDstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
03020100 # Half0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Half1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
03020100 # Word0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Word1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
0100beef # Word2DstData
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef
|
||||
00adbeef # Word3DstData
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
deadbeef
|
||||
03020100 # Double0DstData
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
020100ef # Double1DstData
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef
|
||||
0100beef # Double2DstData
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef
|
||||
00adbeef # Double3DstData
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
deadbeef
|
||||
deadbeef # Double4DstData
|
||||
03020100
|
||||
07060504
|
||||
0b0a0908
|
||||
0f0e0d0c
|
||||
13021110
|
||||
17161514
|
||||
1b1a1918
|
||||
1f1e1d1c
|
||||
23222120
|
||||
27262524
|
||||
2b2a2928
|
||||
2f2e2d2c
|
||||
33023130
|
||||
37363534
|
||||
3b3a3938
|
||||
3f3e3d3c
|
||||
43424140
|
||||
47464544
|
||||
4b4a4948
|
||||
4f4e4d4c
|
||||
53025150
|
||||
57565554
|
||||
5b5a5958
|
||||
5f5e5d5c
|
||||
63626160
|
||||
67666564
|
||||
6b6a6968
|
||||
6f6e6d6c
|
||||
73027170
|
||||
77767574
|
||||
7b7a7978
|
||||
7f7e7d7c
|
||||
deadbeef
|
||||
deadbeef # Double5DstData
|
||||
020100ef
|
||||
06050403
|
||||
0a090807
|
||||
0e0d0c0b
|
||||
0211100f
|
||||
16151413
|
||||
1a191817
|
||||
1e1d1c1b
|
||||
2221201f
|
||||
26252423
|
||||
2a292827
|
||||
2e2d2c2b
|
||||
0231302f
|
||||
36353433
|
||||
3a393837
|
||||
3e3d3c3b
|
||||
4241403f
|
||||
46454443
|
||||
4a494847
|
||||
4e4d4c4b
|
||||
0251504f
|
||||
56555453
|
||||
5a595857
|
||||
5e5d5c5b
|
||||
6261605f
|
||||
66656463
|
||||
6a696867
|
||||
6e6d6c6b
|
||||
0271706f
|
||||
76757473
|
||||
7a797877
|
||||
7e7d7c7b
|
||||
deadbe7f
|
||||
deadbeef # Double6DstData
|
||||
0100beef
|
||||
05040302
|
||||
09080706
|
||||
0d0c0b0a
|
||||
11100f0e
|
||||
15141302
|
||||
19181716
|
||||
1d1c1b1a
|
||||
21201f1e
|
||||
25242322
|
||||
29282726
|
||||
2d2c2b2a
|
||||
31302f2e
|
||||
35343302
|
||||
39383736
|
||||
3d3c3b3a
|
||||
41403f3e
|
||||
45444342
|
||||
49484746
|
||||
4d4c4b4a
|
||||
51504f4e
|
||||
55545302
|
||||
59585756
|
||||
5d5c5b5a
|
||||
61605f5e
|
||||
65646362
|
||||
69686766
|
||||
6d6c6b6a
|
||||
71706f6e
|
||||
75747302
|
||||
79787776
|
||||
7d7c7b7a
|
||||
dead7f7e
|
||||
deadbeef # Double7DstData
|
||||
00adbeef
|
||||
04030201
|
||||
08070605
|
||||
0c0b0a09
|
||||
100f0e0d
|
||||
14130211
|
||||
18171615
|
||||
1c1b1a19
|
||||
201f1e1d
|
||||
24232221
|
||||
28272625
|
||||
2c2b2a29
|
||||
302f2e2d
|
||||
34330231
|
||||
38373635
|
||||
3c3b3a39
|
||||
403f3e3d
|
||||
44434241
|
||||
48474645
|
||||
4c4b4a49
|
||||
504f4e4d
|
||||
54530251
|
||||
58575655
|
||||
5c5b5a59
|
||||
605f5e5d
|
||||
64636261
|
||||
68676665
|
||||
6c6b6a69
|
||||
706f6e6d
|
||||
74730271
|
||||
78777675
|
||||
7c7b7a79
|
||||
de7f7e7d
|
||||
ffffffff #signature
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
000000ff
|
||||
00000000
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
0ffffff0 # Test 12.3.2.2.1: writeback of value written to PMPADDR0, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
20040000 # writeback of value written to PMPADDR1, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
20040030 # writeback of value written to PMPADDR2, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
20040080 # writeback of value written to PMPADDR3, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
20040080 # writeback of value written to PMPADDR4, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
200400c0 # writeback of value written to PMPADDR5, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
20040130 # writeback of value written to PMPADDR6, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
2ffffff0 # writeback of value written to PMPADDR15, less trailing 4 bits for G = 4
|
||||
00000000
|
||||
0009001f # writeback of value written to PMPCFG0
|
||||
0018980c
|
||||
00000000 # writeback of value written to PMPCFG2
|
||||
1f000000
|
||||
0009001f # old value of PMPCFG0 after failed write to locked out region
|
||||
0018980c
|
||||
200400c7 # old value of PMPADDR5 after failed write to locked out region
|
||||
00000000
|
||||
00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00600dbb # read test success from region with L=X=W=R=0
|
||||
00000000
|
||||
0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode
|
||||
00000000
|
||||
00600d15 # read test success from RW range (confirming previous write)
|
||||
00000000
|
||||
00600d02 # read test success from outside the edge of a read only range
|
||||
00000000
|
||||
00600d12 # read test success from outside the other edge of a read only range
|
||||
00000000
|
||||
00000007 # write test with access fault in read only range
|
||||
00000000
|
||||
00600daa # read success from read only range
|
||||
00000000
|
||||
00000007 # write test with access fault in no-access range
|
||||
00000000
|
||||
00000005 # read test with access fault in no-access range
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000001 # execute test with access fault in no-execute range
|
||||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000111 # execute success when X=1
|
||||
00000000
|
||||
00000009 # ecall from terminating tests in S mode
|
||||
00000000
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
0000000b # Test *** Number: Ecall from going from M mode to S mode
|
||||
00000000
|
||||
00000001 # Instruction access fault from turning on virtual memory with invalid satp address
|
||||
00000000
|
||||
00000009 # ecall from ending tests in S mode.
|
||||
00000000
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
00002000 # read SD = 0, FS = 01
|
||||
00000000
|
||||
00006000 # read SD = 1, FS = 11
|
||||
80000000
|
||||
00004000 # read written SD = 1, FS = 10
|
||||
00000000
|
||||
00006000 # read SD = 1, FS = 11
|
||||
80000000
|
||||
00000002 # mcause from attempting fmv with status.FS cleared
|
||||
00000000
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
00000000
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
|
||||
0000000a
|
||||
0000000b # ecall from ending tests in M mode
|
||||
00000000
|
||||
|
|
@ -31,7 +31,7 @@ rvtest_entry_point:
|
|||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
|
||||
|
||||
RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",misa)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ rvtest_entry_point:
|
|||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",ld)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",ld)
|
||||
|
||||
# This test checks the misaligned load and stores work correctly and across D$ line spills.
|
||||
# The general approach is to
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I_Zicsr_Zifencei")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",pmp)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
RVTEST_ISA("RV64IAF_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;",status-fp-enabled)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
RVTEST_ISA("RV64I_Zicsr")
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",xlen)
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue