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Changed DTIM latency to 2 cycles

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David Harris 2021-02-02 14:22:12 -05:00
parent 616830a3f0
commit 9f9c3bcece
1 changed files with 3 additions and 9 deletions
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12
wally-pipelined/src/uncore/dtim.sv
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@ -39,27 +39,21 @@ module dtim (
// logic [`XLEN-1:0] write;
logic [15:0] entry;
logic memread, memwrite;
// logic busy;
logic [3:0] busycount;
// busy FSM to extend READY signal
always_ff @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin
// busy <= 0;
HREADYTim <= 1;
end else begin
// if (~busy & HSELTim) begin
if (HREADYTim & HSELTim) begin
// busy <= 1;
busycount <= 0;
HREADYTim <= 0;
// end else if (busy) begin
end else if (~HREADYTim) begin
busycount <= busycount + 1;
if (busycount == 4) begin // TIM latency, for testing purposes
// busy <= 0;
if (busycount == 0) begin // TIM latency, for testing purposes
HREADYTim <= 1;
end
end else
busycount <= busycount + 1;
end
end