github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-22 12:57:23 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fixed clock edge for Design Compiler compatibility

Browse source
This commit is contained in:
David Harris 2025-03-05 08:39:25 -08:00
parent e69d962e50
commit a166b522e5
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/uncore/spi_controller.sv
View file

@ -207,7 +207,7 @@ module spi_controller (
// Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
// Sweeeeeeeeeet...
assign InvertClock = ^SckMode;
always_ff @(posedge ~PCLK) begin
always_ff @(negedge PCLK) begin
if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0;
SampleEdge <= 0;