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Merge pull request #1365 from coreyqh/ccov

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Full priv and cacheways code coverage
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David Harris 2025-04-17 09:19:44 -07:00 • committed by GitHub
commit ed93cca5f4
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6
sim/questa/coverage-exclusions-rv64gc.do
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@ -451,6 +451,12 @@ coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum
coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "MTIME traps"] -item e 1 -fecexprrow 2 4
coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "assign NextHPMCOUNTERM"] -item b 1
# attempting to write stimecmp with STCE=0 traps, causing CSRSWriteM to go low
coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSTIMECMPM"] -item e 1 -fecexprrow 5
# mode != m_mode and TVM = 1 causes a trap, causing CSRSWriteM to go low
coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSATPM"] -item e 1 -fecexprrow 5 8
####################
# EBU
####################

12
tests/coverage/dcache2.S
View file

@ -31,20 +31,32 @@ main:
li t0, 0x80100770
sd zero, 0(t0)
sd zero, 1(t0)
lr.d t1, (t0)
addi t0, t0, 1
sc.d t2, t1, (t0)
// way 1
li t0, 0x80101770
sd zero, 0(t0)
sd zero, 1(t0)
lr.d t1, (t0)
addi t0, t0, 1
sc.d t2, t1, (t0)
// way 2
li t0, 0x80102770
sd zero, 0(t0)
sd zero, 1(t0)
lr.d t1, (t0)
addi t0, t0, 1
sc.d t2, t1, (t0)
// way 3
li t0, 0x80103770
sd zero, 0(t0)
sd zero, 1(t0)
lr.d t1, (t0)
addi t0, t0, 1
sc.d t2, t1, (t0)
j done