Merge pull request #716 from davidharrishmc/dev

Fixed coremark to use wsim, more testfloat regression tests

.gitignore

@@ -190,3 +190,4 @@ sim/verilator/logs
 sim/verilator/wkdir
 sim/vcs/logs
 sim/vcs/wkdir
+benchmarks/coremark/coremark_results.csv

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
+Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b

benchmarks/coremark/Makefile

@@ -28,7 +28,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
+	#(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump

benchmarks/coremark/coremark_sweep.py

@@ -73,6 +73,7 @@ with open('coremark_results.csv', mode='w', newline='') as csvfile:
         os.system(make_all)
 
         make_run = f"make run XLEN={xlen_value} ARCH={arch}"
+        print("Running: " + make_run)
         output = os.popen(make_run).read()  # Capture the output of the command
 
         # Extract the Coremark values using regular expressions

bin/regression-wally

@@ -254,20 +254,20 @@ os.chdir(regressionDir)
 coveragesim = "questa"  # Questa is required for code/functional coverage
 defaultsim = "questa"   # Default simulator for all other tests; change to Verilator when flow is ready
 
-coverage = '-coverage' in sys.argv
+coverage = '--coverage' in sys.argv
-fp = '-fp' in sys.argv
+fp = '--fp' in sys.argv
-nightly = '-nightly' in sys.argv
+nightly = '--nightly' in sys.argv
-testfloat = '-testfloat' in sys.argv
+testfloat = '--testfloat' in sys.argv
 
 if (nightly):
-    nightMode = "-nightly";
+    nightMode = "--nightly";
     sims = ["questa", "verilator", "vcs"]
 else:
     nightMode = "";
     sims = [defaultsim]
 
 if (coverage):  # only run RV64GC tests in coverage mode
-    coverStr = '-coverage'
+    coverStr = '--coverage'
 else:
    coverStr = ''
 
@@ -298,7 +298,22 @@ else:
 # testfloat tests
 if (testfloat):
     configs = []
-    testfloatconfigs = [
+
+    testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
+    for config in testfloatconfigs:
+        tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
+        if ("f_" in config):
+            tests.remove("cvtfp")
+        for test in tests:
+            tc = TestCase(
+                    name=test,
+                    variant=config,
+                    cmd="wsim --tb testbench_fp " + config + " " + test,
+                    grepstr="All Tests completed with          0 errors")
+            configs.append(tc)
+
+
+    testfloatdivconfigs = [
     "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
     "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
     "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
@@ -324,12 +339,14 @@ if (testfloat):
     "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc",
     "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc"
     ]
-    for config in testfloatconfigs:
+    for config in testfloatdivconfigs:
         # div test case
         tests = ["div", "sqrt"]
         if ("ieee" in config):
             tests.append("cvtint")
             tests.append("cvtfp")
+        if ("f_" in config):
+            tests.remove("cvtfp")
         for test in tests:
             tc = TestCase(
                     name=test,
@@ -349,26 +366,26 @@ def main():
         except:
             pass
  
-    if '-makeTests' in sys.argv:
+    if '--makeTests' in sys.argv:
         os.chdir(regressionDir)
         os.system('./make-tests.sh | tee ./logs/make-tests.log')
 
-    if '-all' in sys.argv:
+    if '--all' in sys.argv:
         TIMEOUT_DUR = 30*7200 # seconds
         #configs.append(getBuildrootTC(boot=True))
-    elif '-buildroot' in sys.argv:
+    elif '--buildroot' in sys.argv:
         TIMEOUT_DUR = 30*7200 # seconds
         #configs=[getBuildrootTC(boot=True)]
-    elif '-coverage' in sys.argv:
+    elif '--coverage' in sys.argv:
         TIMEOUT_DUR = 20*60 # seconds    
     #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
     #   Also it is slow to run.   
     #    configs.append(getBuildrootTC(boot=False))
         os.system('rm -f cov/*.ucdb')
-    elif '-nightly' in sys.argv:
+    elif '--nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
         #configs.append(getBuildrootTC(boot=False))
-    elif '-testfloat' in sys.argv:
+    elif '--testfloat' in sys.argv:
         TIMEOUT_DUR = 60*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds

config/derivlist.txt

@@ -587,6 +587,9 @@ IEEE754     1
 deriv fd_ieee_rv64gc fd_rv64gc
 IEEE754     1
 
+deriv fdh_ieee_rv64gc fdh_rv64gc
+IEEE754     1
+
 deriv fdq_ieee_rv64gc fdq_rv64gc
 IEEE754     1
 

testbench/testbench_fp.sv

@@ -821,8 +821,8 @@ module testbench_fp;
       case (UnitVal)
 	`FMAUNIT: Res = FpRes;
 	`DIVUNIT: Res = FpRes;
-	`CMPUNIT: Res = {{(FLEN-XLEN){1'b0}}, CmpRes};
+	`CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes};
-	`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN-XLEN){1'b0}}, IntRes}; else Res = FpRes;
+	`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes;
 	`CVTFPUNIT: Res = FpRes;
       endcase
 
@@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // quad -> long
                     X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // quad -> int
                     X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
@@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // single -> long
                     X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // single -> int
                     X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
@@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // half -> long
                     X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // half -> int
                     X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};