mirror of
https://github.com/openhwgroup/cvw.git
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Merge pull request #711 from ross144/main
Got questa running with the wavefiles with unified do for testbench and testbench-fp
This commit is contained in:
David Harris
GitHub
commit
b7b835f4eb
10 changed files with 138 additions and 80 deletions
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@ -246,10 +246,10 @@ def run_test_case(config):
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# Main body
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##################################
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regressionDir = os.path.dirname(os.path.abspath(__file__))
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os.chdir(regressionDir)
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WALLY = os.environ.get('WALLY')
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regressionDir = WALLY + '/sim'
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os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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10
bin/wsim
10
bin/wsim
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@ -37,6 +37,16 @@ if (args.coverage):
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print("Coverage option only available for Questa")
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exit(1)
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# create the output sub-directories.
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WALLY = os.environ.get('WALLY')
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regressionDir = WALLY + '/sim/'
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for d in ["logs", "wkdir", "cov"]:
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try:
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os.mkdir(regressionDir+args.sim+"/"+d)
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except:
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pass
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# Launch selected simulator
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cd = "cd $WALLY/sim/" +args.sim
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if (args.sim == "questa"):
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@ -9,4 +9,6 @@
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# sqrt - test square root
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# all - test everything
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vsim -do "do testfloat.do fdqh_ieee_rv64gc $1"
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wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui
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@ -1,2 +1,2 @@
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vsim -do "do wally.do rv64gc wally64periph"
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wsim rv64gc arch64i --gui
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@ -1 +1 @@
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../wsim rv64gc arch64i
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wsim rv64gc arch64i
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@ -50,6 +50,9 @@ set from 4
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set step 1
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set lst {}
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set GUI 0
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set PlusArgs {}
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set ParamArgs {}
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set accFlag ""
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for {set i 0} true {incr i} {
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set x [expr {$i*$step + $from}]
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if {$x > $argc} break
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@ -58,13 +61,29 @@ for {set i 0} true {incr i} {
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}
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if {$argc >= 3} {
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set tbArgs $lst
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puts $tbArgs
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if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} {
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set GUI 1
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}
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set accFlag "+acc"
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set tbArgs [lrange $lst 0 end-1]
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} else {
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set tbArgs $lst
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}
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set tbArgsLst [split $lst " "]
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# might be able to remove this, but I'm keeping the code for now in case we need to separate the two types of args.
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foreach otherArg $tbArgsLst {
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if {[string index $otherArg 0] eq "+"} {
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lappend PlusArgs $otherArg
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} else {
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lappend ParamArgs $otherArg
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}
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}
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#echo "PlusArgs"
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#echo $PlusArgs
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#echo "ParamArgs"
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#echo $ParamArgs
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#echo "accFlag"
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#echo $accFlag
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#if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
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# set coverage 1
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# set CoverageVoptArg "+cover=sbecf"
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@ -84,9 +103,9 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdi
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
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vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
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# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim
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vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${tbArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg}
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vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} -fatal 7 -suppress 3829 ${CoverageVsimArg}
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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@ -205,7 +205,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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@ -407,29 +406,29 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
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add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
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add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
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add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
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||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
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||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
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||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
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||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
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||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
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||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
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||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
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add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
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||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
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||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW
|
||||
|
|
@ -678,4 +677,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {11566 ns} {11760 ns}
|
||||
WaveRestoreZoom {0 ns} {284634 ns}
|
||||
|
|
|
|||
25
testbench/coverage/test_fencei_coverage.svh
Normal file
25
testbench/coverage/test_fencei_coverage.svh
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t;
|
||||
|
||||
covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins);
|
||||
option.per_instance = 1;
|
||||
option.comment = "Fence.I";
|
||||
|
||||
cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) {
|
||||
option.comment = "Number of times instruction is executed";
|
||||
bins count[] = {1};
|
||||
}
|
||||
endgroup
|
||||
|
||||
function void test_fencei_sample(int hart, int issue);
|
||||
test_ins_rv64i_t ins;
|
||||
|
||||
case (traceDataQ[hart][issue][0].inst_name)
|
||||
"fenci" : begin
|
||||
ins = new(hart, issue, traceDataQ);
|
||||
test_fencei_cg.sample(ins);
|
||||
end
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
4
testbench/coverage/test_fencei_coverage_init.svh
Normal file
4
testbench/coverage/test_fencei_coverage_init.svh
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei");
|
||||
|
||||
// test_fencei_cg = new();
|
||||
//test_fencei_cg.set_inst_name("obj_fencei");
|
||||
|
|
@ -108,8 +108,6 @@ module testbench;
|
|||
TEST = "none";
|
||||
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
|
||||
INSTR_LIMIT = 0;
|
||||
$display("INSTR_LIMIT = ", INSTR_LIMIT);
|
||||
|
||||
|
||||
// pick tests based on modes supported
|
||||
//tests = '{};
|
||||
|
|
@ -246,7 +244,7 @@ module testbench;
|
|||
logic ResetCntRst;
|
||||
logic CopyRAM;
|
||||
|
||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
|
||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
|
||||
integer begin_signature_addr, end_signature_addr, signature_size;
|
||||
|
||||
assign ResetThreshold = 3'd5;
|
||||
|
|
@ -338,8 +336,9 @@ module testbench;
|
|||
else if(TEST == "buildroot") begin
|
||||
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||
uartoutfilename = {"logs/",TEST,"_uart.out"};
|
||||
$system("rm ",uartoutfilename); // Delete existing UARToutfile
|
||||
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
||||
rmCmd = {"rm ", uartoutfilename};
|
||||
$system(rmCmd); // Delete existing UARToutfile
|
||||
end
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
if (riscofTest) begin
|
||||
|
|
@ -582,7 +581,7 @@ module testbench;
|
|||
|
||||
// Append UART output to file for tests
|
||||
always @(posedge clk) begin
|
||||
if (TEST == "buildroot") begin
|
||||
if (P.UART_SUPPORTED & TEST == "buildroot") begin
|
||||
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
|
||||
memFile = $fopen(uartoutfilename, "ab");
|
||||
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue