mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-22 21:08:08 -04:00
Merge branch 'main' of github.com:10x-Engineers/cvw
This commit is contained in:
Huda-10xe
commit
c5605dc07b
22 changed files with 214 additions and 437 deletions
5
.gitignore
vendored
5
.gitignore
vendored
|
|
@ -26,9 +26,8 @@ tests/riscof/config32e.ini
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|||
tests/riscof/config64.ini
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||||
tests/riscof/riscof_work/
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||||
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
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||||
tests/fp/vectors/**/*.tv
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||||
tests/fp/vectors/**/sed*
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||||
tests/fp/testfloat/*
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||||
tests/fp/vectors/*.tv
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||||
tests/fp/vectors/sed*
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||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
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tests/custom/*/*/
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tests/custom/*/*/*.memfile
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||||
|
|
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|||
|
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@ -438,13 +438,12 @@ if (args.testfloat): # for testfloat alone, just run testfloat tests
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if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
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testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved
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testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"]
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testfloatconfigs.append("fdqh_ieee_rv64gc") # run IEEE tests for single config
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for config in testfloatconfigs:
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tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
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if ("f_" in config):
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tests.remove("cvtfp")
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for test in tests:
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sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log"
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sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log"
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tc = TestCase(
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name=test,
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variant=config,
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|
|
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|||
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@ -208,9 +208,10 @@ fi
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section_header "Installing/Updating RISC-V GNU Toolchain"
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STATUS="RISC-V GNU Toolchain"
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cd "$RISCV"
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if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
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||||
# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
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if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then
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cd riscv-gnu-toolchain
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git reset --hard && git clean -f && git checkout master && git pull
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git reset --hard && git clean -f && git checkout b488ddb #&& git pull
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./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
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make -j "${NUM_THREADS}" 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ]
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if [ "$clean" ]; then
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|
|
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15
bin/wsim
15
bin/wsim
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@ -66,7 +66,9 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che
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print("ELF file not found: " + args.testsuite)
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exit(1)
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||||
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if(args.lockstep and not args.testsuite.endswith('.elf')):
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print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.")
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exit(1)
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|
||||
# Validate arguments
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if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep or args.lockstepverbose):
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||||
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@ -86,11 +88,12 @@ if (args.tb == "testbench_fp"):
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|||
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
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if(int(args.locksteplog) >= 1): EnableLog = 1
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||||
else: EnableLog = 0
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||||
if((args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp) and args.sim == "questa"):
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||||
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
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||||
prefix = "MTI_VCO_MODE=64 " + prefix
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||||
else:
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||||
prefix = ""
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||||
prefix = ""
|
||||
if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp):
|
||||
if (args.sim == "questa" or args.sim == "vcs"):
|
||||
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
|
||||
if (args.sim == "questa"):
|
||||
prefix = "MTI_VCO_MODE=64 " + prefix
|
||||
|
||||
if (args.lockstep or args.lockstepverbose):
|
||||
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
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||||
|
|
|
|||
|
|
@ -880,11 +880,6 @@ deriv fdqh_rv64gc rv64gc
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|||
Q_SUPPORTED 1
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||||
ZFH_SUPPORTED 1
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||||
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||||
# IEEE compatible FPU
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||||
|
||||
deriv fdqh_ieee_rv64gc fdqh_rv64gc
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||||
IEEE754 1
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||||
|
||||
#### MORE DIVIDER variants
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||||
|
||||
#### F_only, RK variable
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||||
|
|
|
|||
|
|
@ -7,5 +7,6 @@
|
|||
|
||||
`include "RV64I_coverage.svh"
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||||
`include "RV64M_coverage.svh"
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||||
//`include "RV64F_coverage.svh"
|
||||
`include "RV64F_coverage.svh"
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||||
`include "RV64Zicond_coverage.svh"
|
||||
`include "RV64Zca_coverage.svh"
|
||||
|
|
|
|||
|
|
@ -1,15 +1,10 @@
|
|||
# Makefile
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||||
# fpcalc Makefile
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||||
|
||||
CC = gcc
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||||
CFLAGS = -O3 -Wno-format-overflow
|
||||
# Link against the riscv-isa-sim version of SoftFloat rather than
|
||||
# the regular version to get RISC-V NaN behavior
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||||
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
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||||
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
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#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
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||||
#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
|
||||
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
SRCS = $(wildcard *.c)
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||||
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
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||||
|
||||
all: $(PROGS)
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||||
|
|
@ -17,5 +12,5 @@ all: $(PROGS)
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|||
%: %.c
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||||
$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
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||||
|
||||
clean:
|
||||
clean:
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||||
rm -f $(PROGS)
|
||||
|
|
|
|||
|
|
@ -1,22 +1,17 @@
|
|||
# Makefile
|
||||
# softfloat_demo Makefile
|
||||
|
||||
CC = gcc
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||||
CFLAGS = -O3
|
||||
LFLAGS = -L.
|
||||
# Link against the riscv-isa-sim version of SoftFloat rather than
|
||||
# the regular version to get RISC-V NaN behavior
|
||||
#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
|
||||
#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
|
||||
IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
|
||||
LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
|
||||
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
SRCS = $(wildcard *.c)
|
||||
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
|
||||
|
||||
all: $(PROGS)
|
||||
|
||||
%: %.c
|
||||
$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
|
||||
|
||||
clean:
|
||||
clean:
|
||||
rm -f $(PROGS)
|
||||
|
|
|
|||
|
|
@ -4,14 +4,9 @@ CC = gcc
|
|||
CFLAGS = -O3
|
||||
LIBS = -lm
|
||||
LFLAGS = -L.
|
||||
# Link against the riscv-isa-sim version of SoftFloat rather than
|
||||
# the regular version to get RISC-V NaN behavior
|
||||
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
|
||||
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
|
||||
#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
|
||||
#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a
|
||||
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
|
||||
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
|
||||
SRCS = $(wildcard *.c)
|
||||
|
||||
PROGS = $(patsubst %.c,%,$(SRCS))
|
||||
|
||||
all: $(PROGS)
|
||||
|
|
|
|||
|
|
@ -92,13 +92,47 @@ typedef struct {
|
|||
|
||||
} RequiredRVVI_t; // total size is 241 bits or 30.125 bytes
|
||||
|
||||
typedef struct __attribute__((packed)) {
|
||||
uint64_t PC;
|
||||
uint32_t insn;
|
||||
uint64_t Mcycle;
|
||||
uint64_t Minstret;
|
||||
uint8_t Trap : 1;
|
||||
uint8_t PrivilegeMode : 2;
|
||||
uint8_t GPREn : 1;
|
||||
uint8_t FPREn : 1;
|
||||
uint8_t Pad3: 3;
|
||||
uint16_t CSRCount : 12;
|
||||
uint16_t Pad4 : 4;
|
||||
uint8_t GPRReg : 5;
|
||||
uint8_t PadG3 : 3;
|
||||
uint64_t GPRValue;
|
||||
uint8_t FPRReg : 5;
|
||||
uint8_t PadF3 : 3;
|
||||
uint64_t FPRValue;
|
||||
uint16_t CSR0Wen : 12;
|
||||
uint16_t PadC04 : 4;
|
||||
uint64_t CSR0Value;
|
||||
uint16_t CSR1Wen : 12;
|
||||
uint16_t PadC14 : 4;
|
||||
uint64_t CSR1Value;
|
||||
uint16_t CSR2Wen : 12;
|
||||
uint16_t PadC24 : 4;
|
||||
uint64_t CSR2Value;
|
||||
uint16_t CSR3Wen : 12;
|
||||
uint16_t PadC34 : 4;
|
||||
uint64_t CSR3Value;
|
||||
uint16_t CSR4Wen : 12;
|
||||
uint16_t PadC44 : 4;
|
||||
uint64_t CSR4Value;
|
||||
} FixedRequiredRVVI_t; // 904 bits
|
||||
|
||||
typedef struct {
|
||||
uint8_t RegAddress : 5;
|
||||
uint64_t RegValue;
|
||||
} Reg_t;
|
||||
|
||||
void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData);
|
||||
void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length);
|
||||
void PrintInstructionData(RequiredRVVI_t *InstructionData);
|
||||
int ProcessRvviAll(RequiredRVVI_t *InstructionData);
|
||||
void set_gpr(int hart, int reg, uint64_t value);
|
||||
|
|
@ -345,111 +379,50 @@ void set_fpr(int hart, int reg, uint64_t value){
|
|||
}
|
||||
|
||||
void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData){
|
||||
// you know this actually easiser in assembly. :(
|
||||
uint8_t buf2[BUF_SIZ], buf3[BUF_SIZ];
|
||||
uint8_t * buf2ptr, *buf3ptr;
|
||||
buf2ptr = buf2;
|
||||
buf3ptr = buf3;
|
||||
//int PayloadSize = sizeof(RequiredRVVI_t) - 1;
|
||||
int PayloadSize = 30;
|
||||
int Buf2Size = BUF_SIZ - PayloadSize;
|
||||
uint64_t Mcycle, Minstret;
|
||||
uint64_t PC;
|
||||
uint32_t insn;
|
||||
// unforunately the struct appoarch does not work?!?
|
||||
PC = * (uint64_t *) payload;
|
||||
payload += 8;
|
||||
insn = * (uint32_t *) payload;
|
||||
payload += 4;
|
||||
Mcycle = * (uint64_t *) payload;
|
||||
payload += 8;
|
||||
Minstret = * (uint64_t *) payload;
|
||||
payload += 8;
|
||||
// the next 4 bytes contain CSRCount (12), FPRWen(1), GPRWen(1), PrivilegeMode(2), Trap(1)
|
||||
uint32_t RequiredFlags;
|
||||
RequiredFlags = * (uint32_t *) payload;
|
||||
uint8_t Trap, PrivilegeMode, GPRWen, FPRWen;
|
||||
uint16_t CSRCount = 0;
|
||||
uint8_t GPRReg = 0;
|
||||
uint64_t GPRData = 0;
|
||||
uint8_t FPRReg = 0;
|
||||
uint64_t FPRData = 0;
|
||||
uint8_t CSRWen[3] = {0, 0, 0};
|
||||
uint16_t CSRReg[3];
|
||||
uint64_t CSRValue[3];
|
||||
int CSRIndex;
|
||||
|
||||
Trap = RequiredFlags & 0x1;
|
||||
PrivilegeMode = (RequiredFlags >> 1) & 0x3;
|
||||
GPRWen = (RequiredFlags >> 3) & 0x1;
|
||||
FPRWen = (RequiredFlags >> 4) & 0x1;
|
||||
CSRCount = (RequiredFlags >> 5) & 0xFFF;
|
||||
payload += 2;
|
||||
FixedRequiredRVVI_t *FixedInstructionData = (FixedRequiredRVVI_t *) payload;
|
||||
InstructionData->PC = FixedInstructionData->PC;
|
||||
InstructionData->insn = FixedInstructionData->insn;
|
||||
InstructionData->Mcycle = FixedInstructionData->Mcycle;
|
||||
InstructionData->Minstret = FixedInstructionData->Minstret;
|
||||
InstructionData->Trap = FixedInstructionData->Trap;
|
||||
InstructionData->PrivilegeMode = FixedInstructionData->PrivilegeMode;
|
||||
InstructionData->GPREn = FixedInstructionData->GPREn;
|
||||
InstructionData->FPREn = FixedInstructionData->FPREn;
|
||||
InstructionData->CSRCount = FixedInstructionData->CSRCount;
|
||||
InstructionData->GPRReg = FixedInstructionData->GPRReg;
|
||||
InstructionData->GPRValue = FixedInstructionData->GPRValue;
|
||||
InstructionData->FPRReg = FixedInstructionData->FPRReg;
|
||||
InstructionData->FPRValue = FixedInstructionData->FPRValue;
|
||||
|
||||
if(GPRWen || FPRWen || (CSRCount != 0)){
|
||||
// the first bit of payload is the last bit of CSRCount.
|
||||
ssize_t newPayloadSize = payloadsize - 30;
|
||||
BitShiftArray(buf2, payload, 1, newPayloadSize);
|
||||
int index;
|
||||
if(GPRWen){
|
||||
GPRReg = * (uint8_t *) buf2ptr;
|
||||
GPRReg = GPRReg & 0x1F;
|
||||
BitShiftArray(buf3, buf2ptr, 5, newPayloadSize);
|
||||
GPRData = * (uint64_t *) buf3;
|
||||
if(FPRWen){
|
||||
buf3ptr += 8;
|
||||
FPRReg = * (uint8_t *) buf3ptr;
|
||||
BitShiftArray(buf2, buf3ptr, 5, newPayloadSize - 8);
|
||||
FPRReg = FPRReg & 0x1F;
|
||||
FPRData = * (uint64_t *) buf2;
|
||||
}
|
||||
}else if(FPRWen){
|
||||
FPRReg = * (uint8_t *) buf2;
|
||||
FPRReg = FPRReg & 0x1F;
|
||||
BitShiftArray(buf3, buf2, 5, newPayloadSize);
|
||||
FPRData = * (uint64_t *) buf3;
|
||||
}
|
||||
if(GPRWen ^ FPRWen){
|
||||
payload += 8;
|
||||
Buf2Size = payloadsize - 38;
|
||||
BitShiftArray(buf2, payload, 6, Buf2Size);
|
||||
}else if(GPRWen & FPRWen){
|
||||
payload += 17;
|
||||
Buf2Size = payloadsize - 47;
|
||||
BitShiftArray(buf2, payload, 3, Buf2Size);
|
||||
}else{
|
||||
Buf2Size = payloadsize - 30;
|
||||
BitShiftArray(buf2, payload, 1, Buf2Size);
|
||||
}
|
||||
buf2ptr = buf2;
|
||||
for(CSRIndex = 0; CSRIndex < CSRCount; CSRIndex++){
|
||||
CSRReg[CSRIndex] = (*(uint16_t *) buf2ptr) & 0xFFF;
|
||||
Buf2Size -= 1;
|
||||
BitShiftArray(buf3, buf2ptr + 1, 4, Buf2Size);
|
||||
CSRValue[CSRIndex] = (*(uint64_t *) buf3);
|
||||
CSRWen[CSRIndex] = 1;
|
||||
buf2ptr = buf3;
|
||||
}
|
||||
}
|
||||
InstructionData->PC = PC;
|
||||
InstructionData->insn = insn;
|
||||
InstructionData->Mcycle = Mcycle;
|
||||
InstructionData->Minstret = Minstret;
|
||||
InstructionData->Trap = Trap;
|
||||
InstructionData->PrivilegeMode = PrivilegeMode;
|
||||
InstructionData->GPREn = GPRWen;
|
||||
InstructionData->FPREn = FPRWen;
|
||||
InstructionData->CSRCount = CSRCount;
|
||||
InstructionData->GPRReg = GPRReg;
|
||||
InstructionData->GPRValue = GPRData;
|
||||
InstructionData->FPRReg = FPRReg;
|
||||
InstructionData->FPRValue = FPRData;
|
||||
for(CSRIndex = 0; CSRIndex < 3; CSRIndex++){
|
||||
InstructionData->CSRWen[CSRIndex] = CSRWen[CSRIndex];
|
||||
InstructionData->CSRReg[CSRIndex] = CSRReg[CSRIndex];
|
||||
InstructionData->CSRValue[CSRIndex] = CSRValue[CSRIndex];
|
||||
}
|
||||
}
|
||||
|
||||
InstructionData->CSRReg[0] = FixedInstructionData->CSR0Wen;
|
||||
if(InstructionData->CSRReg[0] != 0) InstructionData->CSRWen[0] = 1;
|
||||
else InstructionData->CSRWen[0] = 0;
|
||||
InstructionData->CSRValue[0] = FixedInstructionData->CSR0Value;
|
||||
|
||||
InstructionData->CSRReg[1] = FixedInstructionData->CSR1Wen;
|
||||
if(InstructionData->CSRReg[1] != 0) InstructionData->CSRWen[1] = 1;
|
||||
else InstructionData->CSRWen[1] = 0;
|
||||
InstructionData->CSRValue[1] = FixedInstructionData->CSR1Value;
|
||||
|
||||
InstructionData->CSRReg[2] = FixedInstructionData->CSR2Wen;
|
||||
if(InstructionData->CSRReg[2] != 0) InstructionData->CSRWen[2] = 1;
|
||||
else InstructionData->CSRWen[2] = 0;
|
||||
InstructionData->CSRValue[2] = FixedInstructionData->CSR2Value;
|
||||
|
||||
//InstructionData->CSRReg[3] = FixedInstructionData->CSR3Wen;
|
||||
InstructionData->CSRReg[3] = 0;
|
||||
if(InstructionData->CSRReg[3] != 0) InstructionData->CSRWen[3] = 1;
|
||||
else InstructionData->CSRWen[3] = 0;
|
||||
InstructionData->CSRValue[3] = FixedInstructionData->CSR3Value;
|
||||
|
||||
//InstructionData->CSRReg[4] = FixedInstructionData->CSR4Wen;
|
||||
InstructionData->CSRReg[4] = 0;
|
||||
if(InstructionData->CSRReg[4] != 0) InstructionData->CSRWen[4] = 1;
|
||||
else InstructionData->CSRWen[4] = 0;
|
||||
InstructionData->CSRValue[4] = FixedInstructionData->CSR4Value;
|
||||
}
|
||||
|
||||
void PrintInstructionData(RequiredRVVI_t *InstructionData){
|
||||
int CSRIndex;
|
||||
|
|
@ -468,33 +441,3 @@ void PrintInstructionData(RequiredRVVI_t *InstructionData){
|
|||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
void BitShiftArray(uint8_t *dst, uint8_t *src, uint8_t ShiftAmount, int Length){
|
||||
// always shift right by ShiftAmount (0 to 7 bit positions).
|
||||
// *** this implemenation is very inefficient. improve later.
|
||||
if(ShiftAmount < 0 || ShiftAmount > 7) return;
|
||||
/* Read the first source byte
|
||||
Read the second source byte
|
||||
Right Shift byte 1 by ShiftAmount
|
||||
Right Rotate byte 2 by ShiftAmount
|
||||
Mask byte 2 by ~(2^ShiftAmount -1)
|
||||
OR together the two bytes to form the final next byte
|
||||
|
||||
repeat this for each byte
|
||||
On the last byte we don't do the last steps
|
||||
*/
|
||||
int Index;
|
||||
for(Index = 0; Index < Length - 1; Index++){
|
||||
uint8_t byte1 = src[Index];
|
||||
uint8_t byte2 = src[Index+1];
|
||||
byte1 = byte1 >> ShiftAmount;
|
||||
uint8_t byte2rot = (byte2 << (unsigned) (8 - ShiftAmount)) & 0xff;
|
||||
uint8_t byte1final = byte2rot | byte1;
|
||||
dst[Index] = byte1final;
|
||||
}
|
||||
// fence post
|
||||
// For last one there is only one source byte
|
||||
uint8_t byte1 = src[Length-1];
|
||||
byte1 = byte1 >> ShiftAmount;
|
||||
dst[Length-1] = byte1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -502,7 +502,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
|||
logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
|
||||
|
||||
logic valid;
|
||||
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
|
||||
logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
|
||||
|
||||
assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
|
||||
assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
|
||||
|
|
|
|||
|
|
@ -98,7 +98,6 @@ module alu import cvw::*; #(parameter cvw_t P) (
|
|||
3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt
|
||||
3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu
|
||||
3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
|
||||
// 3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported)
|
||||
3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
|
||||
3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
|
||||
3'b111: FullResult = AndResult; // and, bclr, czero.*
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
|
|||
parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4,
|
||||
parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2
|
||||
)(
|
||||
input logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi,
|
||||
input logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi,
|
||||
input logic valid,
|
||||
input logic m_axi_aclk, m_axi_aresetn,
|
||||
output logic RVVIStall,
|
||||
|
|
@ -45,7 +45,9 @@ module packetizer import cvw::*; #(parameter cvw_t P,
|
|||
input logic RvviAxiWready
|
||||
);
|
||||
|
||||
localparam TotalFrameLengthBits = 2*48+17+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12);
|
||||
localparam NearTotalFrameLengthBits = 2*48+16+72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16);
|
||||
localparam WordPadLen = 32 - (NearTotalFrameLengthBits % 32);
|
||||
localparam TotalFrameLengthBits = NearTotalFrameLengthBits + WordPadLen;
|
||||
localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8;
|
||||
|
||||
logic [9:0] WordCount;
|
||||
|
|
@ -56,11 +58,11 @@ module packetizer import cvw::*; #(parameter cvw_t P,
|
|||
logic WordCountEnable;
|
||||
logic [47:0] SrcMac, DstMac;
|
||||
logic [15:0] EthType, Length;
|
||||
logic [31:0] Tag;
|
||||
logic [TotalFrameLengthBits-1:0] TotalFrame;
|
||||
logic [31:0] TotalFrameWords [TotalFrameLengthBytes/4-1:0];
|
||||
logic [WordPadLen-1:0] WordPad;
|
||||
|
||||
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvviDelay;
|
||||
logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvviDelay;
|
||||
|
||||
typedef enum {STATE_RST, STATE_COUNT, STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_INSERT_DELAY} statetype;
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
|
@ -109,7 +111,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
|
|||
counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount);
|
||||
|
||||
|
||||
flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay);
|
||||
flopenr #(72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay);
|
||||
|
||||
|
||||
counter #(10) WordCounter(m_axi_aclk, WordCountReset, WordCountEnable, WordCount);
|
||||
|
|
@ -124,12 +126,12 @@ module packetizer import cvw::*; #(parameter cvw_t P,
|
|||
end
|
||||
|
||||
assign Length = {4'b0, BytesInFrame};
|
||||
assign TotalFrame = {17'b0, rvviDelay, EthType, DstMac, SrcMac};
|
||||
assign WordPad = '0;
|
||||
assign TotalFrame = {WordPad, rvviDelay, EthType, DstMac, SrcMac};
|
||||
|
||||
// *** fix me later
|
||||
assign DstMac = 48'h8F54_0000_1654; // made something up
|
||||
assign SrcMac = 48'h4502_1111_6843;
|
||||
assign Tag = 32'b0;
|
||||
assign EthType = 16'h005c;
|
||||
|
||||
assign RvviAxiWdata = TotalFrameWords[WordCount[4:0]];
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
|||
input logic [P.XLEN-1:0] GPRValue, FPRValue,
|
||||
input var logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0],
|
||||
output logic valid,
|
||||
output logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi
|
||||
output logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi
|
||||
);
|
||||
|
||||
// pipeline controlls
|
||||
|
|
@ -65,9 +65,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
|||
logic [MAX_CSRS-1:0] EnabledCSRs;
|
||||
logic [MAX_CSRS-1:0] CSRCountShort;
|
||||
logic [11:0] CSRCount;
|
||||
logic [177+P.XLEN-1:0] Required;
|
||||
logic [10+2*P.XLEN-1:0] Registers;
|
||||
logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs;
|
||||
logic [56+3*P.XLEN-1:0] Required;
|
||||
logic [16+2*P.XLEN-1:0] Registers;
|
||||
logic [MAX_CSRS*(P.XLEN+16)-1:0] CSRs;
|
||||
|
||||
assign XLENZeros = '0;
|
||||
|
||||
|
|
@ -82,10 +82,10 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
|||
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
|
||||
|
||||
assign valid = InstrValidW & ~StallW;
|
||||
assign Required = {CSRCount, FPRWen, GPRWen, PrivilegeModeW, TrapW, Minstret, Mcycle, InstrRawW, PCW};
|
||||
assign Registers = {FPRWen, GPRWen} == 2'b11 ? {FPRValue, FPRAddr, GPRValue, GPRAddr} :
|
||||
{FPRWen, GPRWen} == 2'b01 ? {XLENZeros, 5'b0, GPRValue, GPRAddr} :
|
||||
{FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} :
|
||||
assign Required = {4'b0, CSRCount, 3'b0, FPRWen, GPRWen, PrivilegeModeW, TrapW, Minstret, Mcycle, InstrRawW, PCW};
|
||||
assign Registers = {FPRWen, GPRWen} == 2'b11 ? {FPRValue, 3'b0, FPRAddr, GPRValue, 3'b0, GPRAddr} :
|
||||
{FPRWen, GPRWen} == 2'b01 ? {XLENZeros, 8'b0, GPRValue, 3'b0, GPRAddr} :
|
||||
{FPRWen, GPRWen} == 2'b10 ? {FPRValue, 3'b0, FPRAddr, XLENZeros, 8'b0} :
|
||||
'0;
|
||||
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
|
|
@ -116,7 +116,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
|||
for(index = 0; index < MAX_CSRS; index = index + 1) begin
|
||||
// step 3b
|
||||
csrindextoaddr #(TOTAL_CSRS) csrindextoaddr(CSRWenPriorityMatrix[index], CSRAddr[index]);
|
||||
assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]};
|
||||
assign CSRs[(index+1) * (P.XLEN + 16)- 1: index * (P.XLEN + 16)] = {CSRValue[index], 4'b0, CSRAddr[index]};
|
||||
assign EnabledCSRs[index] = |CSRWenPriorityMatrix[index];
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ module rvvitbwrapper import cvw::*; #(parameter cvw_t P,
|
|||
);
|
||||
|
||||
logic valid;
|
||||
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
|
||||
logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
|
||||
|
||||
localparam TOTAL_CSRS = 36;
|
||||
|
||||
|
|
|
|||
|
|
@ -33,22 +33,7 @@ module testbench_fp;
|
|||
parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly
|
||||
parameter string TEST_SIZE="all";
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
`ifdef VERILATOR
|
||||
import "DPI-C" function string getenvval(input string env_name);
|
||||
string WALLY_DIR = getenvval("WALLY");
|
||||
`elsif VCS
|
||||
import "DPI-C" function string getenv(input string env_name);
|
||||
string WALLY_DIR = getenv("WALLY");
|
||||
`else
|
||||
string WALLY_DIR = "$WALLY";
|
||||
`endif
|
||||
|
||||
string FP_TESTS = {WALLY_DIR, "/tests/fp/vectors"};
|
||||
string pp;
|
||||
if (P.IEEE754) assign pp = {FP_TESTS, "/ieee/"};
|
||||
else assign pp = {FP_TESTS, "/riscv/"};
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
parameter MAXVECTORS = 8388610;
|
||||
|
||||
|
|
@ -671,6 +656,7 @@ module testbench_fp;
|
|||
|
||||
// Read the first test
|
||||
initial begin
|
||||
static string pp = `PATH;
|
||||
string testname;
|
||||
string tt0;
|
||||
tt0 = $sformatf("%s", Tests[TestNum]);
|
||||
|
|
@ -1009,7 +995,7 @@ module testbench_fp;
|
|||
// clear the vectors
|
||||
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = '1;
|
||||
// read next files
|
||||
$readmemh({pp, Tests[TestNum]}, TestVectors);
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
// set the vector index back to 0
|
||||
VectorNum = 0;
|
||||
// incemet the operation if all the rounding modes have been tested
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define PATH "../../tests/fp/vectors/"
|
||||
`define ADD_OPCTRL 3'b110
|
||||
`define MUL_OPCTRL 3'b100
|
||||
`define SUB_OPCTRL 3'b111
|
||||
|
|
|
|||
|
|
@ -2,28 +2,35 @@
|
|||
# Floating Point Tests Makefile for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
TESTFLOATS := testfloat/ieee/testfloat_gen testfloat/riscv/testfloat_gen
|
||||
SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC
|
||||
TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
|
||||
|
||||
.PHONY: all vectors combined_IF_vectors testfloat clean
|
||||
.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
|
||||
|
||||
all: vectors combined_IF_vectors
|
||||
|
||||
vectors: ${TESTFLOATS}
|
||||
softfloat: ${SOFTFLOAT_DIR}/softfloat.a
|
||||
|
||||
testfloat: ${TESTFLOAT_DIR}/testfloat_gen
|
||||
|
||||
vectors: testfloat
|
||||
$(MAKE) -C ${WALLY}/tests/fp/vectors
|
||||
|
||||
combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
|
||||
cd ${WALLY}/tests/fp/combined_IF_vectors \
|
||||
&& ./create_IF_vectors.sh
|
||||
|
||||
${TESTFLOATS}: testfloat
|
||||
|
||||
testfloat:
|
||||
$(MAKE) -C testfloat
|
||||
|
||||
clean:
|
||||
$(MAKE) -C vectors clean
|
||||
$(MAKE) -C testfloat clean
|
||||
$(MAKE) -C ${WALLY}/tests/fp/vectors clean
|
||||
$(MAKE) -C ${SOFTFLOAT_DIR} clean
|
||||
$(MAKE) -C ${TESTFLOAT_DIR} clean
|
||||
rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
|
||||
${SOFTFLOAT_DIR}/softfloat.a:
|
||||
$(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR}
|
||||
|
||||
${TESTFLOAT_DIR}/testfloat_gen: ${SOFTFLOAT_DIR}/softfloat.a
|
||||
$(MAKE) -C ${TESTFLOAT_DIR}
|
||||
|
||||
${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
|
||||
@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")
|
||||
|
|
|
|||
|
|
@ -1,47 +0,0 @@
|
|||
# Jordan Carlin, jcarlin@hmc.edu, August 2024
|
||||
# Makefile to generate RISCV and IEEE varaints of Testfloat for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
# Makefile to build testfloat and softfloat executables for IEEE and RISC-V floating point variants
|
||||
|
||||
# Disable parallel execution because both versions of softfloat/testfloat use the same build directory
|
||||
.NOTPARALLEL:
|
||||
.SECONDEXPANSION:
|
||||
|
||||
TESTFLOATS := ieee riscv
|
||||
SOFTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/
|
||||
TESTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC/
|
||||
TESTFLOAT_EXECUTABLES := testfloat testfloat_gen testfloat_ver testsoftfloat timesoftfloat
|
||||
ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(patsubst %,${TESTFLOAT_BUILD_DIR}%,${item}))
|
||||
|
||||
.PHONY: all ieee-softfloat riscv-softfloat ${TESTFLOATS} testfloat clean
|
||||
|
||||
all: riscv ieee
|
||||
|
||||
${TESTFLOATS}: dir_$$@ $$@/testfloat_gen
|
||||
|
||||
.PRECIOUS: %/testfloat_gen
|
||||
%/testfloat_gen:
|
||||
$(MAKE) $*-softfloat
|
||||
$(MAKE) testfloat
|
||||
cp -r ${ORIGINAL_TESTFLOAT_EXECUTABLES} $*/
|
||||
|
||||
ieee-softfloat:
|
||||
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
|
||||
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR)
|
||||
|
||||
riscv-softfloat:
|
||||
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
|
||||
$(MAKE) SPECIALIZE_TYPE=RISCV -C $(SOFTFLOAT_BUILD_DIR)
|
||||
|
||||
testfloat:
|
||||
$(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean
|
||||
$(MAKE) -C $(TESTFLOAT_BUILD_DIR)
|
||||
|
||||
dir_%:
|
||||
mkdir -p $*
|
||||
|
||||
clean:
|
||||
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
|
||||
$(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean
|
||||
rm -f ieee/* riscv/*
|
||||
77
tests/fp/vectors/Makefile
Normal file → Executable file
77
tests/fp/vectors/Makefile
Normal file → Executable file
|
|
@ -1,16 +1,75 @@
|
|||
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
|
||||
# Makefile to generate floating point testvectors for CORE-V-Wally
|
||||
# Makefile to generate RISCV floating point testvectors for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.PHONY: ieee riscv clean
|
||||
all: ieee riscv
|
||||
.DELETE_ON_ERROR:
|
||||
.ONESHELL:
|
||||
SHELL := /bin/bash
|
||||
|
||||
ieee:
|
||||
$(MAKE) -C ieee
|
||||
TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
|
||||
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/testfloat_gen
|
||||
|
||||
riscv:
|
||||
$(MAKE) -C riscv
|
||||
# List of testvectors to generate. Each rounding mode will be generated for each test.
|
||||
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
|
||||
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
|
||||
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
|
||||
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
|
||||
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
|
||||
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
|
||||
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
|
||||
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
|
||||
f16_to_f32 f16_to_f64 f16_to_f128 \
|
||||
f32_to_f16 f32_to_f64 f32_to_f128 \
|
||||
f64_to_f16 f64_to_f32 f64_to_f128 \
|
||||
f128_to_f16 f128_to_f32 f128_to_f64
|
||||
add := f16_add f32_add f64_add f128_add
|
||||
sub := f16_sub f32_sub f64_sub f128_sub
|
||||
mul := f16_mul f32_mul f64_mul f128_mul
|
||||
div := f16_div f32_div f64_div f128_div
|
||||
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
|
||||
eq := f16_eq f32_eq f64_eq f128_eq
|
||||
le := f16_le f32_le f64_le f128_le
|
||||
lt := f16_lt f32_lt f64_lt f128_lt
|
||||
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
|
||||
|
||||
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
|
||||
|
||||
# Set rounding modes and extensions
|
||||
rne: ROUND_MODE := rnear_even
|
||||
rne: ROUND_EXT := rne
|
||||
rz: ROUND_MODE := rminMag
|
||||
rz: ROUND_EXT := rz
|
||||
ru: ROUND_MODE := rmax
|
||||
ru: ROUND_EXT := ru
|
||||
rd: ROUND_MODE := rmin
|
||||
rd: ROUND_EXT := rd
|
||||
rnm: ROUND_MODE := rnear_maxMag
|
||||
rnm: ROUND_EXT := rnm
|
||||
|
||||
.PHONY: all rne rz ru rd rnm clean
|
||||
|
||||
# Generate all test vectors
|
||||
all: rne rz ru rd rnm
|
||||
|
||||
# Generate test vectors for each rounding mode
|
||||
rne: $(addsuffix _rne.tv, $(tests))
|
||||
rz: $(addsuffix _rz.tv, $(tests))
|
||||
ru: $(addsuffix _ru.tv, $(tests))
|
||||
rd: $(addsuffix _rd.tv, $(tests))
|
||||
rnm: $(addsuffix _rnm.tv, $(tests))
|
||||
|
||||
# Rule to generate individual test vectors
|
||||
%.tv: ${TESTFLOAT_GEN}
|
||||
@echo Creating $@ vectors
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
|
||||
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
|
||||
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
# Generate TestFloat first if necessary
|
||||
${TESTFLOAT_GEN}:
|
||||
$(MAKE) -C ${WALLY}/tests/fp testfloat
|
||||
|
||||
clean:
|
||||
$(MAKE) -C ieee clean
|
||||
$(MAKE) -C riscv clean
|
||||
rm -f *.tv
|
||||
rm -f sed*
|
||||
|
|
|
|||
|
|
@ -1,78 +0,0 @@
|
|||
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
|
||||
# Makefile to generate IEEE floating point testvectors for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.DELETE_ON_ERROR:
|
||||
.SECONDEXPANSION:
|
||||
.ONESHELL:
|
||||
# MAKEFLAGS += --no-print-directory
|
||||
|
||||
SHELL := /bin/bash
|
||||
|
||||
VECTOR_TYPE := ieee
|
||||
TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat
|
||||
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen
|
||||
|
||||
# List of testvectors to generate. Each rounding mode will be generated for each test.
|
||||
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
|
||||
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
|
||||
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
|
||||
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
|
||||
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
|
||||
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
|
||||
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
|
||||
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
|
||||
f16_to_f32 f16_to_f64 f16_to_f128 \
|
||||
f32_to_f16 f32_to_f64 f32_to_f128 \
|
||||
f64_to_f16 f64_to_f32 f64_to_f128 \
|
||||
f128_to_f16 f128_to_f32 f128_to_f64
|
||||
add := f16_add f32_add f64_add f128_add
|
||||
sub := f16_sub f32_sub f64_sub f128_sub
|
||||
mul := f16_mul f32_mul f64_mul f128_mul
|
||||
div := f16_div f32_div f64_div f128_div
|
||||
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
|
||||
eq := f16_eq f32_eq f64_eq f128_eq
|
||||
le := f16_le f32_le f64_le f128_le
|
||||
lt := f16_lt f32_lt f64_lt f128_lt
|
||||
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
|
||||
|
||||
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
|
||||
|
||||
# Set rounding modes and extensions
|
||||
rne: ROUND_MODE := rnear_even
|
||||
rne: ROUND_EXT := rne
|
||||
rz: ROUND_MODE := rminMag
|
||||
rz: ROUND_EXT := rz
|
||||
ru: ROUND_MODE := rmax
|
||||
ru: ROUND_EXT := ru
|
||||
rd: ROUND_MODE := rmin
|
||||
rd: ROUND_EXT := rd
|
||||
rnm: ROUND_MODE := rnear_maxMag
|
||||
rnm: ROUND_EXT := rnm
|
||||
|
||||
.PHONY: all rne rz ru rd rnm clean
|
||||
|
||||
all: rne rz ru rd rnm
|
||||
|
||||
# Generate test vectors for each rounding mode
|
||||
rne: $(addsuffix _rne.tv, $(tests))
|
||||
rz: $(addsuffix _rz.tv, $(tests))
|
||||
ru: $(addsuffix _ru.tv, $(tests))
|
||||
rd: $(addsuffix _rd.tv, $(tests))
|
||||
rnm: $(addsuffix _rnm.tv, $(tests))
|
||||
|
||||
# Rule to generate individual test vectors
|
||||
%.tv: ${TESTFLOAT_GEN}
|
||||
@echo "Creating $(VECTOR_TYPE) $@ vectors"
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
|
||||
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
|
||||
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
# Appropriate testfloat_gen must exist
|
||||
${TESTFLOAT_GEN}:
|
||||
$(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE}
|
||||
|
||||
clean:
|
||||
rm -f *.tv
|
||||
rm -f sed*
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
|
||||
# Makefile to generate RISCV floating point testvectors for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.DELETE_ON_ERROR:
|
||||
.SECONDEXPANSION:
|
||||
.ONESHELL:
|
||||
# MAKEFLAGS += --no-print-directory
|
||||
|
||||
SHELL := /bin/bash
|
||||
|
||||
VECTOR_TYPE := riscv
|
||||
TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat
|
||||
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen
|
||||
|
||||
# List of testvectors to generate. Each rounding mode will be generated for each test.
|
||||
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
|
||||
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
|
||||
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
|
||||
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
|
||||
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
|
||||
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
|
||||
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
|
||||
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
|
||||
f16_to_f32 f16_to_f64 f16_to_f128 \
|
||||
f32_to_f16 f32_to_f64 f32_to_f128 \
|
||||
f64_to_f16 f64_to_f32 f64_to_f128 \
|
||||
f128_to_f16 f128_to_f32 f128_to_f64
|
||||
add := f16_add f32_add f64_add f128_add
|
||||
sub := f16_sub f32_sub f64_sub f128_sub
|
||||
mul := f16_mul f32_mul f64_mul f128_mul
|
||||
div := f16_div f32_div f64_div f128_div
|
||||
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
|
||||
eq := f16_eq f32_eq f64_eq f128_eq
|
||||
le := f16_le f32_le f64_le f128_le
|
||||
lt := f16_lt f32_lt f64_lt f128_lt
|
||||
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
|
||||
|
||||
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
|
||||
|
||||
# Set rounding modes and extensions
|
||||
rne: ROUND_MODE := rnear_even
|
||||
rne: ROUND_EXT := rne
|
||||
rz: ROUND_MODE := rminMag
|
||||
rz: ROUND_EXT := rz
|
||||
ru: ROUND_MODE := rmax
|
||||
ru: ROUND_EXT := ru
|
||||
rd: ROUND_MODE := rmin
|
||||
rd: ROUND_EXT := rd
|
||||
rnm: ROUND_MODE := rnear_maxMag
|
||||
rnm: ROUND_EXT := rnm
|
||||
|
||||
.PHONY: all rne rz ru rd rnm clean
|
||||
|
||||
all: rne rz ru rd rnm
|
||||
|
||||
# Generate test vectors for each rounding mode
|
||||
rne: $(addsuffix _rne.tv, $(tests))
|
||||
rz: $(addsuffix _rz.tv, $(tests))
|
||||
ru: $(addsuffix _ru.tv, $(tests))
|
||||
rd: $(addsuffix _rd.tv, $(tests))
|
||||
rnm: $(addsuffix _rnm.tv, $(tests))
|
||||
|
||||
# Rule to generate individual test vectors
|
||||
%.tv: ${TESTFLOAT_GEN}
|
||||
@echo "Creating $(VECTOR_TYPE) $@ vectors"
|
||||
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
|
||||
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
|
||||
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
|
||||
@sed -i 's/ /_/g' $@
|
||||
|
||||
# Appropriate testfloat_gen must exist
|
||||
${TESTFLOAT_GEN}:
|
||||
$(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE}
|
||||
|
||||
clean:
|
||||
rm -f *.tv
|
||||
rm -f sed*
|
||||
Loading…
Add table
Add a link
Reference in a new issue