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Created missing wires for axi interfaces in fpgaTop.v.

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This commit is contained in:
Jacob Pease 2023-01-23 19:02:01 -06:00
parent 293cc88bd9
commit c8d487b9e6
1 changed files with 8 additions and 0 deletions
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8
fpga/src/fpgaTop.v
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@ -226,6 +226,7 @@ module fpgaTop
// 64to32 dwidth converter input interface------------------------- // 64to32 dwidth converter input interface-------------------------
wire s01_axi_aclk; wire s01_axi_aclk;
wire s01_axi_aresetn; wire s01_axi_aresetn;
wire [3:0]s01_axi_awid;
wire [31:0]s01_axi_awaddr; wire [31:0]s01_axi_awaddr;
wire [7:0]s01_axi_awlen; wire [7:0]s01_axi_awlen;
wire [2:0]s01_axi_awsize; wire [2:0]s01_axi_awsize;
@ -242,9 +243,11 @@ module fpgaTop
wire s01_axi_wlast; wire s01_axi_wlast;
wire s01_axi_wvalid; wire s01_axi_wvalid;
wire s01_axi_wready; wire s01_axi_wready;
wire [3:0]m01_axi_bid;
wire [1:0]s01_axi_bresp; wire [1:0]s01_axi_bresp;
wire s01_axi_bvalid; wire s01_axi_bvalid;
wire s01_axi_bready; wire s01_axi_bready;
wire [3:0]m01_axi_bid;
wire [31:0]s01_axi_araddr; wire [31:0]s01_axi_araddr;
wire [7:0]s01_axi_arlen; wire [7:0]s01_axi_arlen;
wire [2:0]s01_axi_arsize; wire [2:0]s01_axi_arsize;
@ -256,6 +259,7 @@ module fpgaTop
wire [3:0]s01_axi_arqos; // wire [3:0]s01_axi_arqos; //
wire s01_axi_arvalid; wire s01_axi_arvalid;
wire s01_axi_arready; wire s01_axi_arready;
wire [3:0]m01_axi_rid;
wire [63:0]s01_axi_rdata; wire [63:0]s01_axi_rdata;
wire [1:0]s01_axi_rresp; wire [1:0]s01_axi_rresp;
wire s01_axi_rlast; wire s01_axi_rlast;
@ -338,6 +342,7 @@ module fpgaTop
wire SDCout_axi_rready; wire SDCout_axi_rready;
// Output Interface // Output Interface
wire [3:0]m01_axi_awid;
wire [31:0]m01_axi_awaddr; wire [31:0]m01_axi_awaddr;
wire [7:0]m01_axi_awlen; wire [7:0]m01_axi_awlen;
wire [2:0]m01_axi_awsize; wire [2:0]m01_axi_awsize;
@ -354,9 +359,11 @@ module fpgaTop
wire m01_axi_wlast; wire m01_axi_wlast;
wire m01_axi_wvalid; wire m01_axi_wvalid;
wire m01_axi_wready; wire m01_axi_wready;
wire [3:0] m01_axi_bid;
wire [1:0]m01_axi_bresp; wire [1:0]m01_axi_bresp;
wire m01_axi_bvalid; wire m01_axi_bvalid;
wire m01_axi_bready; wire m01_axi_bready;
wire [3:0] m01_axi_arid;
wire [31:0]m01_axi_araddr; wire [31:0]m01_axi_araddr;
wire [7:0]m01_axi_arlen; wire [7:0]m01_axi_arlen;
wire [2:0]m01_axi_arsize; wire [2:0]m01_axi_arsize;
@ -368,6 +375,7 @@ module fpgaTop
wire [3:0]m01_axi_arqos; wire [3:0]m01_axi_arqos;
wire m01_axi_arvalid; wire m01_axi_arvalid;
wire m01_axi_arready; wire m01_axi_arready;
wire [3:0] m01_axi_rid;
wire [31:0]m01_axi_rdata; wire [31:0]m01_axi_rdata;
wire [1:0]m01_axi_rresp; wire [1:0]m01_axi_rresp;
wire m01_axi_rlast; wire m01_axi_rlast;