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https://github.com/openhwgroup/cvw.git
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Fixing comments from Jordan
This commit is contained in:
David Harris
parent
1d079dbdc7
commit
c8da70738e
10 changed files with 28 additions and 33 deletions
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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wsim rv32gc $(TARGET).elf --lockstepverbose
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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wsim rv32gc $(TARGET).elf --lockstepverbose
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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wsim rv32gc $(TARGET).elf --lockstepverbose
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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wsim rv32gc $(TARGET).elf --lockstepverbose
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate with Spike
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sim: $(TARGET).elf.objdump
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spike --isa=rv32i_zicsr -d $(TARGET).elf
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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spike --isa=rv32i_zicsr -d $(TARGET).elf
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@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
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riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
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-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
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# simulate in lockstep with ImperasDV
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# simulate in Spike
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sim: $(TARGET).elf.objdump
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wsim rv32gc 8p9.elf --lockstepverbose > log
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@ -49,17 +49,13 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) (
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logic TORMatch, NAMatch;
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logic PAltPMPAdr;
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logic [P.PA_BITS-1:0] PMPAdrFull;
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logic [1:0] AdrMode;
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assign AdrMode = PMPCfg[4:3];
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// Bottom two bits of PMPAdr are 00
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assign PMPAdrFull = {PMPAdr, 2'b00};
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// Top-of-range (TOR)
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// Append two implicit trailing 0's to PMPAdr value
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assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, PMPAdrFull}; // unsigned comparison
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assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, PMPAdr, 2'b00}; // unsigned comparison
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assign PAgePMPAdrOut = ~PAltPMPAdr;
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assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn
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@ -224,7 +224,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
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always_comb begin
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logic [P.XLEN-1:0] pmpaddr;
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pmpaddr = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_PREGRAIN_REGW[i]}; // raw value in PMP registers
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if (PMPCFG_ARRAY_REGW[i][4]) PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:Gm1], {Gm1 {1'b1}}}; // in NAPOT, bottom G-1 bits read as all 1s
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if (PMPCFG_ARRAY_REGW[i][4]) PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:Gm1], {Gm1 {1'b1}}}; // in NAPOT/NA4, bottom G-1 bits read as all 1s (but no bits affected for NA4)
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else PMPADDR_ARRAY_REGW[i] = {pmpaddr[P.PA_BITS-3:P.PMP_G], {P.PMP_G{1'b0}}}; // in TOR/OFF, bottom G bits read as 0s
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end
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@ -28,23 +28,23 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) (
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module trickbox_apb import cvw::*; #(parameter XLEN = 64, NUM_HARTS = 1) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [15:0] PADDR,
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input logic [P.XLEN-1:0] PWDATA,
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input logic [P.XLEN/8-1:0] PSTRB,
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input logic [XLEN-1:0] PWDATA,
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input logic [XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [P.XLEN-1:0] PRDATA,
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output logic [XLEN-1:0] PRDATA,
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output logic PREADY,
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input logic [63:0] MTIME_IN,
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input logic [NUM_HARTS-1:0] MTIP_IN, MSIP_IN, SSIP_IN, MEIP_IN, SEIP_IN,
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input var logic [P.XLEN-1:0] HGEIP_IN[NUM_HARTS-1:0],
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input var logic [XLEN-1:0] HGEIP_IN[NUM_HARTS-1:0],
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output logic [63:0] MTIME_OUT,
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output logic [NUM_HARTS-1:0] MTIP_OUT, MSIP_OUT, SSIP_OUT, MEIP_OUT, SEIP_OUT,
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output var logic [P.XLEN-1:0] HGEIP_OUT[NUM_HARTS-1:0],
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output logic [P.XLEN-1:0] TOHOST_OUT
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output var logic [XLEN-1:0] HGEIP_OUT[NUM_HARTS-1:0],
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output logic [XLEN-1:0] TOHOST_OUT
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);
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// register map
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@ -56,8 +56,8 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) (
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logic [7:0] TRICKEN;
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logic [63:0] MTIME;
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logic [NUM_HARTS-1:0] MTIP, MSIP, SSIP, MEIP, SEIP;
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logic [P.XLEN-1:0] TOHOST;
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logic [P.XLEN-1:0] HGEIP[NUM_HARTS-1:0];
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logic [XLEN-1:0] TOHOST;
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logic [XLEN-1:0] HGEIP[NUM_HARTS-1:0];
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logic [15:0] entry;
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logic [9:0] hart; // which hart is being accessed
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logic memwrite;
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@ -82,16 +82,16 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) (
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10'b0000000001: RD <= '0; // Reading COM1 has no effect; busy bit not yet implemented. Later add busy bit
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10'b0000000010: RD <= {56'b0, TRICKEN};
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10'b1111111111: RD <= MTIME;
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default: RD = '0;
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default: RD <= '0;
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endcase
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3'b110: RD = HGEIP[hart];
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default: RD = '0;
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3'b110: RD <= HGEIP[hart];
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default: RD <= '0;
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endcase
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end
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// word aligned reads
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if (P.XLEN == 64) assign PRDATA = RD;
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else assign PRDATA = RD[PADDR[2]*32 +: 32]; // 32-bit register access to upper or lower half
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if (XLEN == 64) assign PRDATA = RD;
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else assign PRDATA = RD[PADDR[2]*32 +: 32]; // 32-bit register access to upper or lower half
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// write circuitry
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always_ff @(posedge PCLK)
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@ -123,8 +123,8 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) (
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HGEIP[i] <= 0;
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end else if (memwrite & (hart == i)) begin
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if (PADDR[15:13] == 3'b010) begin
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if (P.XLEN == 64) MTIMECMP[hart] <= PWDATA; // 64-bit write
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else MTIMECMP[hart][PADDR[2]*32 +: 32] <= PWDATA; // 32-bit write
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if (XLEN == 64) MTIMECMP[hart] <= PWDATA; // 64-bit write
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else MTIMECMP[hart][PADDR[2]*32 +: 32] <= PWDATA; // 32-bit write
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end else if (PADDR[15:13] == 3'b110) begin
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HGEIP[hart] <= PWDATA;
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end
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@ -134,11 +134,10 @@ module trickbox_apb import cvw::*; #(parameter cvw_t P, NUM_HARTS = 1) (
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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MTIME <= '0;
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// MTIMECMP is not reset
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end else if (memwrite & (PADDR[15:13] == 3'b101 && hart == 10'b1111111111)) begin
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if (P.XLEN == 64) MTIME <= PWDATA; // 64-bit write
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else MTIME <= MTIME[PADDR[2]*32 +: 32]; // 32-bit write
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end else MTIME <= MTIME + 1;
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if (XLEN == 64) MTIME <= PWDATA; // 64-bit write
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else MTIME <= MTIME[PADDR[2]*32 +: 32]; // 32-bit write
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end else MTIME <= MTIME + 1;
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// timer interrupt when MTIME >= MTIMECMP (unsigned)
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for (i=0;i<NUM_HARTS;i++)
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