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Fixing comments from Jordan

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This commit is contained in:
David Harris 2025-06-04 10:42:40 -07:00
parent 1d079dbdc7
commit c8da70738e
10 changed files with 28 additions and 33 deletions
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2
examples/exercises/11p6/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
wsim rv32gc $(TARGET).elf --lockstepverbose

2
examples/exercises/8p3/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
wsim rv32gc $(TARGET).elf --lockstepverbose

2
examples/exercises/8p4/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
wsim rv32gc $(TARGET).elf --lockstepverbose

2
examples/exercises/8p5/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32i_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
wsim rv32gc $(TARGET).elf --lockstepverbose

2
examples/exercises/8p7/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate with Spike
sim: $(TARGET).elf.objdump
spike --isa=rv32i_zicsr -d $(TARGET).elf

2
examples/exercises/8p8/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
spike --isa=rv32i_zicsr -d $(TARGET).elf

2
examples/exercises/8p9/Makefile
View file

@ -7,7 +7,7 @@ $(TARGET).elf: $(TARGET).S Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32im_zicsr -mabi=ilp32 -mcmodel=medany \
-nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
# simulate in lockstep with ImperasDV
# simulate in Spike
sim: $(TARGET).elf.objdump
wsim rv32gc 8p9.elf --lockstepverbose > log